diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index 8c0ebe6f90a6c..f46455a9acedf 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -1838,5 +1838,5 @@ let Predicates = [HasVInstructionsI64, IsRV64] in { } } // Predicates = [HasVInstructionsI64, IsRV64] -include "RISCVInstrInfoZvfbf.td" include "RISCVInstrInfoVPseudos.td" +include "RISCVInstrInfoZvfbf.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index ecde628fc7e21..b4be9e0c09b3e 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -6450,8 +6450,6 @@ defm PseudoVFWMACC : VPseudoVWMAC_VV_VF_RM; defm PseudoVFWNMACC : VPseudoVWMAC_VV_VF_RM; defm PseudoVFWMSAC : VPseudoVWMAC_VV_VF_RM; defm PseudoVFWNMSAC : VPseudoVWMAC_VV_VF_RM; -let Predicates = [HasStdExtZvfbfwma] in -defm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM; } //===----------------------------------------------------------------------===// @@ -6544,7 +6542,6 @@ defm PseudoVFWCVT_F_XU : VPseudoVWCVTF_V; defm PseudoVFWCVT_F_X : VPseudoVWCVTF_V; defm PseudoVFWCVT_F_F : VPseudoVWCVTD_V; -defm PseudoVFWCVTBF16_F_F : VPseudoVWCVTD_V; } // mayRaiseFPException = true //===----------------------------------------------------------------------===// @@ -6561,7 +6558,6 @@ defm PseudoVFNCVT_F_XU : VPseudoVNCVTF_W_RM; defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W_RM; defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W_RM; -defm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM; defm PseudoVFNCVT_ROD_F_F : VPseudoVNCVTD_W; } // mayRaiseFPException = true @@ -7090,9 +7086,6 @@ defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmsac", "PseudoVFWMSAC", AllWidenableFloatVectors, isSEWAware=1>; defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwnmsac", "PseudoVFWNMSAC", AllWidenableFloatVectors, isSEWAware=1>; -let Predicates = [HasStdExtZvfbfwma] in -defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmaccbf16", "PseudoVFWMACCBF16", - AllWidenableBFloatToFloatVectors, isSEWAware=1>; //===----------------------------------------------------------------------===// // 13.8. Vector Floating-Point Square-Root Instruction @@ -7206,8 +7199,6 @@ defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_x_v", "PseudoVFWCVT_F_X", isSEWAware=1>; defm : VPatConversionWF_VF<"int_riscv_vfwcvt_f_f_v", "PseudoVFWCVT_F_F", isSEWAware=1>; -defm : VPatConversionWF_VF_BF<"int_riscv_vfwcvtbf16_f_f_v", - "PseudoVFWCVTBF16_F_F", isSEWAware=1>; //===----------------------------------------------------------------------===// // 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions @@ -7224,8 +7215,6 @@ defm : VPatConversionVF_WI_RM<"int_riscv_vfncvt_f_x_w", "PseudoVFNCVT_F_X", isSEWAware=1>; defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F", AllWidenableFloatVectors, isSEWAware=1>; -defm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w", - "PseudoVFNCVTBF16_F_F", isSEWAware=1>; defm : VPatConversionVF_WF<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F", isSEWAware=1>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td index cc2977c329de1..d4c9215e1863a 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -1315,8 +1315,6 @@ foreach fvti = AllFloatVectors in { // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions defm : VPatWidenFPMulAccSDNode_VV_VF_RM<"PseudoVFWMACC", AllWidenableFloatVectors>; -defm : VPatWidenFPMulAccSDNode_VV_VF_RM<"PseudoVFWMACCBF16", - AllWidenableBFloatToFloatVectors>; defm : VPatWidenFPNegMulAccSDNode_VV_VF_RM<"PseudoVFWNMACC">; defm : VPatWidenFPMulSacSDNode_VV_VF_RM<"PseudoVFWMSAC">; defm : VPatWidenFPNegMulSacSDNode_VV_VF_RM<"PseudoVFWNMSAC">; @@ -1460,20 +1458,6 @@ foreach fvtiToFWti = AllWidenableFloatVectors in { fvti.AVL, fvti.Log2SEW, TA_MA)>; } -foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in { - defvar fvti = fvtiToFWti.Vti; - defvar fwti = fvtiToFWti.Wti; - let Predicates = [HasVInstructionsBF16Minimal] in - def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))), - (!cast("PseudoVFNCVTBF16_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW) - (fvti.Vector (IMPLICIT_DEF)), - fwti.RegClass:$rs1, - // Value to indicate no rounding mode change in - // RISCVInsertReadWriteCSR - FRM_DYN, - fvti.AVL, fvti.Log2SEW, TA_MA)>; -} - //===----------------------------------------------------------------------===// // Vector Element Extracts //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td index 063ee5c5e8b94..ff35c1bd558a4 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -2322,8 +2322,6 @@ defm : VPatFPMulAddVL_VV_VF_RM; // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions defm : VPatWidenFPMulAccVL_VV_VF_RM; -defm : VPatWidenFPMulAccVL_VV_VF_RM; defm : VPatWidenFPMulAccVL_VV_VF_RM; defm : VPatWidenFPMulAccVL_VV_VF_RM; defm : VPatWidenFPMulAccVL_VV_VF_RM; @@ -2541,20 +2539,6 @@ foreach fvtiToFWti = AllWidenableFloatVectors in { GPR:$vl, fvti.Log2SEW, TA_MA)>; } -foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in { - defvar fvti = fvtiToFWti.Vti; - defvar fwti = fvtiToFWti.Wti; - let Predicates = [HasVInstructionsBF16Minimal] in - def : Pat<(fwti.Vector (any_riscv_fpextend_vl - (fvti.Vector fvti.RegClass:$rs1), - (fvti.Mask VMV0:$vm), - VLOpFrag)), - (!cast("PseudoVFWCVTBF16_F_F_V_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK") - (fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, - (fvti.Mask VMV0:$vm), - GPR:$vl, fvti.Log2SEW, TA_MA)>; -} - // 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions defm : VPatNConvertFP2I_RM_VL_W; defm : VPatNConvertFP2I_RM_VL_W; @@ -2596,22 +2580,6 @@ foreach fvtiToFWti = AllWidenableFloatVectors in { } } -foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in { - defvar fvti = fvtiToFWti.Vti; - defvar fwti = fvtiToFWti.Wti; - let Predicates = [HasVInstructionsBF16Minimal] in - def : Pat<(fvti.Vector (any_riscv_fpround_vl - (fwti.Vector fwti.RegClass:$rs1), - (fwti.Mask VMV0:$vm), VLOpFrag)), - (!cast("PseudoVFNCVTBF16_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK") - (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, - (fwti.Mask VMV0:$vm), - // Value to indicate no rounding mode change in - // RISCVInsertReadWriteCSR - FRM_DYN, - GPR:$vl, fvti.Log2SEW, TA_MA)>; -} - // 14. Vector Reduction Operations // 14.1. Vector Single-Width Integer Reduction Instructions diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td index 8f8fcb5d32feb..10614203d3197 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td @@ -32,3 +32,68 @@ let Predicates = [HasStdExtZvfbfwma], DestEEW = EEWSEWx2 in { defm VFWMACCBF16_V : VWMAC_FV_V_F<"vfwmaccbf16", 0b111011>; } + +//===----------------------------------------------------------------------===// +// Pseudo instructions +//===----------------------------------------------------------------------===// +let Predicates = [HasStdExtZvfbfmin] in { + defm PseudoVFWCVTBF16_F_F : VPseudoVWCVTD_V; + defm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM; +} + +let mayRaiseFPException = true, Predicates = [HasStdExtZvfbfwma] in + defm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM; + +//===----------------------------------------------------------------------===// +// Patterns +//===----------------------------------------------------------------------===// +let Predicates = [HasStdExtZvfbfmin] in { + defm : VPatConversionWF_VF_BF<"int_riscv_vfwcvtbf16_f_f_v", + "PseudoVFWCVTBF16_F_F", isSEWAware=1>; + defm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w", + "PseudoVFNCVTBF16_F_F", isSEWAware=1>; + + foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in { + defvar fvti = fvtiToFWti.Vti; + defvar fwti = fvtiToFWti.Wti; + let Predicates = [HasVInstructionsBF16Minimal] in + def : Pat<(fwti.Vector (any_riscv_fpextend_vl + (fvti.Vector fvti.RegClass:$rs1), + (fvti.Mask VMV0:$vm), + VLOpFrag)), + (!cast("PseudoVFWCVTBF16_F_F_V_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK") + (fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, + (fvti.Mask VMV0:$vm), + GPR:$vl, fvti.Log2SEW, TA_MA)>; + + let Predicates = [HasVInstructionsBF16Minimal] in + def : Pat<(fvti.Vector (any_riscv_fpround_vl + (fwti.Vector fwti.RegClass:$rs1), + (fwti.Mask VMV0:$vm), VLOpFrag)), + (!cast("PseudoVFNCVTBF16_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK") + (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, + (fwti.Mask VMV0:$vm), + // Value to indicate no rounding mode change in + // RISCVInsertReadWriteCSR + FRM_DYN, + GPR:$vl, fvti.Log2SEW, TA_MA)>; + let Predicates = [HasVInstructionsBF16Minimal] in + def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))), + (!cast("PseudoVFNCVTBF16_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW) + (fvti.Vector (IMPLICIT_DEF)), + fwti.RegClass:$rs1, + // Value to indicate no rounding mode change in + // RISCVInsertReadWriteCSR + FRM_DYN, + fvti.AVL, fvti.Log2SEW, TA_MA)>; + } +} + +let Predicates = [HasStdExtZvfbfwma] in { + defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmaccbf16", "PseudoVFWMACCBF16", + AllWidenableBFloatToFloatVectors, isSEWAware=1>; + defm : VPatWidenFPMulAccVL_VV_VF_RM; + defm : VPatWidenFPMulAccSDNode_VV_VF_RM<"PseudoVFWMACCBF16", + AllWidenableBFloatToFloatVectors>; +}