From 7fc854320861b4ff2e7bed6387d75b4f030c03c5 Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Tue, 3 Jul 2018 09:48:22 +0000 Subject: [PATCH] [AArch64][SVE] Asm: Support for saturing ADD/SUB instructions. The variants added are: signed Saturating ADD/SUB (immediate) e.g. sqadd z0.h, z0.h, #42 unsigned Saturating ADD/SUB (immediate) e.g. uqadd z0.h, z0.h, #42 signed Saturating ADD/SUB (vectors) e.g. sqadd z0.h, z0.h, z1.h unsigned Saturating ADD/SUB (vectors) e.g. uqadd z0.h, z0.h, z1.h llvm-svn: 336186 --- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 8 ++ llvm/test/MC/AArch64/SVE/sqadd-diagnostics.s | 88 +++++++++++++ llvm/test/MC/AArch64/SVE/sqadd.s | 117 ++++++++++++++++++ llvm/test/MC/AArch64/SVE/sqsub-diagnostics.s | 88 +++++++++++++ llvm/test/MC/AArch64/SVE/sqsub.s | 117 ++++++++++++++++++ llvm/test/MC/AArch64/SVE/uqadd-diagnostics.s | 88 +++++++++++++ llvm/test/MC/AArch64/SVE/uqadd.s | 117 ++++++++++++++++++ llvm/test/MC/AArch64/SVE/uqsub-diagnostics.s | 88 +++++++++++++ llvm/test/MC/AArch64/SVE/uqsub.s | 117 ++++++++++++++++++ 9 files changed, 828 insertions(+) create mode 100644 llvm/test/MC/AArch64/SVE/sqadd-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE/sqadd.s create mode 100644 llvm/test/MC/AArch64/SVE/sqsub-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE/sqsub.s create mode 100644 llvm/test/MC/AArch64/SVE/uqadd-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE/uqadd.s create mode 100644 llvm/test/MC/AArch64/SVE/uqsub-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE/uqsub.s diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index b145526ececae..67659af1c6e68 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -14,6 +14,10 @@ let Predicates = [HasSVE] in { defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add">; defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub">; + defm SQADD_ZZZ : sve_int_bin_cons_arit_0<0b100, "sqadd">; + defm UQADD_ZZZ : sve_int_bin_cons_arit_0<0b101, "uqadd">; + defm SQSUB_ZZZ : sve_int_bin_cons_arit_0<0b110, "sqsub">; + defm UQSUB_ZZZ : sve_int_bin_cons_arit_0<0b111, "uqsub">; def AND_ZZZ : sve_int_bin_cons_log<0b00, "and">; def ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">; @@ -30,6 +34,10 @@ let Predicates = [HasSVE] in { defm ADD_ZI : sve_int_arith_imm0<0b000, "add">; defm SUB_ZI : sve_int_arith_imm0<0b001, "sub">; + defm SQADD_ZI : sve_int_arith_imm0<0b100, "sqadd">; + defm UQADD_ZI : sve_int_arith_imm0<0b101, "uqadd">; + defm SQSUB_ZI : sve_int_arith_imm0<0b110, "sqsub">; + defm UQSUB_ZI : sve_int_arith_imm0<0b111, "uqsub">; defm ORR_ZI : sve_int_log_imm<0b00, "orr", "orn">; defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon">; diff --git a/llvm/test/MC/AArch64/SVE/sqadd-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqadd-diagnostics.s new file mode 100644 index 0000000000000..92672b648a6f6 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/sqadd-diagnostics.s @@ -0,0 +1,88 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// Register z32 does not exist. +sqadd z22.h, z10.h, z32.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: sqadd z22.h, z10.h, z32.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Invalid element kind. +sqadd z20.h, z2.h, z31.x +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier +// CHECK-NEXT: sqadd z20.h, z2.h, z31.x +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Element size specifiers should match. +sqadd z27.h, z11.h, z27.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqadd z27.h, z11.h, z27.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid immediates + +sqadd z0.b, z0.b, #0, lsl #8 // #0, lsl #8 is not valid for .b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: sqadd z0.b, z0.b, #0, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqadd z0.b, z0.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: sqadd z0.b, z0.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqadd z0.b, z0.b, #1, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: sqadd z0.b, z0.b, #1, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqadd z0.b, z0.b, #256 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: sqadd z0.b, z0.b, #256 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqadd z0.h, z0.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqadd z0.h, z0.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqadd z0.h, z0.h, #256, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqadd z0.h, z0.h, #256, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqadd z0.h, z0.h, #65536 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqadd z0.h, z0.h, #65536 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqadd z0.s, z0.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqadd z0.s, z0.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqadd z0.s, z0.s, #256, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqadd z0.s, z0.s, #256, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqadd z0.s, z0.s, #65536 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqadd z0.s, z0.s, #65536 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqadd z0.d, z0.d, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqadd z0.d, z0.d, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqadd z0.d, z0.d, #256, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqadd z0.d, z0.d, #256, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqadd z0.d, z0.d, #65536 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqadd z0.d, z0.d, #65536 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/sqadd.s b/llvm/test/MC/AArch64/SVE/sqadd.s new file mode 100644 index 0000000000000..49abd41a6ade4 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/sqadd.s @@ -0,0 +1,117 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqadd z0.b, z0.b, z0.b +// CHECK-INST: sqadd z0.b, z0.b, z0.b +// CHECK-ENCODING: [0x00,0x10,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 10 20 04 + +sqadd z0.h, z0.h, z0.h +// CHECK-INST: sqadd z0.h, z0.h, z0.h +// CHECK-ENCODING: [0x00,0x10,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 10 60 04 + +sqadd z0.s, z0.s, z0.s +// CHECK-INST: sqadd z0.s, z0.s, z0.s +// CHECK-ENCODING: [0x00,0x10,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 10 a0 04 + +sqadd z0.d, z0.d, z0.d +// CHECK-INST: sqadd z0.d, z0.d, z0.d +// CHECK-ENCODING: [0x00,0x10,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 10 e0 04 + +sqadd z0.b, z0.b, #0 +// CHECK-INST: sqadd z0.b, z0.b, #0 +// CHECK-ENCODING: [0x00,0xc0,0x24,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 24 25 + +sqadd z31.b, z31.b, #255 +// CHECK-INST: sqadd z31.b, z31.b, #255 +// CHECK-ENCODING: [0xff,0xdf,0x24,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff df 24 25 + +sqadd z0.h, z0.h, #0 +// CHECK-INST: sqadd z0.h, z0.h, #0 +// CHECK-ENCODING: [0x00,0xc0,0x64,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 64 25 + +sqadd z0.h, z0.h, #0, lsl #8 +// CHECK-INST: sqadd z0.h, z0.h, #0, lsl #8 +// CHECK-ENCODING: [0x00,0xe0,0x64,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 e0 64 25 + +sqadd z31.h, z31.h, #255, lsl #8 +// CHECK-INST: sqadd z31.h, z31.h, #65280 +// CHECK-ENCODING: [0xff,0xff,0x64,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff 64 25 + +sqadd z31.h, z31.h, #65280 +// CHECK-INST: sqadd z31.h, z31.h, #65280 +// CHECK-ENCODING: [0xff,0xff,0x64,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff 64 25 + +sqadd z0.s, z0.s, #0 +// CHECK-INST: sqadd z0.s, z0.s, #0 +// CHECK-ENCODING: [0x00,0xc0,0xa4,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 a4 25 + +sqadd z0.s, z0.s, #0, lsl #8 +// CHECK-INST: sqadd z0.s, z0.s, #0, lsl #8 +// CHECK-ENCODING: [0x00,0xe0,0xa4,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 e0 a4 25 + +sqadd z31.s, z31.s, #255, lsl #8 +// CHECK-INST: sqadd z31.s, z31.s, #65280 +// CHECK-ENCODING: [0xff,0xff,0xa4,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff a4 25 + +sqadd z31.s, z31.s, #65280 +// CHECK-INST: sqadd z31.s, z31.s, #65280 +// CHECK-ENCODING: [0xff,0xff,0xa4,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff a4 25 + +sqadd z0.d, z0.d, #0 +// CHECK-INST: sqadd z0.d, z0.d, #0 +// CHECK-ENCODING: [0x00,0xc0,0xe4,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 e4 25 + +sqadd z0.d, z0.d, #0, lsl #8 +// CHECK-INST: sqadd z0.d, z0.d, #0, lsl #8 +// CHECK-ENCODING: [0x00,0xe0,0xe4,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 e0 e4 25 + +sqadd z31.d, z31.d, #255, lsl #8 +// CHECK-INST: sqadd z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe4,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e4 25 + +sqadd z31.d, z31.d, #65280 +// CHECK-INST: sqadd z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe4,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e4 25 diff --git a/llvm/test/MC/AArch64/SVE/sqsub-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqsub-diagnostics.s new file mode 100644 index 0000000000000..8155c366c0ab7 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/sqsub-diagnostics.s @@ -0,0 +1,88 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// Register z32 does not exist. +sqsub z22.h, z10.h, z32.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: sqsub z22.h, z10.h, z32.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Invalid element kind. +sqsub z20.h, z2.h, z31.x +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier +// CHECK-NEXT: sqsub z20.h, z2.h, z31.x +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Element size specifiers should match. +sqsub z27.h, z11.h, z27.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqsub z27.h, z11.h, z27.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid immediates + +sqsub z0.b, z0.b, #0, lsl #8 // #0, lsl #8 is not valid for .b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: sqsub z0.b, z0.b, #0, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqsub z0.b, z0.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: sqsub z0.b, z0.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqsub z0.b, z0.b, #1, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: sqsub z0.b, z0.b, #1, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqsub z0.b, z0.b, #256 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: sqsub z0.b, z0.b, #256 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqsub z0.h, z0.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqsub z0.h, z0.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqsub z0.h, z0.h, #256, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqsub z0.h, z0.h, #256, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqsub z0.h, z0.h, #65536 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqsub z0.h, z0.h, #65536 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqsub z0.s, z0.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqsub z0.s, z0.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqsub z0.s, z0.s, #256, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqsub z0.s, z0.s, #256, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqsub z0.s, z0.s, #65536 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqsub z0.s, z0.s, #65536 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqsub z0.d, z0.d, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqsub z0.d, z0.d, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqsub z0.d, z0.d, #256, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqsub z0.d, z0.d, #256, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqsub z0.d, z0.d, #65536 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: sqsub z0.d, z0.d, #65536 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/sqsub.s b/llvm/test/MC/AArch64/SVE/sqsub.s new file mode 100644 index 0000000000000..ad41b5ae41b6c --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/sqsub.s @@ -0,0 +1,117 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqsub z0.b, z0.b, z0.b +// CHECK-INST: sqsub z0.b, z0.b, z0.b +// CHECK-ENCODING: [0x00,0x18,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 18 20 04 + +sqsub z0.h, z0.h, z0.h +// CHECK-INST: sqsub z0.h, z0.h, z0.h +// CHECK-ENCODING: [0x00,0x18,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 18 60 04 + +sqsub z0.s, z0.s, z0.s +// CHECK-INST: sqsub z0.s, z0.s, z0.s +// CHECK-ENCODING: [0x00,0x18,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 18 a0 04 + +sqsub z0.d, z0.d, z0.d +// CHECK-INST: sqsub z0.d, z0.d, z0.d +// CHECK-ENCODING: [0x00,0x18,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 18 e0 04 + +sqsub z0.b, z0.b, #0 +// CHECK-INST: sqsub z0.b, z0.b, #0 +// CHECK-ENCODING: [0x00,0xc0,0x26,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 26 25 + +sqsub z31.b, z31.b, #255 +// CHECK-INST: sqsub z31.b, z31.b, #255 +// CHECK-ENCODING: [0xff,0xdf,0x26,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff df 26 25 + +sqsub z0.h, z0.h, #0 +// CHECK-INST: sqsub z0.h, z0.h, #0 +// CHECK-ENCODING: [0x00,0xc0,0x66,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 66 25 + +sqsub z0.h, z0.h, #0, lsl #8 +// CHECK-INST: sqsub z0.h, z0.h, #0, lsl #8 +// CHECK-ENCODING: [0x00,0xe0,0x66,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 e0 66 25 + +sqsub z31.h, z31.h, #255, lsl #8 +// CHECK-INST: sqsub z31.h, z31.h, #65280 +// CHECK-ENCODING: [0xff,0xff,0x66,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff 66 25 + +sqsub z31.h, z31.h, #65280 +// CHECK-INST: sqsub z31.h, z31.h, #65280 +// CHECK-ENCODING: [0xff,0xff,0x66,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff 66 25 + +sqsub z0.s, z0.s, #0 +// CHECK-INST: sqsub z0.s, z0.s, #0 +// CHECK-ENCODING: [0x00,0xc0,0xa6,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 a6 25 + +sqsub z0.s, z0.s, #0, lsl #8 +// CHECK-INST: sqsub z0.s, z0.s, #0, lsl #8 +// CHECK-ENCODING: [0x00,0xe0,0xa6,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 e0 a6 25 + +sqsub z31.s, z31.s, #255, lsl #8 +// CHECK-INST: sqsub z31.s, z31.s, #65280 +// CHECK-ENCODING: [0xff,0xff,0xa6,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff a6 25 + +sqsub z31.s, z31.s, #65280 +// CHECK-INST: sqsub z31.s, z31.s, #65280 +// CHECK-ENCODING: [0xff,0xff,0xa6,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff a6 25 + +sqsub z0.d, z0.d, #0 +// CHECK-INST: sqsub z0.d, z0.d, #0 +// CHECK-ENCODING: [0x00,0xc0,0xe6,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 e6 25 + +sqsub z0.d, z0.d, #0, lsl #8 +// CHECK-INST: sqsub z0.d, z0.d, #0, lsl #8 +// CHECK-ENCODING: [0x00,0xe0,0xe6,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 e0 e6 25 + +sqsub z31.d, z31.d, #255, lsl #8 +// CHECK-INST: sqsub z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe6,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e6 25 + +sqsub z31.d, z31.d, #65280 +// CHECK-INST: sqsub z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe6,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e6 25 diff --git a/llvm/test/MC/AArch64/SVE/uqadd-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqadd-diagnostics.s new file mode 100644 index 0000000000000..1a6179a14ca5e --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/uqadd-diagnostics.s @@ -0,0 +1,88 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// Register z32 does not exist. +uqadd z22.h, z10.h, z32.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: uqadd z22.h, z10.h, z32.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Invalid element kind. +uqadd z20.h, z2.h, z31.x +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier +// CHECK-NEXT: uqadd z20.h, z2.h, z31.x +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Element size specifiers should match. +uqadd z27.h, z11.h, z27.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqadd z27.h, z11.h, z27.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid immediates + +uqadd z0.b, z0.b, #0, lsl #8 // #0, lsl #8 is not valid for .b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: uqadd z0.b, z0.b, #0, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqadd z0.b, z0.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: uqadd z0.b, z0.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqadd z0.b, z0.b, #1, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: uqadd z0.b, z0.b, #1, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqadd z0.b, z0.b, #256 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: uqadd z0.b, z0.b, #256 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqadd z0.h, z0.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqadd z0.h, z0.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqadd z0.h, z0.h, #256, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqadd z0.h, z0.h, #256, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqadd z0.h, z0.h, #65536 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqadd z0.h, z0.h, #65536 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqadd z0.s, z0.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqadd z0.s, z0.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqadd z0.s, z0.s, #256, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqadd z0.s, z0.s, #256, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqadd z0.s, z0.s, #65536 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqadd z0.s, z0.s, #65536 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqadd z0.d, z0.d, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqadd z0.d, z0.d, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqadd z0.d, z0.d, #256, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqadd z0.d, z0.d, #256, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqadd z0.d, z0.d, #65536 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqadd z0.d, z0.d, #65536 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/uqadd.s b/llvm/test/MC/AArch64/SVE/uqadd.s new file mode 100644 index 0000000000000..fc152297c39c8 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/uqadd.s @@ -0,0 +1,117 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +uqadd z0.b, z0.b, z0.b +// CHECK-INST: uqadd z0.b, z0.b, z0.b +// CHECK-ENCODING: [0x00,0x14,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 14 20 04 + +uqadd z0.h, z0.h, z0.h +// CHECK-INST: uqadd z0.h, z0.h, z0.h +// CHECK-ENCODING: [0x00,0x14,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 14 60 04 + +uqadd z0.s, z0.s, z0.s +// CHECK-INST: uqadd z0.s, z0.s, z0.s +// CHECK-ENCODING: [0x00,0x14,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 14 a0 04 + +uqadd z0.d, z0.d, z0.d +// CHECK-INST: uqadd z0.d, z0.d, z0.d +// CHECK-ENCODING: [0x00,0x14,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 14 e0 04 + +uqadd z0.b, z0.b, #0 +// CHECK-INST: uqadd z0.b, z0.b, #0 +// CHECK-ENCODING: [0x00,0xc0,0x25,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 25 25 + +uqadd z31.b, z31.b, #255 +// CHECK-INST: uqadd z31.b, z31.b, #255 +// CHECK-ENCODING: [0xff,0xdf,0x25,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff df 25 25 + +uqadd z0.h, z0.h, #0 +// CHECK-INST: uqadd z0.h, z0.h, #0 +// CHECK-ENCODING: [0x00,0xc0,0x65,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 65 25 + +uqadd z0.h, z0.h, #0, lsl #8 +// CHECK-INST: uqadd z0.h, z0.h, #0, lsl #8 +// CHECK-ENCODING: [0x00,0xe0,0x65,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 e0 65 25 + +uqadd z31.h, z31.h, #255, lsl #8 +// CHECK-INST: uqadd z31.h, z31.h, #65280 +// CHECK-ENCODING: [0xff,0xff,0x65,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff 65 25 + +uqadd z31.h, z31.h, #65280 +// CHECK-INST: uqadd z31.h, z31.h, #65280 +// CHECK-ENCODING: [0xff,0xff,0x65,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff 65 25 + +uqadd z0.s, z0.s, #0 +// CHECK-INST: uqadd z0.s, z0.s, #0 +// CHECK-ENCODING: [0x00,0xc0,0xa5,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 a5 25 + +uqadd z0.s, z0.s, #0, lsl #8 +// CHECK-INST: uqadd z0.s, z0.s, #0, lsl #8 +// CHECK-ENCODING: [0x00,0xe0,0xa5,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 e0 a5 25 + +uqadd z31.s, z31.s, #255, lsl #8 +// CHECK-INST: uqadd z31.s, z31.s, #65280 +// CHECK-ENCODING: [0xff,0xff,0xa5,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff a5 25 + +uqadd z31.s, z31.s, #65280 +// CHECK-INST: uqadd z31.s, z31.s, #65280 +// CHECK-ENCODING: [0xff,0xff,0xa5,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff a5 25 + +uqadd z0.d, z0.d, #0 +// CHECK-INST: uqadd z0.d, z0.d, #0 +// CHECK-ENCODING: [0x00,0xc0,0xe5,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 e5 25 + +uqadd z0.d, z0.d, #0, lsl #8 +// CHECK-INST: uqadd z0.d, z0.d, #0, lsl #8 +// CHECK-ENCODING: [0x00,0xe0,0xe5,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 e0 e5 25 + +uqadd z31.d, z31.d, #255, lsl #8 +// CHECK-INST: uqadd z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe5,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e5 25 + +uqadd z31.d, z31.d, #65280 +// CHECK-INST: uqadd z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe5,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e5 25 diff --git a/llvm/test/MC/AArch64/SVE/uqsub-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqsub-diagnostics.s new file mode 100644 index 0000000000000..566334ceea8d3 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/uqsub-diagnostics.s @@ -0,0 +1,88 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// Register z32 does not exist. +uqsub z22.h, z10.h, z32.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: uqsub z22.h, z10.h, z32.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Invalid element kind. +uqsub z20.h, z2.h, z31.x +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier +// CHECK-NEXT: uqsub z20.h, z2.h, z31.x +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Element size specifiers should match. +uqsub z27.h, z11.h, z27.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqsub z27.h, z11.h, z27.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid immediates + +uqsub z0.b, z0.b, #0, lsl #8 // #0, lsl #8 is not valid for .b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: uqsub z0.b, z0.b, #0, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqsub z0.b, z0.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: uqsub z0.b, z0.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqsub z0.b, z0.b, #1, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: uqsub z0.b, z0.b, #1, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqsub z0.b, z0.b, #256 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0 +// CHECK-NEXT: uqsub z0.b, z0.b, #256 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqsub z0.h, z0.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqsub z0.h, z0.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqsub z0.h, z0.h, #256, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqsub z0.h, z0.h, #256, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqsub z0.h, z0.h, #65536 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqsub z0.h, z0.h, #65536 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqsub z0.s, z0.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqsub z0.s, z0.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqsub z0.s, z0.s, #256, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqsub z0.s, z0.s, #256, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqsub z0.s, z0.s, #65536 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqsub z0.s, z0.s, #65536 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqsub z0.d, z0.d, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqsub z0.d, z0.d, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqsub z0.d, z0.d, #256, lsl #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqsub z0.d, z0.d, #256, lsl #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqsub z0.d, z0.d, #65536 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] +// CHECK-NEXT: uqsub z0.d, z0.d, #65536 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/uqsub.s b/llvm/test/MC/AArch64/SVE/uqsub.s new file mode 100644 index 0000000000000..4fb90cae9ee72 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/uqsub.s @@ -0,0 +1,117 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +uqsub z0.b, z0.b, z0.b +// CHECK-INST: uqsub z0.b, z0.b, z0.b +// CHECK-ENCODING: [0x00,0x1c,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 1c 20 04 + +uqsub z0.h, z0.h, z0.h +// CHECK-INST: uqsub z0.h, z0.h, z0.h +// CHECK-ENCODING: [0x00,0x1c,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 1c 60 04 + +uqsub z0.s, z0.s, z0.s +// CHECK-INST: uqsub z0.s, z0.s, z0.s +// CHECK-ENCODING: [0x00,0x1c,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 1c a0 04 + +uqsub z0.d, z0.d, z0.d +// CHECK-INST: uqsub z0.d, z0.d, z0.d +// CHECK-ENCODING: [0x00,0x1c,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 1c e0 04 + +uqsub z0.b, z0.b, #0 +// CHECK-INST: uqsub z0.b, z0.b, #0 +// CHECK-ENCODING: [0x00,0xc0,0x27,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 27 25 + +uqsub z31.b, z31.b, #255 +// CHECK-INST: uqsub z31.b, z31.b, #255 +// CHECK-ENCODING: [0xff,0xdf,0x27,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff df 27 25 + +uqsub z0.h, z0.h, #0 +// CHECK-INST: uqsub z0.h, z0.h, #0 +// CHECK-ENCODING: [0x00,0xc0,0x67,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 67 25 + +uqsub z0.h, z0.h, #0, lsl #8 +// CHECK-INST: uqsub z0.h, z0.h, #0, lsl #8 +// CHECK-ENCODING: [0x00,0xe0,0x67,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 e0 67 25 + +uqsub z31.h, z31.h, #255, lsl #8 +// CHECK-INST: uqsub z31.h, z31.h, #65280 +// CHECK-ENCODING: [0xff,0xff,0x67,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff 67 25 + +uqsub z31.h, z31.h, #65280 +// CHECK-INST: uqsub z31.h, z31.h, #65280 +// CHECK-ENCODING: [0xff,0xff,0x67,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff 67 25 + +uqsub z0.s, z0.s, #0 +// CHECK-INST: uqsub z0.s, z0.s, #0 +// CHECK-ENCODING: [0x00,0xc0,0xa7,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 a7 25 + +uqsub z0.s, z0.s, #0, lsl #8 +// CHECK-INST: uqsub z0.s, z0.s, #0, lsl #8 +// CHECK-ENCODING: [0x00,0xe0,0xa7,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 e0 a7 25 + +uqsub z31.s, z31.s, #255, lsl #8 +// CHECK-INST: uqsub z31.s, z31.s, #65280 +// CHECK-ENCODING: [0xff,0xff,0xa7,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff a7 25 + +uqsub z31.s, z31.s, #65280 +// CHECK-INST: uqsub z31.s, z31.s, #65280 +// CHECK-ENCODING: [0xff,0xff,0xa7,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff a7 25 + +uqsub z0.d, z0.d, #0 +// CHECK-INST: uqsub z0.d, z0.d, #0 +// CHECK-ENCODING: [0x00,0xc0,0xe7,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 e7 25 + +uqsub z0.d, z0.d, #0, lsl #8 +// CHECK-INST: uqsub z0.d, z0.d, #0, lsl #8 +// CHECK-ENCODING: [0x00,0xe0,0xe7,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 e0 e7 25 + +uqsub z31.d, z31.d, #255, lsl #8 +// CHECK-INST: uqsub z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe7,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e7 25 + +uqsub z31.d, z31.d, #65280 +// CHECK-INST: uqsub z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe7,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e7 25