diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 295e25969663c..834fa9ea8f57f 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -9441,7 +9441,8 @@ void VPReductionRecipe::execute(VPTransformState &State) { for (unsigned Part = 0; Part < State.UF; ++Part) { Value *NewVecOp = State.get(getVecOp(), Part); if (VPValue *Cond = getCondOp()) { - Value *NewCond = State.get(Cond, Part); + Value *NewCond = State.VF.isVector() ? State.get(Cond, Part) + : State.get(Cond, {Part, 0}); VectorType *VecTy = dyn_cast(NewVecOp->getType()); Type *ElementTy = VecTy ? VecTy->getElementType() : NewVecOp->getType(); Value *Iden = RdxDesc.getRecurrenceIdentity(Kind, ElementTy, diff --git a/llvm/test/Transforms/LoopVectorize/strict-fadd-interleave-only.ll b/llvm/test/Transforms/LoopVectorize/strict-fadd-interleave-only.ll index 1222ab2580f6a..452fa9fa8c8e5 100644 --- a/llvm/test/Transforms/LoopVectorize/strict-fadd-interleave-only.ll +++ b/llvm/test/Transforms/LoopVectorize/strict-fadd-interleave-only.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 ; RUN: opt -passes=loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -force-vector-interleave=2 -force-vector-width=1 -force-ordered-reductions -S %s | FileCheck %s +; RUN: opt -passes=loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -force-vector-interleave=2 -force-vector-width=1 -force-ordered-reductions -force-tail-folding-style=data -S %s | FileCheck --check-prefix=CHECK-ALM %s define float @pr70988() { ; CHECK-LABEL: define float @pr70988() { @@ -38,6 +39,44 @@ define float @pr70988() { ; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi float [ [[RDX_NEXT]], [[LOOP]] ], [ [[TMP5]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: ret float [[DOTLCSSA]] ; +; CHECK-ALM-LABEL: define float @pr70988() { +; CHECK-ALM-NEXT: entry: +; CHECK-ALM-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; CHECK-ALM: vector.ph: +; CHECK-ALM-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK-ALM: vector.body: +; CHECK-ALM-NEXT: [[INDEX1:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT3:%.*]], [[VECTOR_BODY]] ] +; CHECK-ALM-NEXT: [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, [[VECTOR_PH]] ], [ [[TMP7:%.*]], [[VECTOR_BODY]] ] +; CHECK-ALM-NEXT: [[TMP0:%.*]] = add i32 [[INDEX1]], 0 +; CHECK-ALM-NEXT: [[TMP1:%.*]] = add i32 [[INDEX1]], 1 +; CHECK-ALM-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <1 x i1> @llvm.get.active.lane.mask.v1i1.i32(i32 [[TMP0]], i32 1021) +; CHECK-ALM-NEXT: [[ACTIVE_LANE_MASK2:%.*]] = call <1 x i1> @llvm.get.active.lane.mask.v1i1.i32(i32 [[TMP1]], i32 1021) +; CHECK-ALM-NEXT: [[TMP2:%.*]] = extractelement <1 x i1> [[ACTIVE_LANE_MASK]], i32 0 +; CHECK-ALM-NEXT: [[TMP3:%.*]] = select contract i1 [[TMP2]], float 1.000000e+00, float -0.000000e+00 +; CHECK-ALM-NEXT: [[TMP4:%.*]] = fadd contract float [[VEC_PHI]], [[TMP3]] +; CHECK-ALM-NEXT: [[TMP5:%.*]] = extractelement <1 x i1> [[ACTIVE_LANE_MASK2]], i32 0 +; CHECK-ALM-NEXT: [[TMP6:%.*]] = select contract i1 [[TMP5]], float 1.000000e+00, float -0.000000e+00 +; CHECK-ALM-NEXT: [[TMP7]] = fadd contract float [[TMP4]], [[TMP6]] +; CHECK-ALM-NEXT: [[INDEX_NEXT3]] = add i32 [[INDEX1]], 2 +; CHECK-ALM-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT3]], 1022 +; CHECK-ALM-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK-ALM: middle.block: +; CHECK-ALM-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK-ALM: scalar.ph: +; CHECK-ALM-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 1022, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-ALM-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[TMP7]], [[MIDDLE_BLOCK]] ] +; CHECK-ALM-NEXT: br label [[LOOP:%.*]] +; CHECK-ALM: loop: +; CHECK-ALM-NEXT: [[INDEX:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDEX_NEXT:%.*]], [[LOOP]] ] +; CHECK-ALM-NEXT: [[RDX:%.*]] = phi float [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[RDX_NEXT:%.*]], [[LOOP]] ] +; CHECK-ALM-NEXT: [[RDX_NEXT]] = fadd contract float [[RDX]], 1.000000e+00 +; CHECK-ALM-NEXT: [[INDEX_NEXT]] = add nuw nsw i32 [[INDEX]], 1 +; CHECK-ALM-NEXT: [[COND:%.*]] = icmp ult i32 [[INDEX_NEXT]], 1021 +; CHECK-ALM-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP3:![0-9]+]] +; CHECK-ALM: exit: +; CHECK-ALM-NEXT: [[DOTLCSSA:%.*]] = phi float [ [[RDX_NEXT]], [[LOOP]] ], [ [[TMP7]], [[MIDDLE_BLOCK]] ] +; CHECK-ALM-NEXT: ret float [[DOTLCSSA]] +; entry: br label %loop @@ -53,3 +92,134 @@ exit: %.lcssa = phi float [ %rdx.next, %loop ] ret float %.lcssa } + +define float @pr72720reduction_using_active_lane_mask(ptr %src) { +; CHECK-LABEL: define float @pr72720reduction_using_active_lane_mask( +; CHECK-SAME: ptr [[SRC:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_LOAD_CONTINUE3:%.*]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, [[VECTOR_PH]] ], [ [[TMP13:%.*]], [[PRED_LOAD_CONTINUE3]] ] +; CHECK-NEXT: [[VEC_IV:%.*]] = add i32 [[INDEX]], 0 +; CHECK-NEXT: [[VEC_IV1:%.*]] = add i32 [[INDEX]], 1 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ule i32 [[VEC_IV]], 14 +; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[VEC_IV1]], 14 +; CHECK-NEXT: br i1 [[TMP0]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]] +; CHECK: pred.load.if: +; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[INDEX]], 0 +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr float, ptr [[SRC]], i32 [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = load float, ptr [[TMP3]], align 4 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE]] +; CHECK: pred.load.continue: +; CHECK-NEXT: [[TMP5:%.*]] = phi float [ poison, [[VECTOR_BODY]] ], [ [[TMP4]], [[PRED_LOAD_IF]] ] +; CHECK-NEXT: br i1 [[TMP1]], label [[PRED_LOAD_IF2:%.*]], label [[PRED_LOAD_CONTINUE3]] +; CHECK: pred.load.if2: +; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[INDEX]], 1 +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr float, ptr [[SRC]], i32 [[TMP6]] +; CHECK-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP7]], align 4 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE3]] +; CHECK: pred.load.continue3: +; CHECK-NEXT: [[TMP9:%.*]] = phi float [ poison, [[PRED_LOAD_CONTINUE]] ], [ [[TMP8]], [[PRED_LOAD_IF2]] ] +; CHECK-NEXT: [[TMP10:%.*]] = select contract i1 [[TMP0]], float [[TMP5]], float -0.000000e+00 +; CHECK-NEXT: [[TMP11:%.*]] = fadd contract float [[VEC_PHI]], [[TMP10]] +; CHECK-NEXT: [[TMP12:%.*]] = select contract i1 [[TMP1]], float [[TMP9]], float -0.000000e+00 +; CHECK-NEXT: [[TMP13]] = fadd contract float [[TMP11]], [[TMP12]] +; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 2 +; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[INDEX_NEXT]], 16 +; CHECK-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 16, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[TMP13]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[NARROW:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[RDX:%.*]] = phi float [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[RDX_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[NARROW]] = add nuw nsw i32 [[IV]], 1 +; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i32 [[IV]] +; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4 +; CHECK-NEXT: [[RDX_NEXT]] = fadd contract float [[RDX]], [[L]] +; CHECK-NEXT: [[EC:%.*]] = icmp ult i32 [[NARROW]], 15 +; CHECK-NEXT: br i1 [[EC]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP5:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi float [ [[RDX_NEXT]], [[LOOP]] ], [ [[TMP13]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: ret float [[DOTLCSSA]] +; +; CHECK-ALM-LABEL: define float @pr72720reduction_using_active_lane_mask( +; CHECK-ALM-SAME: ptr [[SRC:%.*]]) { +; CHECK-ALM-NEXT: entry: +; CHECK-ALM-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; CHECK-ALM: vector.ph: +; CHECK-ALM-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK-ALM: vector.body: +; CHECK-ALM-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_LOAD_CONTINUE3:%.*]] ] +; CHECK-ALM-NEXT: [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, [[VECTOR_PH]] ], [ [[TMP15:%.*]], [[PRED_LOAD_CONTINUE3]] ] +; CHECK-ALM-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0 +; CHECK-ALM-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 1 +; CHECK-ALM-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <1 x i1> @llvm.get.active.lane.mask.v1i1.i32(i32 [[TMP0]], i32 15) +; CHECK-ALM-NEXT: [[ACTIVE_LANE_MASK1:%.*]] = call <1 x i1> @llvm.get.active.lane.mask.v1i1.i32(i32 [[TMP1]], i32 15) +; CHECK-ALM-NEXT: [[TMP2:%.*]] = extractelement <1 x i1> [[ACTIVE_LANE_MASK]], i32 0 +; CHECK-ALM-NEXT: br i1 [[TMP2]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]] +; CHECK-ALM: pred.load.if: +; CHECK-ALM-NEXT: [[TMP3:%.*]] = getelementptr float, ptr [[SRC]], i32 [[TMP0]] +; CHECK-ALM-NEXT: [[TMP4:%.*]] = load float, ptr [[TMP3]], align 4 +; CHECK-ALM-NEXT: br label [[PRED_LOAD_CONTINUE]] +; CHECK-ALM: pred.load.continue: +; CHECK-ALM-NEXT: [[TMP5:%.*]] = phi float [ poison, [[VECTOR_BODY]] ], [ [[TMP4]], [[PRED_LOAD_IF]] ] +; CHECK-ALM-NEXT: [[TMP6:%.*]] = extractelement <1 x i1> [[ACTIVE_LANE_MASK1]], i32 0 +; CHECK-ALM-NEXT: br i1 [[TMP6]], label [[PRED_LOAD_IF2:%.*]], label [[PRED_LOAD_CONTINUE3]] +; CHECK-ALM: pred.load.if2: +; CHECK-ALM-NEXT: [[TMP7:%.*]] = getelementptr float, ptr [[SRC]], i32 [[TMP1]] +; CHECK-ALM-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP7]], align 4 +; CHECK-ALM-NEXT: br label [[PRED_LOAD_CONTINUE3]] +; CHECK-ALM: pred.load.continue3: +; CHECK-ALM-NEXT: [[TMP9:%.*]] = phi float [ poison, [[PRED_LOAD_CONTINUE]] ], [ [[TMP8]], [[PRED_LOAD_IF2]] ] +; CHECK-ALM-NEXT: [[TMP10:%.*]] = extractelement <1 x i1> [[ACTIVE_LANE_MASK]], i32 0 +; CHECK-ALM-NEXT: [[TMP11:%.*]] = select contract i1 [[TMP10]], float [[TMP5]], float -0.000000e+00 +; CHECK-ALM-NEXT: [[TMP12:%.*]] = fadd contract float [[VEC_PHI]], [[TMP11]] +; CHECK-ALM-NEXT: [[TMP13:%.*]] = extractelement <1 x i1> [[ACTIVE_LANE_MASK1]], i32 0 +; CHECK-ALM-NEXT: [[TMP14:%.*]] = select contract i1 [[TMP13]], float [[TMP9]], float -0.000000e+00 +; CHECK-ALM-NEXT: [[TMP15]] = fadd contract float [[TMP12]], [[TMP14]] +; CHECK-ALM-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 2 +; CHECK-ALM-NEXT: [[TMP16:%.*]] = icmp eq i32 [[INDEX_NEXT]], 16 +; CHECK-ALM-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; CHECK-ALM: middle.block: +; CHECK-ALM-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK-ALM: scalar.ph: +; CHECK-ALM-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 16, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-ALM-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[TMP15]], [[MIDDLE_BLOCK]] ] +; CHECK-ALM-NEXT: br label [[LOOP:%.*]] +; CHECK-ALM: loop: +; CHECK-ALM-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[NARROW:%.*]], [[LOOP]] ] +; CHECK-ALM-NEXT: [[RDX:%.*]] = phi float [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[RDX_NEXT:%.*]], [[LOOP]] ] +; CHECK-ALM-NEXT: [[NARROW]] = add nuw nsw i32 [[IV]], 1 +; CHECK-ALM-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i32 [[IV]] +; CHECK-ALM-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4 +; CHECK-ALM-NEXT: [[RDX_NEXT]] = fadd contract float [[RDX]], [[L]] +; CHECK-ALM-NEXT: [[EC:%.*]] = icmp ult i32 [[NARROW]], 15 +; CHECK-ALM-NEXT: br i1 [[EC]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP5:![0-9]+]] +; CHECK-ALM: exit: +; CHECK-ALM-NEXT: [[DOTLCSSA:%.*]] = phi float [ [[RDX_NEXT]], [[LOOP]] ], [ [[TMP15]], [[MIDDLE_BLOCK]] ] +; CHECK-ALM-NEXT: ret float [[DOTLCSSA]] +; +entry: + br label %loop + +loop: + %iv = phi i32 [ 0, %entry ], [ %narrow, %loop ] + %rdx = phi float [ 0.0, %entry ], [ %rdx.next, %loop ] + %narrow = add nuw nsw i32 %iv, 1 + %gep = getelementptr float, ptr %src, i32 %iv + %l = load float, ptr %gep, align 4 + %rdx.next = fadd contract float %rdx, %l + %ec = icmp ult i32 %narrow, 15 + br i1 %ec, label %loop, label %exit + +exit: + %.lcssa = phi float [ %rdx.next, %loop ] + ret float %.lcssa +}