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[AMDGPU][MC] Add detection of mandatory literals in parser
Differential Revision: https://reviews.llvm.org/D133606
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dpreobra committed Sep 13, 2022
1 parent 5a7764c commit 815ba49
Showing 1 changed file with 46 additions and 8 deletions.
54 changes: 46 additions & 8 deletions llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Expand Up @@ -166,9 +166,17 @@ class AMDGPUOperand : public MCParsedAsmOperand {
ImmTyWaitEXP,
};

// Immediate operand kind.
// It helps to identify the location of an offending operand after an error.
// Note that regular literals and mandatory literals (KImm) must be handled
// differently. When looking for an offending operand, we should usually
// ignore mandatory literals because they are part of the instruction and
// cannot be changed. Report location of mandatory operands only for VOPD,
// when both OpX and OpY have a KImm and there are no other literals.
enum ImmKindTy {
ImmKindTyNone,
ImmKindTyLiteral,
ImmKindTyMandatoryLiteral,
ImmKindTyConst,
};

Expand Down Expand Up @@ -228,6 +236,11 @@ class AMDGPUOperand : public MCParsedAsmOperand {
Imm.Kind = ImmKindTyLiteral;
}

void setImmKindMandatoryLiteral() const {
assert(isImm());
Imm.Kind = ImmKindTyMandatoryLiteral;
}

void setImmKindConst() const {
assert(isImm());
Imm.Kind = ImmKindTyConst;
Expand All @@ -237,6 +250,10 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return isImm() && Imm.Kind == ImmKindTyLiteral;
}

bool IsImmKindMandatoryLiteral() const {
return isImm() && Imm.Kind == ImmKindTyMandatoryLiteral;
}

bool isImmKindConst() const {
return isImm() && Imm.Kind == ImmKindTyConst;
}
Expand Down Expand Up @@ -1619,8 +1636,11 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
const OperandVector &Operands) const;
SMLoc getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const;
SMLoc getRegLoc(unsigned Reg, const OperandVector &Operands) const;
SMLoc getLitLoc(const OperandVector &Operands) const;
SMLoc getLitLoc(const OperandVector &Operands,
bool SearchMandatoryLiterals = false) const;
SMLoc getMandatoryLitLoc(const OperandVector &Operands) const;
SMLoc getConstLoc(const OperandVector &Operands) const;
SMLoc getInstLoc(const OperandVector &Operands) const;

bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
Expand Down Expand Up @@ -2173,7 +2193,11 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo

uint64_t ImmVal = FPLiteral.bitcastToAPInt().getZExtValue();
Inst.addOperand(MCOperand::createImm(ImmVal));
setImmKindLiteral();
if (OpTy == AMDGPU::OPERAND_KIMM32 || OpTy == AMDGPU::OPERAND_KIMM16) {
setImmKindMandatoryLiteral();
} else {
setImmKindLiteral();
}
return;
}
default:
Expand Down Expand Up @@ -2258,11 +2282,11 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
}
case AMDGPU::OPERAND_KIMM32:
Inst.addOperand(MCOperand::createImm(Literal.getLoBits(32).getZExtValue()));
setImmKindNone();
setImmKindMandatoryLiteral();
return;
case AMDGPU::OPERAND_KIMM16:
Inst.addOperand(MCOperand::createImm(Literal.getLoBits(16).getZExtValue()));
setImmKindNone();
setImmKindMandatoryLiteral();
return;
default:
llvm_unreachable("invalid operand size");
Expand All @@ -2272,7 +2296,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
template <unsigned Bitwidth>
void AMDGPUOperand::addKImmFPOperands(MCInst &Inst, unsigned N) const {
APInt Literal(64, Imm.Val);
setImmKindNone();
setImmKindMandatoryLiteral();

if (!Imm.IsFPImm) {
// We got int literal token.
Expand Down Expand Up @@ -7170,6 +7194,10 @@ AMDGPUAsmParser::lex() {
Parser.Lex();
}

SMLoc AMDGPUAsmParser::getInstLoc(const OperandVector &Operands) const {
return ((AMDGPUOperand &)*Operands[0]).getStartLoc();
}

SMLoc
AMDGPUAsmParser::getOperandLoc(std::function<bool(const AMDGPUOperand&)> Test,
const OperandVector &Operands) const {
Expand All @@ -7178,7 +7206,7 @@ AMDGPUAsmParser::getOperandLoc(std::function<bool(const AMDGPUOperand&)> Test,
if (Test(Op))
return Op.getStartLoc();
}
return ((AMDGPUOperand &)*Operands[0]).getStartLoc();
return getInstLoc(Operands);
}

SMLoc
Expand All @@ -7197,11 +7225,21 @@ AMDGPUAsmParser::getRegLoc(unsigned Reg,
return getOperandLoc(Test, Operands);
}

SMLoc
AMDGPUAsmParser::getLitLoc(const OperandVector &Operands) const {
SMLoc AMDGPUAsmParser::getLitLoc(const OperandVector &Operands,
bool SearchMandatoryLiterals) const {
auto Test = [](const AMDGPUOperand& Op) {
return Op.IsImmKindLiteral() || Op.isExpr();
};
SMLoc Loc = getOperandLoc(Test, Operands);
if (SearchMandatoryLiterals && Loc == getInstLoc(Operands))
Loc = getMandatoryLitLoc(Operands);
return Loc;
}

SMLoc AMDGPUAsmParser::getMandatoryLitLoc(const OperandVector &Operands) const {
auto Test = [](const AMDGPUOperand &Op) {
return Op.IsImmKindMandatoryLiteral();
};
return getOperandLoc(Test, Operands);
}

Expand Down

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