diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index c2206b77d8ad8..fa5ba2efc8a8c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -20716,7 +20716,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
               TypeSize::isKnownLE(ST1->getMemoryVT().getStoreSize(),
                                   ST->getMemoryVT().getStoreSize())) {
             CombineTo(ST1, ST1->getChain());
-            return SDValue();
+            return SDValue(N, 0);
           }
         } else {
           const BaseIndexOffset STBase = BaseIndexOffset::match(ST, DAG);
@@ -20729,7 +20729,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
                               ChainBase,
                               ST1->getMemoryVT().getFixedSizeInBits())) {
             CombineTo(ST1, ST1->getChain());
-            return SDValue();
+            return SDValue(N, 0);
           }
         }
       }
diff --git a/llvm/test/CodeGen/RISCV/pr64772.ll b/llvm/test/CodeGen/RISCV/pr64772.ll
new file mode 100644
index 0000000000000..bbc6a90762dbc
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr64772.ll
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
+
+define void @f() {
+; CHECK-LABEL: f:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sb zero, 0(zero)
+; CHECK-NEXT:    ret
+  %B1 = shl i64 -9223372036854775808, 0
+  %LGV6 = load i8, ptr null, align 1
+  %G3 = getelementptr i32, ptr null, i64 %B1
+  %B5 = ashr i64 -9223372036854775808, 0
+  store i1 false, ptr %G3, align 1
+  store i8 1, ptr null, align 1
+  store i1 false, ptr null, align 1
+  ret void
+}