diff --git a/llvm/lib/Analysis/MemorySSAUpdater.cpp b/llvm/lib/Analysis/MemorySSAUpdater.cpp index 0eb338383c5616..d7ebe0e884e03e 100644 --- a/llvm/lib/Analysis/MemorySSAUpdater.cpp +++ b/llvm/lib/Analysis/MemorySSAUpdater.cpp @@ -491,8 +491,7 @@ void MemorySSAUpdater::fixupDefs(const SmallVectorImpl &Vars) { } while (!Worklist.empty()) { - const BasicBlock *FixupBlock = Worklist.back(); - Worklist.pop_back(); + const BasicBlock *FixupBlock = Worklist.pop_back_val(); // Get the first def in the block that isn't a phi node. if (auto *Defs = MSSA->getWritableBlockDefs(FixupBlock)) { diff --git a/llvm/lib/Analysis/StackSafetyAnalysis.cpp b/llvm/lib/Analysis/StackSafetyAnalysis.cpp index 9f22b27b45408a..0e981d123b7bdd 100644 --- a/llvm/lib/Analysis/StackSafetyAnalysis.cpp +++ b/llvm/lib/Analysis/StackSafetyAnalysis.cpp @@ -600,8 +600,7 @@ void StackSafetyDataFlowAnalysis::runDataFlow() { updateAllNodes(); while (!WorkList.empty()) { - const CalleeTy *Callee = WorkList.back(); - WorkList.pop_back(); + const CalleeTy *Callee = WorkList.pop_back_val(); updateOneNode(Callee); } } diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index 4a0a1d93d46456..365e25263ce805 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -5112,8 +5112,7 @@ bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr, TypePromotionTransaction::ConstRestorationPt LastKnownGood = TPT.getRestorationPoint(); while (!worklist.empty()) { - Value *V = worklist.back(); - worklist.pop_back(); + Value *V = worklist.pop_back_val(); // We allow traversing cyclic Phi nodes. // In case of success after this loop we ensure that traversing through @@ -6465,8 +6464,7 @@ bool CodeGenPrepare::optimizeLoadExt(LoadInst *Load) { APInt WidestAndBits(BitWidth, 0); while (!WorkList.empty()) { - Instruction *I = WorkList.back(); - WorkList.pop_back(); + Instruction *I = WorkList.pop_back_val(); // Break use-def graph loops. if (!Visited.insert(I).second) diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 34b1b3faec895f..c7d1c538533727 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -740,8 +740,7 @@ bool IRTranslator::translateSwitch(const User &U, MachineIRBuilder &MIB) { // FIXME: At the moment we don't do any splitting optimizations here like // SelectionDAG does, so this worklist only has one entry. while (!WorkList.empty()) { - SwitchWorkListItem W = WorkList.back(); - WorkList.pop_back(); + SwitchWorkListItem W = WorkList.pop_back_val(); if (!lowerSwitchWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB, MIB)) return false; } diff --git a/llvm/lib/CodeGen/LiveRangeEdit.cpp b/llvm/lib/CodeGen/LiveRangeEdit.cpp index c3f796a8f64b2e..5b0275e0a82f16 100644 --- a/llvm/lib/CodeGen/LiveRangeEdit.cpp +++ b/llvm/lib/CodeGen/LiveRangeEdit.cpp @@ -413,8 +413,7 @@ void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl &Dead, break; // Shrink just one live interval. Then delete new dead defs. - LiveInterval *LI = ToShrink.back(); - ToShrink.pop_back(); + LiveInterval *LI = ToShrink.pop_back_val(); if (foldAsLoad(LI, Dead)) continue; unsigned VReg = LI->reg(); diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp index 7181dbc9c870ac..300a9059de88cc 100644 --- a/llvm/lib/CodeGen/LiveVariables.cpp +++ b/llvm/lib/CodeGen/LiveVariables.cpp @@ -119,8 +119,7 @@ void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo, MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList); while (!WorkList.empty()) { - MachineBasicBlock *Pred = WorkList.back(); - WorkList.pop_back(); + MachineBasicBlock *Pred = WorkList.pop_back_val(); MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList); } } @@ -484,8 +483,7 @@ void LiveVariables::HandlePhysRegDef(Register Reg, MachineInstr *MI, void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI, SmallVectorImpl &Defs) { while (!Defs.empty()) { - Register Reg = Defs.back(); - Defs.pop_back(); + Register Reg = Defs.pop_back_val(); for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); SubRegs.isValid(); ++SubRegs) { unsigned SubReg = *SubRegs; diff --git a/llvm/lib/CodeGen/LoopTraversal.cpp b/llvm/lib/CodeGen/LoopTraversal.cpp index 9490dfc40a82c7..0d400253c6529a 100644 --- a/llvm/lib/CodeGen/LoopTraversal.cpp +++ b/llvm/lib/CodeGen/LoopTraversal.cpp @@ -39,8 +39,7 @@ LoopTraversal::TraversalOrder LoopTraversal::traverse(MachineFunction &MF) { bool Primary = true; Workqueue.push_back(MBB); while (!Workqueue.empty()) { - MachineBasicBlock *ActiveMBB = &*Workqueue.back(); - Workqueue.pop_back(); + MachineBasicBlock *ActiveMBB = Workqueue.pop_back_val(); bool Done = isBlockDone(ActiveMBB); MBBTraversalOrder.push_back(TraversedMBBInfo(ActiveMBB, Primary, Done)); for (MachineBasicBlock *Succ : ActiveMBB->successors()) { diff --git a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp index 34e9a2fd4d5ee7..1264e6021b6e55 100644 --- a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp +++ b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp @@ -397,8 +397,7 @@ void ReachingDefAnalysis::getGlobalUses(MachineInstr *MI, MCRegister PhysReg, SmallVector ToVisit(MBB->successors()); SmallPtrSetVisited; while (!ToVisit.empty()) { - MachineBasicBlock *MBB = ToVisit.back(); - ToVisit.pop_back(); + MachineBasicBlock *MBB = ToVisit.pop_back_val(); if (Visited.count(MBB) || !MBB->isLiveIn(PhysReg)) continue; if (getLiveInUses(MBB, PhysReg, Uses)) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp index 05a974af3b5550..1f73c9eea10472 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp @@ -223,8 +223,7 @@ bool DAGTypeLegalizer::run() { #endif PerformExpensiveChecks(); - SDNode *N = Worklist.back(); - Worklist.pop_back(); + SDNode *N = Worklist.pop_back_val(); assert(N->getNodeId() == ReadyToProcess && "Node should be ready if on worklist!"); diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp index 0022e5ec31f0b1..1b89864116cb93 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -56,9 +56,7 @@ namespace { SUnit *pop() { if (empty()) return nullptr; - SUnit *V = Queue.back(); - Queue.pop_back(); - return V; + return Queue.pop_back_val(); } }; diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index 1664b4dadfec96..5729d1d977a35f 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -667,8 +667,7 @@ void TwoAddressInstructionPass::scanUses(Register DstReg) { unsigned ToReg = VirtRegPairs.back(); VirtRegPairs.pop_back(); while (!VirtRegPairs.empty()) { - unsigned FromReg = VirtRegPairs.back(); - VirtRegPairs.pop_back(); + unsigned FromReg = VirtRegPairs.pop_back_val(); bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second; if (!isNew) assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!"); diff --git a/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp b/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp index 3c22c93d065d83..c663f5cfa3b5ae 100644 --- a/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp +++ b/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp @@ -550,8 +550,7 @@ class ObjectLinkingLayerJITLinkContext final : public JITLinkContext { // Propagate block-level dependencies through the block-dependence graph. while (!WorkList.empty()) { - auto *B = WorkList.back(); - WorkList.pop_back(); + auto *B = WorkList.pop_back_val(); auto &BI = BlockInfos[B]; assert(BI.DependenciesChanged && diff --git a/llvm/lib/IR/Value.cpp b/llvm/lib/IR/Value.cpp index da67da1ac6c597..a13380b51b21cd 100644 --- a/llvm/lib/IR/Value.cpp +++ b/llvm/lib/IR/Value.cpp @@ -1013,8 +1013,7 @@ bool Value::isTransitiveUsedByMetadataOnly() const { llvm::SmallPtrSet Visited; WorkList.insert(WorkList.begin(), user_begin(), user_end()); while (!WorkList.empty()) { - const User *U = WorkList.back(); - WorkList.pop_back(); + const User *U = WorkList.pop_back_val(); Visited.insert(U); // If it is transitively used by a global value or a non-constant value, // it's obviously not only used by metadata. diff --git a/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp b/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp index fe725b568000d8..5d8af760f5acca 100644 --- a/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp +++ b/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp @@ -276,8 +276,7 @@ Optional AArch64StackTaggingPreRA::findFirstSlotCandidate() { WorkList.push_back(RetagReg); while (!WorkList.empty()) { - Register UseReg = WorkList.back(); - WorkList.pop_back(); + Register UseReg = WorkList.pop_back_val(); for (auto &UseI : MRI->use_instructions(UseReg)) { unsigned Opcode = UseI.getOpcode(); if (Opcode == AArch64::STGOffset || Opcode == AArch64::ST2GOffset || diff --git a/llvm/lib/Target/ARM/A15SDOptimizer.cpp b/llvm/lib/Target/ARM/A15SDOptimizer.cpp index bb81233cf8030e..cbe98b93ca7357 100644 --- a/llvm/lib/Target/ARM/A15SDOptimizer.cpp +++ b/llvm/lib/Target/ARM/A15SDOptimizer.cpp @@ -182,8 +182,7 @@ void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) { Front.push_back(MI); while (Front.size() != 0) { - MI = Front.back(); - Front.pop_back(); + MI = Front.pop_back_val(); // MI is already known to be dead. We need to see // if other instructions can also be removed. diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index d54d1d242c594d..6e259b1baf97f8 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -2476,8 +2476,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB, } } else { for (unsigned i = 0; i != NumMove; ++i) { - MachineInstr *Op = Ops.back(); - Ops.pop_back(); + MachineInstr *Op = Ops.pop_back_val(); MBB->splice(InsertPos, MBB, Op); } } diff --git a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp index ea582921993838..488e7784d7f45f 100644 --- a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp +++ b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp @@ -89,8 +89,7 @@ bool WebAssemblyAsmTypeCheck::popType(SMLoc ErrorLoc, : StringRef( "empty stack while popping value")); } - auto PVT = Stack.back(); - Stack.pop_back(); + auto PVT = Stack.pop_back_val(); if (EVT.hasValue() && EVT.getValue() != PVT) { return typeError( ErrorLoc, StringRef("popped ") + WebAssembly::typeToString(PVT) + diff --git a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp index f00ad5d0b05738..add3fe7a50f823 100644 --- a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp +++ b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp @@ -1868,8 +1868,7 @@ static void cleanupSinglePredPHIs(Function &F) { } } while (!Worklist.empty()) { - auto *Phi = Worklist.back(); - Worklist.pop_back(); + auto *Phi = Worklist.pop_back_val(); auto *OriginalValue = Phi->getIncomingValue(0); Phi->replaceAllUsesWith(OriginalValue); } diff --git a/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp b/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp index 111206b14641a5..cfa74464559faf 100644 --- a/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp +++ b/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp @@ -144,8 +144,7 @@ class DFAJumpThreading { Stack.push_back(SIToUnfold); while (!Stack.empty()) { - SelectInstToUnfold SIToUnfold = Stack.back(); - Stack.pop_back(); + SelectInstToUnfold SIToUnfold = Stack.pop_back_val(); std::vector NewSIsToUnfold; std::vector NewBBs; @@ -662,8 +661,7 @@ struct AllSwitchPaths { SmallSet SeenValues; while (!Stack.empty()) { - PHINode *CurPhi = Stack.back(); - Stack.pop_back(); + PHINode *CurPhi = Stack.pop_back_val(); Res[CurPhi->getParent()] = CurPhi; SeenValues.insert(CurPhi);