diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index a8271257cbfec..3fad668a89a44 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -429,6 +429,14 @@ class ARMMCInstrAnalysis : public MCInstrAnalysis {
     // is 4 bytes.
     uint64_t Offset = ((Desc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8;
 
+    // A Thumb instruction BLX(i) can be 16-bit aligned while targets Arm code
+    // which is 32-bit aligned. The target address for the case is calculated as
+    //   targetAddress = Align(PC,4) + imm32;
+    // where
+    //   Align(x, y) = y * (x DIV y);
+    if (Inst.getOpcode() == ARM::tBLXi)
+      Addr &= ~0x3;
+
     Target = Addr + Imm + Offset;
     return true;
   }
diff --git a/llvm/test/tools/llvm-objdump/ELF/ARM/tblxi-target.s b/llvm/test/tools/llvm-objdump/ELF/ARM/tblxi-target.s
new file mode 100644
index 0000000000000..096c1a3a24026
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/tblxi-target.s
@@ -0,0 +1,26 @@
+## Check that the disassembler reports the target address of a Thumb BLX(i)
+## instruction correctly even if the instruction is not 32-bit aligned.
+
+# RUN: llvm-mc %s --triple=armv8a -filetype=obj | \
+# RUN:   llvm-objdump -dr - --triple armv8a --no-show-raw-insn | \
+# RUN:   FileCheck %s
+
+# CHECK:      <test>:
+# CHECK-NEXT:   4:  nop
+# CHECK-NEXT:   6:  blx  #-8 <foo>
+# CHECK-NEXT:   a:  blx  #4 <bar>
+
+  .arm
+foo:
+  nop
+
+  .thumb
+test:
+  nop
+  blx #-8
+  blx #4
+
+  .arm
+  .p2align 2
+bar:
+  nop