diff --git a/llvm/include/llvm/IR/IntrinsicsRISCVXTHead.td b/llvm/include/llvm/IR/IntrinsicsRISCVXTHead.td
index 8486b678022b4b..5af10a3e197aae 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCVXTHead.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCVXTHead.td
@@ -1,3 +1,15 @@
+//===- IntrinsicsRISCVXTHead.td - T-Head intrinsics --------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines all of the T-Head vendor intrinsics for RISC-V.
+//
+//===----------------------------------------------------------------------===//
+
 let TargetPrefix = "riscv" in {
 
   class TH_VdotTernaryWideMasked
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCVXsf.td b/llvm/include/llvm/IR/IntrinsicsRISCVXsf.td
index 67105944616c39..0c8da35491cef0 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCVXsf.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCVXsf.td
@@ -1,3 +1,15 @@
+//===- IntrinsicsRISCVXsf.td - SiFive intrinsics -----------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines all of the SiFive vendor intrinsics for RISC-V.
+//
+//===----------------------------------------------------------------------===//
+
 class VCIXSuffix<string range> {
   list<string> suffix = !cond(!eq(range, "c"): ["e8mf8", "e8mf4", "e8mf2", "e8m1", "e8m2", "e8m4", "e8m8"],
                               !eq(range, "s"): ["e16mf4", "e16mf2", "e16m1", "e16m2", "e16m4", "e16m8"],