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[WebAssembly] [Codegen] Add patterns for relaxed dot (#163266)
The pattern I added for `relaxed dot` similar to normal dot @ #151775. For `relaxed dot add`, i noticed that in the proposal the portion of dot implementation is similar to `relaxed dot`, so I think we can add a pattern where after we do relaxed dot and do extadd pairwise, we can do `relaxed dot add`. One current obstacles is I don't think there is any pattern to singly create a extadd pairwise from other instructions so the `relaxed dot add` pattern would not cover a wide range of instructions. related to #55932
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‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td‎

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@@ -1763,6 +1763,26 @@ defm RELAXED_DOT :
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"i16x8.relaxed_dot_i8x16_i7x16_s\t$dst, $lhs, $rhs",
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"i16x8.relaxed_dot_i8x16_i7x16_s", 0x112>;
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def : Pat<
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(v8i16 (add
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(wasm_shuffle
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(v8i16 (extmul_low_s v16i8:$lhs, v16i8:$rhs)),
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(v8i16 (extmul_high_s v16i8:$lhs, v16i8:$rhs)),
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(i32 0), (i32 1), (i32 4), (i32 5),
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(i32 8), (i32 9), (i32 12), (i32 13),
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(i32 16), (i32 17), (i32 20), (i32 21),
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(i32 24), (i32 25), (i32 28), (i32 29)),
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(wasm_shuffle
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(v8i16 (extmul_low_s v16i8:$lhs, v16i8:$rhs)),
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(v8i16 (extmul_high_s v16i8:$lhs, v16i8:$rhs)),
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(i32 2), (i32 3), (i32 6), (i32 7),
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(i32 10), (i32 11), (i32 14), (i32 15),
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(i32 18), (i32 19), (i32 22), (i32 23),
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(i32 26), (i32 27), (i32 30), (i32 31)))
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),
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(v8i16 (RELAXED_DOT v16i8:$lhs, v16i8:$rhs))
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>;
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defm RELAXED_DOT_ADD :
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RELAXED_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, V128:$acc),
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(outs), (ins),
@@ -1771,6 +1791,14 @@ defm RELAXED_DOT_ADD :
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"i32x4.relaxed_dot_i8x16_i7x16_add_s\t$dst, $lhs, $rhs, $acc",
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"i32x4.relaxed_dot_i8x16_i7x16_add_s", 0x113>;
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def : Pat<
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(v4i32 (add
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(v4i32 (int_wasm_extadd_pairwise_signed
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(v8i16 (int_wasm_relaxed_dot_i8x16_i7x16_signed v16i8:$lhs, v16i8:$rhs)))),
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(v4i32 V128:$acc))),
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(v4i32 (RELAXED_DOT_ADD v16i8:$lhs, v16i8:$rhs, (v4i32 V128:$acc)))
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>;
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def : Pat<(v4i32 (partial_reduce_smla (v4i32 V128:$acc), (v16i8 V128:$lhs),
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(v16i8 V128:$rhs))),
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(RELAXED_DOT_ADD $lhs, $rhs, $acc)>, Requires<[HasRelaxedSIMD]>;

‎llvm/test/CodeGen/WebAssembly/simd-relaxed-dot.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+fp16,+simd128,+relaxed-simd | FileCheck %s
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target triple = "wasm32"
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; relaxed_dot stands for relaxed_dot_i8x16_i7x16_s, as in td
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; relaxed_dot_add stands for i32x4.relaxed_dot_i8x16_i7x16_add_s, as in td
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define <8 x i16> @relaxed_dot_sext_1(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: relaxed_dot_sext_1:
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; CHECK: .functype relaxed_dot_sext_1 (v128, v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i16x8.relaxed_dot_i8x16_i7x16_s $push0=, $0, $1
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; CHECK-NEXT: return $pop0
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%sext1 = sext <16 x i8> %a to <16 x i16>
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%sext2 = sext <16 x i8> %b to <16 x i16>
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%mul = mul <16 x i16> %sext1, %sext2
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%shuffle1 = shufflevector <16 x i16> %mul, <16 x i16> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%shuffle2 = shufflevector <16 x i16> %mul, <16 x i16> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%res = add <8 x i16> %shuffle1, %shuffle2
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ret <8 x i16> %res
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}
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define <8 x i16> @relaxed_dot_sext_2(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: relaxed_dot_sext_2:
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; CHECK: .functype relaxed_dot_sext_2 (v128, v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i16x8.relaxed_dot_i8x16_i7x16_s $push0=, $0, $1
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; CHECK-NEXT: return $pop0
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%sext1 = sext <16 x i8> %a to <16 x i16>
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%sext2 = sext <16 x i8> %b to <16 x i16>
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%mul = mul <16 x i16> %sext1, %sext2
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%shuffle1 = shufflevector <16 x i16> %mul, <16 x i16> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%shuffle2 = shufflevector <16 x i16> %mul, <16 x i16> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%res = add <8 x i16> %shuffle2, %shuffle1
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ret <8 x i16> %res
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}
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define <8 x i16> @relaxed_dot_sext_self(<16 x i8> %v) {
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; CHECK-LABEL: relaxed_dot_sext_self:
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; CHECK: .functype relaxed_dot_sext_self (v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i16x8.relaxed_dot_i8x16_i7x16_s $push0=, $0, $0
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; CHECK-NEXT: return $pop0
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%sext = sext <16 x i8> %v to <16 x i16>
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%mul = mul <16 x i16> %sext, %sext
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%shuffle1 = shufflevector <16 x i16> %mul, <16 x i16> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%shuffle2 = shufflevector <16 x i16> %mul, <16 x i16> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%res = add <8 x i16> %shuffle1, %shuffle2
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ret <8 x i16> %res
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}
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define <4 x i32> @relaxed_dot_add_from_relaxed_dot(<16 x i8> %a, <16 x i8> %b, <4 x i32> %c) {
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; CHECK-LABEL: relaxed_dot_add_from_relaxed_dot:
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; CHECK: .functype relaxed_dot_add_from_relaxed_dot (v128, v128, v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i32x4.relaxed_dot_i8x16_i7x16_add_s $push0=, $0, $1, $2
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; CHECK-NEXT: return $pop0
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%relaxed_dot_call = call <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed(<16 x i8> %a, <16 x i8> %b)
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%sext = call <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16> %relaxed_dot_call)
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%res = add <4 x i32> %sext, %c
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ret <4 x i32> %res
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}
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; INFO: Negative test
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define <8 x i16> @relaxed_dot_zext(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: relaxed_dot_zext:
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; CHECK: .functype relaxed_dot_zext (v128, v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i16x8.extmul_low_i8x16_u $push6=, $0, $1
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; CHECK-NEXT: local.tee $push5=, $2=, $pop6
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; CHECK-NEXT: i16x8.extmul_high_i8x16_u $push4=, $0, $1
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; CHECK-NEXT: local.tee $push3=, $1=, $pop4
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; CHECK-NEXT: i8x16.shuffle $push1=, $pop5, $pop3, 0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29
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; CHECK-NEXT: i8x16.shuffle $push0=, $2, $1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31
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; CHECK-NEXT: i16x8.add $push2=, $pop1, $pop0
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; CHECK-NEXT: return $pop2
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%zext1 = zext <16 x i8> %a to <16 x i16>
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%zext2 = zext <16 x i8> %b to <16 x i16>
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%mul = mul <16 x i16> %zext1, %zext2
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%shuffle1 = shufflevector <16 x i16> %mul, <16 x i16> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%shuffle2 = shufflevector <16 x i16> %mul, <16 x i16> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%res = add <8 x i16> %shuffle1, %shuffle2
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ret <8 x i16> %res
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}
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; INFO: Negative test
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define <8 x i16> @relaxed_dot_wrong_shuffle(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: relaxed_dot_wrong_shuffle:
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; CHECK: .functype relaxed_dot_wrong_shuffle (v128, v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i16x8.extmul_low_i8x16_s $push1=, $0, $1
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; CHECK-NEXT: i16x8.extmul_high_i8x16_s $push0=, $0, $1
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; CHECK-NEXT: i16x8.add $push2=, $pop1, $pop0
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; CHECK-NEXT: return $pop2
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%sext1 = sext <16 x i8> %a to <16 x i16>
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%sext2 = sext <16 x i8> %b to <16 x i16>
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%mul = mul <16 x i16> %sext1, %sext2
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%shuffle1 = shufflevector <16 x i16> %mul, <16 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%shuffle2 = shufflevector <16 x i16> %mul, <16 x i16> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%res = add <8 x i16> %shuffle1, %shuffle2
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ret <8 x i16> %res
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}

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