From 8a25eabd42780616954f10e135effbd95edec847 Mon Sep 17 00:00:00 2001
From: Michael Liao <michael.hliao@gmail.com>
Date: Sat, 10 Aug 2019 16:15:06 +0000
Subject: [PATCH] [TableGen] Correct the shift to the proper bit width.

- Replace the previous 32-bit shift with 64-bit one matching `OpInit`.

llvm-svn: 368513
---
 .../test/TableGen/FixedLenDecoderEmitter/InitValue.td | 11 +++++++++++
 llvm/utils/TableGen/FixedLenDecoderEmitter.cpp        |  2 +-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/InitValue.td b/llvm/test/TableGen/FixedLenDecoderEmitter/InitValue.td
index 27058baa73c09..2ed3f1343b4b1 100644
--- a/llvm/test/TableGen/FixedLenDecoderEmitter/InitValue.td
+++ b/llvm/test/TableGen/FixedLenDecoderEmitter/InitValue.td
@@ -28,8 +28,19 @@ def bar : Instruction {
     let Inst{15-8} = factor{7-0};
     }
 
+def bax : Instruction {
+    let InOperandList = (ins i32imm:$factor);
+    field bits<16> Inst;
+    field bits<16> SoftFail = 0;
+    bits<33> factor;
+    let factor{32} = 1; // non-zero initial value
+    let Inst{15-8} = factor{32-25};
+    }
+
 }
 
 // CHECK: tmp = fieldFromInstruction(insn, 9, 7) << 1;
 // CHECK: tmp = 0x1;
 // CHECK: tmp |= fieldFromInstruction(insn, 9, 7) << 1;
+// CHECK: tmp = 0x100000000;
+// CHECK: tmp |= fieldFromInstruction(insn, 8, 7) << 25;
diff --git a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
index 7a6f44b9ab6ea..cfe06dd4d7fb5 100644
--- a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
+++ b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
@@ -2038,7 +2038,7 @@ populateInstruction(CodeGenTarget &Target, const Record &EncodingDef,
         for (unsigned I = 0; I < OpBits->getNumBits(); ++I)
           if (const BitInit *OpBit = dyn_cast<BitInit>(OpBits->getBit(I)))
             if (OpBit->getValue())
-              OpInfo.InitValue |= 1 << I;
+              OpInfo.InitValue |= 1ULL << I;
 
     unsigned Base = ~0U;
     unsigned Width = 0;