diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d1ed862db55e6..c4ee6a193a049 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -21776,12 +21776,14 @@ static SDValue splitVectorStore(StoreSDNode *Store, SelectionDAG &DAG) {
          "Expecting 256/512-bit op");
 
   // Splitting volatile memory ops is not allowed unless the operation was not
-  // legal to begin with. We are assuming the input op is legal (this transform
-  // is only used for targets with AVX).
+  // legal to begin with. Assume the input store is legal (this transform is
+  // only used for targets with AVX). Note: It is possible that we have an
+  // illegal type like v2i128, and so we could allow splitting a volatile store
+  // in that case if that is important.
   if (!Store->isSimple())
     return SDValue();
 
-  MVT StoreVT = StoredVal.getSimpleValueType();
+  EVT StoreVT = StoredVal.getValueType();
   unsigned NumElems = StoreVT.getVectorNumElements();
   unsigned HalfSize = StoredVal.getValueSizeInBits() / 2;
   unsigned HalfAlign = (128 == HalfSize ? 16 : 32);
diff --git a/llvm/test/CodeGen/X86/avx-load-store.ll b/llvm/test/CodeGen/X86/avx-load-store.ll
index 402e2705191ed..1b3c35855ae9a 100644
--- a/llvm/test/CodeGen/X86/avx-load-store.ll
+++ b/llvm/test/CodeGen/X86/avx-load-store.ll
@@ -333,3 +333,26 @@ define void @add4i64a16(<4 x i64>* %ret, <4 x i64>* %bp) nounwind {
   ret void
 }
 
+; This used to crash.
+; v2i128 may not be a "simple" (MVT) type, but we can split that.
+; This example gets split further in legalization.
+
+define void @PR43916(<2 x i128> %y, <2 x i128>* %z) {
+; CHECK-LABEL: PR43916:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rcx, 24(%r8)
+; CHECK-NEXT:    movq %rdx, 16(%r8)
+; CHECK-NEXT:    movq %rsi, 8(%r8)
+; CHECK-NEXT:    movq %rdi, (%r8)
+; CHECK-NEXT:    retq
+;
+; CHECK_O0-LABEL: PR43916:
+; CHECK_O0:       # %bb.0:
+; CHECK_O0-NEXT:    movq %rdi, (%r8)
+; CHECK_O0-NEXT:    movq %rsi, 8(%r8)
+; CHECK_O0-NEXT:    movq %rdx, 16(%r8)
+; CHECK_O0-NEXT:    movq %rcx, 24(%r8)
+; CHECK_O0-NEXT:    retq
+  store <2 x i128> %y, <2 x i128>* %z, align 16
+  ret void
+}