From 8e8fb77aa40c287067306df7ff2416122b31e33b Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Sun, 3 Oct 2021 23:37:09 +0300 Subject: [PATCH] [X86][Costmodel] Load/store i16 Stride=3 VF=2 interleaving costs The only sched models that for cpu's that support avx2 but not avx512 are: haswell, broadwell, skylake, zen1-3 For load we have: https://godbolt.org/z/xnE988aej - for intels `Block RThroughput: =5.0`; for ryzens, `Block RThroughput: <=2.5` So pick cost of `5`. For store we have: https://godbolt.org/z/rMGT31Tnh - for intels `Block RThroughput: =4.0`; for ryzens, `Block RThroughput: <=2.0` So pick cost of `4`. I'm directly using the shuffling asm the llc produced, without any manual fixups that may be needed to ensure sequential execution. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D111014 --- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 4 ++++ .../Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll | 2 +- .../Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll | 2 +- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index b49409b63bbba..86f2221197d5d 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -5100,6 +5100,8 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 {3, MVT::v32i8, 14}, // (load 96i8 and) deinterleave into 3 x 32i8 + {3, MVT::v2i16, 5}, // (load 6i16 and) deinterleave into 3 x 2i16 + {3, MVT::v8i32, 17}, // (load 24i32 and) deinterleave into 3 x 8i32 {4, MVT::v2i8, 4}, // (load 8i8 and) deinterleave into 4 x 2i8 @@ -5158,6 +5160,8 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) + {3, MVT::v2i16, 4}, // interleave 3 x 2i16 into 6i16 (and store) + {4, MVT::v2i8, 4}, // interleave 4 x 2i8 into 8i8 (and store) {4, MVT::v4i8, 4}, // interleave 4 x 4i8 into 16i8 (and store) {4, MVT::v8i8, 4}, // interleave 4 x 8i8 into 32i8 (and store) diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll index ceb0310b10c8b..daa802e4e50e3 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll @@ -26,7 +26,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX1: LV: Found an estimated cost of 258 for VF 32 For instruction: %v0 = load i16, i16* %in0, align 2 ; ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i16, i16* %in0, align 2 -; AVX2: LV: Found an estimated cost of 15 for VF 2 For instruction: %v0 = load i16, i16* %in0, align 2 +; AVX2: LV: Found an estimated cost of 8 for VF 2 For instruction: %v0 = load i16, i16* %in0, align 2 ; AVX2: LV: Found an estimated cost of 31 for VF 4 For instruction: %v0 = load i16, i16* %in0, align 2 ; AVX2: LV: Found an estimated cost of 58 for VF 8 For instruction: %v0 = load i16, i16* %in0, align 2 ; AVX2: LV: Found an estimated cost of 129 for VF 16 For instruction: %v0 = load i16, i16* %in0, align 2 diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll index b42da831676a7..9b40dcaf1afb0 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll @@ -26,7 +26,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX1: LV: Found an estimated cost of 258 for VF 32 For instruction: store i16 %v2, i16* %out2, align 2 ; ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store i16 %v2, i16* %out2, align 2 -; AVX2: LV: Found an estimated cost of 15 for VF 2 For instruction: store i16 %v2, i16* %out2, align 2 +; AVX2: LV: Found an estimated cost of 7 for VF 2 For instruction: store i16 %v2, i16* %out2, align 2 ; AVX2: LV: Found an estimated cost of 30 for VF 4 For instruction: store i16 %v2, i16* %out2, align 2 ; AVX2: LV: Found an estimated cost of 53 for VF 8 For instruction: store i16 %v2, i16* %out2, align 2 ; AVX2: LV: Found an estimated cost of 129 for VF 16 For instruction: store i16 %v2, i16* %out2, align 2