From 96b52c1eec7b7952059a4cc4acd2f5e62e1ba1ca Mon Sep 17 00:00:00 2001
From: eopXD <yueh.ting.chen@gmail.com>
Date: Sun, 8 Jan 2023 07:55:06 -0800
Subject: [PATCH] [Clang][RISCV] Expose vlenb to user

This commit adds function `vlenb` into riscv_vector.h. `vlenb` is defined
through builtin function `__builtin_rvv_vlenb`, which is lowered to
`llvm.read_register`.

Reviewed By: kito-cheng, pcwang-thead

Differential Revision: https://reviews.llvm.org/D141032
---
 clang/include/clang/Basic/riscv_vector.td     | 26 +++++++++++++
 .../test/CodeGen/RISCV/rvv-intrinsics/vlenb.c | 39 +++++++++++++++++++
 2 files changed, 65 insertions(+)
 create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c

diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 6e089a7d87d6b..29ff8accf7f07 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1558,6 +1558,32 @@ void vwrite_csr(enum RVV_CSR __csr, unsigned long __value) {
 }] in
 def vread_vwrite_csr: RVVHeader;
 
+let HeaderCode =
+[{
+#define vlenb() __builtin_rvv_vlenb()
+}] in
+def vlenb_macro: RVVHeader;
+
+let HasBuiltinAlias = false, HasVL = false, HasMasked = false,
+    UnMaskedPolicyScheme = NonePolicy, MaskedPolicyScheme = NonePolicy,
+    Log2LMUL = [0], IRName = "",
+    ManualCodegen = [{
+    {
+      LLVMContext &Context = CGM.getLLVMContext();
+      llvm::MDBuilder MDHelper(Context);
+
+      llvm::Metadata *Ops[] = {llvm::MDString::get(Context, "vlenb")};
+      llvm::MDNode *RegName = llvm::MDNode::get(Context, Ops);
+      llvm::Value *Metadata = llvm::MetadataAsValue::get(Context, RegName);
+      llvm::Function *F =
+        CGM.getIntrinsic(llvm::Intrinsic::read_register, {SizeTy});
+      return Builder.CreateCall(F, Metadata);
+    }
+    }] in
+{
+  def vlenb : RVVBuiltin<"", "u", "i">;
+}
+
 // 6. Configuration-Setting Instructions
 // 6.1. vsetvli/vsetvl instructions
 
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
new file mode 100644
index 0000000000000..999e1accbed2f
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
@@ -0,0 +1,39 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn %s -o - \
+// RUN:     | opt -S -O2 | FileCheck --check-prefix=RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm -Qn %s -o - \
+// RUN:     | opt -S -O2 | FileCheck --check-prefix=RV64 %s
+
+#include <riscv_vector.h>
+
+// RV32-LABEL: @test_vlenb(
+// RV32-NEXT:  entry:
+// RV32-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.read_register.i32(metadata [[META3:![0-9]+]])
+// RV32-NEXT:    ret i32 [[TMP0]]
+//
+// RV64-LABEL: @test_vlenb(
+// RV64-NEXT:  entry:
+// RV64-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.read_register.i64(metadata [[META3:![0-9]+]])
+// RV64-NEXT:    ret i64 [[TMP0]]
+//
+unsigned long test_vlenb(void) {
+  return vlenb();
+}
+//.
+// RV32: attributes #0 = { mustprogress nofree noinline nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+v,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
+// RV32: attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(read) }
+//.
+// RV64: attributes #0 = { mustprogress nofree noinline nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+v,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
+// RV64: attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(read) }
+//.
+// RV32: !0 = !{i32 1, !"wchar_size", i32 4}
+// RV32: !1 = !{i32 1, !"target-abi", !"ilp32d"}
+// RV32: !2 = !{i32 1, !"SmallDataLimit", i32 0}
+// RV32: !3 = !{!"vlenb"}
+//.
+// RV64: !0 = !{i32 1, !"wchar_size", i32 4}
+// RV64: !1 = !{i32 1, !"target-abi", !"lp64d"}
+// RV64: !2 = !{i32 1, !"SmallDataLimit", i32 0}
+// RV64: !3 = !{!"vlenb"}
+//.