diff --git a/llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll b/llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll index 536526a5cfe06..1dfeaa1959e07 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll @@ -1,27 +1,29 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 ; RUN: opt --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -mcpu=icelake-server -S < %s | FileCheck %s -define i1 @test() { +define i1 @test(i64 %v) { ; CHECK-LABEL: define i1 @test -; CHECK-SAME: () #[[ATTR0:[0-9]+]] { +; CHECK-SAME: (i64 [[V:%.*]]) #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = shl i64 0, 0 -; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i64> , i64 0, i32 0 -; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> [[TMP1]], <8 x i64> poison, <8 x i32> -; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i64> , i64 [[TMP0]], i32 0 -; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i64> [[TMP11]], i64 0, i32 1 -; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> poison, <8 x i32> -; CHECK-NEXT: [[TMP6:%.*]] = or <8 x i64> [[TMP3]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = sub <8 x i64> [[TMP3]], [[TMP5]] -; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x i64> [[TMP6]], <8 x i64> [[TMP7]], <8 x i32> -; CHECK-NEXT: [[TMP9:%.*]] = icmp ult <8 x i64> [[TMP8]], zeroinitializer -; CHECK-NEXT: [[TMP10:%.*]] = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> [[TMP9]]) -; CHECK-NEXT: ret i1 [[TMP10]] +; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[V]], 1 +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[V]], 3 +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[V]], 7 +; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i64> , i64 [[TMP1]], i32 0 +; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i64> [[TMP3]], <8 x i64> poison, <8 x i32> +; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i64> , i64 [[TMP0]], i32 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i64> [[TMP5]], i64 [[TMP2]], i32 1 +; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i64> [[TMP6]], <4 x i64> poison, <8 x i32> +; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i64> [[TMP4]], [[TMP7]] +; CHECK-NEXT: [[TMP9:%.*]] = sub <8 x i64> [[TMP4]], [[TMP7]] +; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i64> [[TMP8]], <8 x i64> [[TMP9]], <8 x i32> +; CHECK-NEXT: [[TMP11:%.*]] = icmp ult <8 x i64> [[TMP10]], zeroinitializer +; CHECK-NEXT: [[TMP12:%.*]] = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> [[TMP11]]) +; CHECK-NEXT: ret i1 [[TMP12]] ; entry: - %0 = shl i64 0, 0 - %1 = add i64 0, 0 - %2 = add i64 0, 0 + %0 = shl i64 %v, 1 + %1 = add i64 %v, 3 + %2 = add i64 %v, 7 %3 = or i64 %2, %1 %cmp750 = icmp ult i64 %3, 0 %4 = or i64 %0, %1