diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir index b17965cd3355c..05f804fb170c3 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir @@ -1,19 +1,17 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s -# CHECK-NOT: $lr = tMOVr $r0, 13 -# CHECK: $lr = t2DLS killed $r0 -# CHECK: $lr = t2LEUpdate renamable $lr, %bb.1 --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv8.1m.main" - + define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) { entry: %scevgep = getelementptr i32, i32* %q, i32 -1 %scevgep3 = getelementptr i32, i32* %p, i32 -1 call void @llvm.set.loop.iterations.i32(i32 %n) br label %while.body - + while.body: ; preds = %while.body, %entry %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %entry ] %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %entry ] @@ -27,14 +25,14 @@ %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) %3 = icmp ne i32 %2, 0 br i1 %3, label %while.body, label %while.end - + while.end: ; preds = %while.body ret i32 0 } - + declare void @llvm.set.loop.iterations.i32(i32) #0 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0 - + attributes #0 = { noduplicate nounwind } attributes #1 = { nounwind } @@ -75,20 +73,40 @@ frameInfo: restorePoint: '' fixedStack: [] stack: - - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, + - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, + - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } callSites: [] constants: [] machineFunctionInfo: {} body: | + ; CHECK-LABEL: name: do_copy + ; CHECK: bb.0.entry: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: liveins: $r0, $r1, $r2, $r7, $lr + ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK: $lr = t2DLS killed $r0 + ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg + ; CHECK: bb.1.while.body: + ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) + ; CHECK: liveins: $lr, $r0, $r1 + ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) + ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) + ; CHECK: $lr = t2LEUpdate renamable $lr, %bb.1 + ; CHECK: bb.2.while.end: + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr - + frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -97,17 +115,17 @@ body: | t2DoLoopStart killed $r0 renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg - + bb.1.while.body: successors: %bb.1(0x7c000000), %bb.2(0x04000000) liveins: $lr, $r0, $r1 - + renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) renamable $lr = t2LoopDec killed renamable $lr, 1 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr tB %bb.2, 14, $noreg - + bb.2.while.end: $r0, dead $cpsr = tMOVi8 0, 14, $noreg tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir index 8fa138a6d987e..2ab2a120de7ce 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir @@ -1,19 +1,10 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s -# CHECK-NOT: DoLoopStart -# CHECK-NOT: DLS -# CHECK: bb.1.for.body: -# CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr -# CHECK-NOT: t2CMPri $lr -# CHECK: tBcc %bb.3, 1, $cpsr -# CHECK: tB %bb.2, 14, $noreg -# CHECK: bb.2.for.cond.cleanup: -# CHECK: bb.3.for.header: - --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv8.1m.main" - + define void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) { entry: call void @llvm.set.loop.iterations.i32(i32 %N) @@ -21,7 +12,7 @@ %scevgep4 = getelementptr i32, i32* %c, i32 -1 %scevgep8 = getelementptr i32, i32* %b, i32 -1 br label %for.header - + for.body: ; preds = %for.header %scevgep11 = getelementptr i32, i32* %lsr.iv9, i32 1 %ld1 = load i32, i32* %scevgep11, align 4 @@ -36,10 +27,10 @@ %count.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1) %cmp = icmp ne i32 %count.next, 0 br i1 %cmp, label %for.header, label %for.cond.cleanup - + for.cond.cleanup: ; preds = %for.body ret void - + for.header: ; preds = %for.body, %entry %lsr.iv9 = phi i32* [ %scevgep8, %entry ], [ %scevgep10, %for.body ] %lsr.iv5 = phi i32* [ %scevgep4, %entry ], [ %scevgep6, %for.body ] @@ -47,16 +38,16 @@ %count = phi i32 [ %N, %entry ], [ %count.next, %for.body ] br label %for.body } - + ; Function Attrs: nounwind declare i32 @llvm.arm.space(i32 immarg, i32) #0 - + ; Function Attrs: noduplicate nounwind declare void @llvm.set.loop.iterations.i32(i32) #1 - + ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 - + attributes #0 = { nounwind } attributes #1 = { noduplicate nounwind } @@ -98,44 +89,95 @@ frameInfo: restorePoint: '' fixedStack: [] stack: - - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, + - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 1, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, + - { id: 1, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 2, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, + - { id: 2, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 3, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, + - { id: 3, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 4, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, + - { id: 4, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 5, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, + - { id: 5, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 6, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, + - { id: 6, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 7, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, + - { id: 7, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 8, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, + - { id: 8, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 9, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, + - { id: 9, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } callSites: [] constants: [] machineFunctionInfo: {} body: | + ; CHECK-LABEL: name: size_limit + ; CHECK: bb.0.entry: + ; CHECK: successors: %bb.3(0x80000000) + ; CHECK: liveins: $r0, $r1, $r2, $r3, $r7, $lr + ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK: $sp = frame-setup tSUBspi $sp, 8, 14, $noreg + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40 + ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg + ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg + ; CHECK: tSTRspi killed $r1, $sp, 7, 14, $noreg :: (store 4 into %stack.0) + ; CHECK: tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1) + ; CHECK: tSTRspi killed $r0, $sp, 5, 14, $noreg :: (store 4 into %stack.2) + ; CHECK: tSTRspi killed $r3, $sp, 4, 14, $noreg :: (store 4 into %stack.3) + ; CHECK: tB %bb.3, 14, $noreg + ; CHECK: bb.1.for.body: + ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) + ; CHECK: $r0 = tLDRspi $sp, 3, 14, $noreg :: (load 4 from %stack.4) + ; CHECK: renamable $r1, renamable $r0 = t2LDR_PRE renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep11) + ; CHECK: $r2 = tLDRspi $sp, 2, 14, $noreg :: (load 4 from %stack.5) + ; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7) + ; CHECK: renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14, $noreg + ; CHECK: $r3 = tLDRspi $sp, 1, 14, $noreg :: (load 4 from %stack.6) + ; CHECK: early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, renamable $r3, 4, 14, $noreg :: (store 4 into %ir.scevgep3) + ; CHECK: $r1 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.7) + ; CHECK: $lr = tMOVr killed $r1, 14, $noreg + ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr + ; CHECK: $r12 = tMOVr $lr, 14, $noreg + ; CHECK: tSTRspi killed $r0, $sp, 7, 14, $noreg :: (store 4 into %stack.0) + ; CHECK: tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1) + ; CHECK: tSTRspi killed $r3, $sp, 5, 14, $noreg :: (store 4 into %stack.2) + ; CHECK: t2STRi12 killed $r12, $sp, 16, 14, $noreg :: (store 4 into %stack.3) + ; CHECK: tBcc %bb.3, 1, $cpsr + ; CHECK: tB %bb.2, 14, $noreg + ; CHECK: bb.2.for.cond.cleanup: + ; CHECK: $sp = tADDspi $sp, 8, 14, $noreg + ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: bb.3.for.header: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: $r0 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %stack.3) + ; CHECK: $r1 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %stack.2) + ; CHECK: $r2 = tLDRspi $sp, 6, 14, $noreg :: (load 4 from %stack.1) + ; CHECK: $r3 = tLDRspi $sp, 7, 14, $noreg :: (load 4 from %stack.0) + ; CHECK: tSTRspi killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.7) + ; CHECK: tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.6) + ; CHECK: tSTRspi killed $r2, $sp, 2, 14, $noreg :: (store 4 into %stack.5) + ; CHECK: tSTRspi killed $r3, $sp, 3, 14, $noreg :: (store 4 into %stack.4) + ; CHECK: tB %bb.1, 14, $noreg bb.0.entry: successors: %bb.3(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr - + frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -151,10 +193,10 @@ body: | tSTRspi killed $r0, $sp, 5, 14, $noreg :: (store 4 into %stack.2) tSTRspi killed $r3, $sp, 4, 14, $noreg :: (store 4 into %stack.3) tB %bb.3, 14, $noreg - + bb.1.for.body: successors: %bb.3(0x40000000), %bb.2(0x40000000) - + $r0 = tLDRspi $sp, 3, 14, $noreg :: (load 4 from %stack.4) renamable $r1, renamable $r0 = t2LDR_PRE renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep11) $r2 = tLDRspi $sp, 2, 14, $noreg :: (load 4 from %stack.5) @@ -172,14 +214,14 @@ body: | t2STRi12 killed $r12, $sp, 16, 14, $noreg :: (store 4 into %stack.3) t2LoopEnd killed renamable $lr, %bb.3, implicit-def dead $cpsr tB %bb.2, 14, $noreg - + bb.2.for.cond.cleanup: $sp = tADDspi $sp, 8, 14, $noreg tPOP_RET 14, $noreg, def $r7, def $pc - + bb.3.for.header: successors: %bb.1(0x80000000) - + $r0 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %stack.3) $r1 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %stack.2) $r2 = tLDRspi $sp, 6, 14, $noreg :: (load 4 from %stack.1) diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir index 47f933fdebd63..4206c9dae129d 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir @@ -1,19 +1,17 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s -# CHECK: $lr = t2DLS $r0 -# CHECK-NOT: $lr = tMOVr $r0 -# CHECK: $lr = t2LEUpdate renamable $lr, %bb.1 --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv8.1m.main" - + define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) { entry: %scevgep = getelementptr i32, i32* %q, i32 -1 %scevgep3 = getelementptr i32, i32* %p, i32 -1 call void @llvm.set.loop.iterations.i32(i32 %n) br label %while.body - + while.body: ; preds = %while.body, %entry %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %entry ] %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %entry ] @@ -27,14 +25,14 @@ %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) %3 = icmp ne i32 %2, 0 br i1 %3, label %while.body, label %while.end - + while.end: ; preds = %while.body ret i32 0 } - + declare void @llvm.set.loop.iterations.i32(i32) #0 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0 - + attributes #0 = { noduplicate nounwind } attributes #1 = { nounwind } @@ -75,20 +73,40 @@ frameInfo: restorePoint: '' fixedStack: [] stack: - - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, + - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, + - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } callSites: [] constants: [] machineFunctionInfo: {} body: | + ; CHECK-LABEL: name: do_copy + ; CHECK: bb.0.entry: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: liveins: $r0, $r1, $r2, $r7, $lr + ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK: $lr = t2DLS $r0 + ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg + ; CHECK: bb.1.while.body: + ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) + ; CHECK: liveins: $lr, $r0, $r1 + ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) + ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) + ; CHECK: $lr = t2LEUpdate renamable $lr, %bb.1 + ; CHECK: bb.2.while.end: + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr - + frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -97,17 +115,17 @@ body: | $lr = tMOVr killed $r0, 14, $noreg renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg - + bb.1.while.body: successors: %bb.1(0x7c000000), %bb.2(0x04000000) liveins: $lr, $r0, $r1 - + renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) renamable $lr = t2LoopDec killed renamable $lr, 1 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr tB %bb.2, 14, $noreg - + bb.2.while.end: $r0, dead $cpsr = tMOVi8 0, 14, $noreg tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir index 6e9dcaf3827cc..f640052414a8c 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir @@ -1,30 +1,20 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s -# CHECK: body: -# CHECK: bb.0.entry: -# CHECK: t2CMPri $r3, 0, 14 -# CHECK-NEXT: t2Bcc %bb.3, 0, $cpsr -# CHECK-NEXT: tB %bb.1 -# CHECK: bb.1.do.body.preheader: -# CHECK: $lr = tMOVr killed $r3 -# CHECK: bb.2.do.body: -# CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr -# CHECK-NEXT: t2Bcc %bb.2, 1, $cpsr -# CHECK-NEXT: tB %bb.3, 14 --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv8.1m.main" - + define void @ne_trip_count(i1 zeroext %t1, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) #0 { entry: %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N) br i1 %0, label %do.body.preheader, label %if.end - + do.body.preheader: ; preds = %entry %scevgep2 = getelementptr i32, i32* %a, i32 -1 %scevgep5 = getelementptr i32, i32* %b, i32 -1 br label %do.body - + do.body: ; preds = %do.body, %do.body.preheader %lsr.iv6 = phi i32* [ %scevgep5, %do.body.preheader ], [ %scevgep7, %do.body ] %lsr.iv = phi i32* [ %scevgep2, %do.body.preheader ], [ %scevgep3, %do.body ] @@ -39,20 +29,20 @@ %scevgep3 = getelementptr i32, i32* %lsr.iv, i32 1 %scevgep7 = getelementptr i32, i32* %lsr.iv6, i32 1 br i1 %3, label %do.body, label %if.end - + if.end: ; preds = %do.body, %entry ret void } - + ; Function Attrs: nounwind declare i32 @llvm.arm.space(i32 immarg, i32) #1 - + ; Function Attrs: noduplicate nounwind declare i1 @llvm.test.set.loop.iterations.i32(i32) #2 - + ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2 - + attributes #0 = { "target-features"="+lob" } attributes #1 = { nounwind } attributes #2 = { noduplicate nounwind } @@ -94,46 +84,74 @@ frameInfo: restorePoint: '' fixedStack: [] stack: - - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, + - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, + - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } callSites: [] constants: [] machineFunctionInfo: {} body: | + ; CHECK-LABEL: name: ne_trip_count + ; CHECK: bb.0.entry: + ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) + ; CHECK: liveins: $r1, $r2, $r3, $r7, $lr + ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK: t2CMPri $r3, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.3, 0, $cpsr + ; CHECK: tB %bb.1, 14, $noreg + ; CHECK: bb.1.do.body.preheader: + ; CHECK: successors: %bb.2(0x80000000) + ; CHECK: liveins: $r1, $r2, $r3 + ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg + ; CHECK: $lr = tMOVr killed $r3, 14, $noreg + ; CHECK: bb.2.do.body: + ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK: liveins: $lr, $r0, $r1 + ; CHECK: dead renamable $r2 = SPACE 4096, undef renamable $r0 + ; CHECK: renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep) + ; CHECK: early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14, $noreg :: (store 4 into %ir.scevgep1) + ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr + ; CHECK: t2Bcc %bb.2, 1, $cpsr + ; CHECK: tB %bb.3, 14, $noreg + ; CHECK: bb.3.if.end: + ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x40000000), %bb.3(0x40000000) liveins: $r1, $r2, $r3, $r7, $lr - + frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 t2WhileLoopStart $r3, %bb.3, implicit-def dead $cpsr tB %bb.1, 14, $noreg - + bb.1.do.body.preheader: successors: %bb.2(0x80000000) liveins: $r1, $r2, $r3 - + renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg $lr = tMOVr killed $r3, 14, $noreg - + bb.2.do.body: successors: %bb.2(0x7c000000), %bb.3(0x04000000) liveins: $lr, $r0, $r1 - + dead renamable $r2 = SPACE 4096, undef renamable $r0 renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep) early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14, $noreg :: (store 4 into %ir.scevgep1) renamable $lr = t2LoopDec killed renamable $lr, 1 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr tB %bb.3, 14, $noreg - + bb.3.if.end: tPOP_RET 14, $noreg, def $r7, def $pc diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir index efbee0e609cb8..1583b2652e243 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir @@ -1,14 +1,12 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s -# CHECK: $lr = t2DLS $r0 -# CHECK: $lr = tMOVr $r0, 14 -# CHECK: $lr = t2LEUpdate renamable $lr, %bb.2 # TODO: Explore the preheader to remove the redundant tMOVr --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv8.1m.main" - + define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) { entry: %scevgep = getelementptr i32, i32* %q, i32 -1 @@ -18,7 +16,7 @@ preheader: br label %while.body - + while.body: ; preds = %while.body, %entry %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %preheader ] %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %preheader ] @@ -32,14 +30,14 @@ %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) %3 = icmp ne i32 %2, 0 br i1 %3, label %while.body, label %while.end - + while.end: ; preds = %while.body ret i32 0 } - + declare void @llvm.set.loop.iterations.i32(i32) #0 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0 - + attributes #0 = { noduplicate nounwind } attributes #1 = { nounwind } @@ -80,20 +78,44 @@ frameInfo: restorePoint: '' fixedStack: [] stack: - - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, + - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, + - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } callSites: [] constants: [] machineFunctionInfo: {} body: | + ; CHECK-LABEL: name: do_copy + ; CHECK: bb.0.entry: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: liveins: $r0, $r1, $r2, $r7, $lr + ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK: $lr = t2DLS $r0 + ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg + ; CHECK: bb.1.preheader: + ; CHECK: successors: %bb.2(0x80000000) + ; CHECK: liveins: $r0 + ; CHECK: $lr = tMOVr $r0, 14, $noreg + ; CHECK: bb.2.while.body: + ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK: liveins: $lr, $r0, $r1 + ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) + ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) + ; CHECK: $lr = t2LEUpdate renamable $lr, %bb.2 + ; CHECK: bb.3.while.end: + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr - + frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -106,17 +128,17 @@ body: | successors: %bb.2(0x80000000) liveins: $r0 $lr = tMOVr $r0, 14, $noreg - + bb.2.while.body: successors: %bb.2(0x7c000000), %bb.3(0x04000000) liveins: $lr, $r0, $r1 - + renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) renamable $lr = t2LoopDec killed renamable $lr, 1 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr tB %bb.3, 14, $noreg - + bb.3.while.end: $r0, dead $cpsr = tMOVi8 0, 14, $noreg tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir index acb7ebd35f3fd..458ae06454c49 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir @@ -1,30 +1,27 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=armv8.1m.main -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s -# CHECK: entry: -# CHECK: $lr = t2DLS -# CHECK: for.body: -# CHECK: $lr = t2LEUpdate renamable $lr --- | ; ModuleID = 'size-limit.ll' source_filename = "size-limit.ll" target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv8.1m.main" - + define dso_local arm_aapcscc void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) { entry: %cmp8 = icmp eq i32 %N, 0 br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader - + for.body.preheader: ; preds = %entry %scevgep = getelementptr i32, i32* %a, i32 -1 %scevgep4 = getelementptr i32, i32* %c, i32 -1 %scevgep8 = getelementptr i32, i32* %b, i32 -1 call void @llvm.set.loop.iterations.i32(i32 %N) br label %for.body - + for.cond.cleanup: ; preds = %for.body, %entry ret void - + for.body: ; preds = %for.body, %for.body.preheader %lsr.iv9 = phi i32* [ %scevgep8, %for.body.preheader ], [ %scevgep10, %for.body ] %lsr.iv5 = phi i32* [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ] @@ -45,19 +42,19 @@ %4 = icmp ne i32 %3, 0 br i1 %4, label %for.body, label %for.cond.cleanup } - + ; Function Attrs: nounwind declare i32 @llvm.arm.space(i32 immarg, i32) #0 - + ; Function Attrs: noduplicate nounwind declare void @llvm.set.loop.iterations.i32(i32) #1 - + ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 - + ; Function Attrs: nounwind declare void @llvm.stackprotector(i8*, i8**) #0 - + attributes #0 = { nounwind } attributes #1 = { noduplicate nounwind } @@ -99,20 +96,46 @@ frameInfo: restorePoint: '' fixedStack: [] stack: - - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, + - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, + - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } callSites: [] constants: [] machineFunctionInfo: {} body: | + ; CHECK-LABEL: name: size_limit + ; CHECK: bb.0.entry: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: liveins: $r0, $r1, $r2, $r3, $r7, $lr + ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK: tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: t2IT 0, 8, implicit-def $itstate + ; CHECK: tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg + ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg + ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg + ; CHECK: $lr = t2DLS killed $r3 + ; CHECK: bb.1.for.body: + ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) + ; CHECK: liveins: $lr, $r0, $r1, $r2 + ; CHECK: dead renamable $r3 = SPACE 4070, undef renamable $r0 + ; CHECK: renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep3) + ; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7) + ; CHECK: renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14, $noreg + ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep11) + ; CHECK: $lr = t2LEUpdate renamable $lr, %bb.1 + ; CHECK: bb.2.for.cond.cleanup: + ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr - + frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -125,11 +148,11 @@ body: | renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg $lr = tMOVr $r3, 14, $noreg t2DoLoopStart killed $r3 - + bb.1.for.body: successors: %bb.1(0x7c000000), %bb.2(0x04000000) liveins: $lr, $r0, $r1, $r2 - + dead renamable $r3 = SPACE 4070, undef renamable $r0 renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep3) renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7) @@ -138,7 +161,7 @@ body: | renamable $lr = t2LoopDec killed renamable $lr, 1 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr tB %bb.2, 14, $noreg - + bb.2.for.cond.cleanup: tPOP_RET 14, $noreg, def $r7, def $pc