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[X86] Remove some more code from combineShuffle that is no longer nee…

…ded with widening legalization.

llvm-svn: 368523
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topperc committed Aug 11, 2019
1 parent 0f74b82 commit 9758e0e1bf8545d27a10616fb85e2967a084e2db
Showing with 0 additions and 47 deletions.
  1. +0 −47 llvm/lib/Target/X86/X86ISelLowering.cpp
}
}


// Look for a truncating shuffle to v2i32 of a PMULUDQ where one of the
// operands is an extend from v2i32 to v2i64. Turn it into a pmulld.
// FIXME: This can probably go away once we default to widening legalization.
if (Subtarget.hasSSE41() && VT == MVT::v4i32 &&
N->getOpcode() == ISD::VECTOR_SHUFFLE &&
N->getOperand(0).getOpcode() == ISD::BITCAST &&
N->getOperand(0).getOperand(0).getOpcode() == X86ISD::PMULUDQ) {
SDValue BC = N->getOperand(0);
SDValue MULUDQ = BC.getOperand(0);
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
ArrayRef<int> Mask = SVOp->getMask();
if (BC.hasOneUse() && MULUDQ.hasOneUse() &&
Mask[0] == 0 && Mask[1] == 2 && Mask[2] == -1 && Mask[3] == -1) {
SDValue Op0 = MULUDQ.getOperand(0);
SDValue Op1 = MULUDQ.getOperand(1);
if (Op0.getOpcode() == ISD::BITCAST &&
Op0.getOperand(0).getOpcode() == ISD::VECTOR_SHUFFLE &&
Op0.getOperand(0).getValueType() == MVT::v4i32) {
ShuffleVectorSDNode *SVOp0 =
cast<ShuffleVectorSDNode>(Op0.getOperand(0));
ArrayRef<int> Mask2 = SVOp0->getMask();
if (Mask2[0] == 0 && Mask2[1] == -1 &&
Mask2[2] == 1 && Mask2[3] == -1) {
Op0 = SVOp0->getOperand(0);
Op1 = DAG.getBitcast(MVT::v4i32, Op1);
Op1 = DAG.getVectorShuffle(MVT::v4i32, dl, Op1, Op1, Mask);
return DAG.getNode(ISD::MUL, dl, MVT::v4i32, Op0, Op1);
}
}
if (Op1.getOpcode() == ISD::BITCAST &&
Op1.getOperand(0).getOpcode() == ISD::VECTOR_SHUFFLE &&
Op1.getOperand(0).getValueType() == MVT::v4i32) {
ShuffleVectorSDNode *SVOp1 =
cast<ShuffleVectorSDNode>(Op1.getOperand(0));
ArrayRef<int> Mask2 = SVOp1->getMask();
if (Mask2[0] == 0 && Mask2[1] == -1 &&
Mask2[2] == 1 && Mask2[3] == -1) {
Op0 = DAG.getBitcast(MVT::v4i32, Op0);
Op0 = DAG.getVectorShuffle(MVT::v4i32, dl, Op0, Op0, Mask);
Op1 = SVOp1->getOperand(0);
return DAG.getNode(ISD::MUL, dl, MVT::v4i32, Op0, Op1);
}
}
}
}

return SDValue();
}

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