diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index ecf11bd986f80..56b2981353d97 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -20,7 +20,8 @@ static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
   for (auto Instr : Res) {
     bool Compressed;
     switch (Instr.Opc) {
-    default: llvm_unreachable("Unexpected opcode");
+    default:
+      llvm_unreachable("Unexpected opcode");
     case RISCV::SLLI:
     case RISCV::SRLI:
       Compressed = true;
@@ -122,6 +123,14 @@ static void generateInstSeqImpl(int64_t Val,
     }
   }
 
+  // Try to use SLLIUW for Hi52 when it is uint32 but not int32.
+  if (isUInt<32>((uint64_t)Hi52) && !isInt<32>((uint64_t)Hi52) &&
+      ActiveFeatures[RISCV::FeatureStdExtZba]) {
+    // Use LUI+ADDI or LUI to compose, then clear the upper 32 bits with SLLIUW.
+    Hi52 = ((uint64_t)Hi52) | (0xffffffffull << 32);
+    Unsigned = true;
+  }
+
   generateInstSeqImpl(Hi52, ActiveFeatures, Res);
 
   if (Unsigned)
@@ -281,8 +290,7 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
 }
 
 int getIntMatCost(const APInt &Val, unsigned Size,
-                  const FeatureBitset &ActiveFeatures,
-                  bool CompressionCost) {
+                  const FeatureBitset &ActiveFeatures, bool CompressionCost) {
   bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
   bool HasRVC = CompressionCost && ActiveFeatures[RISCV::FeatureStdExtC];
   int PlatRegSize = IsRV64 ? 64 : 32;
diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll
index cac757c7b7943..1ce3ebd55ae64 100644
--- a/llvm/test/CodeGen/RISCV/imm.ll
+++ b/llvm/test/CodeGen/RISCV/imm.ll
@@ -1599,10 +1599,9 @@ define i64 @imm_12900936431479() {
 ;
 ; RV64IZBA-LABEL: imm_12900936431479:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    lui a0, 192239
-; RV64IZBA-NEXT:    slli a0, a0, 2
-; RV64IZBA-NEXT:    addi a0, a0, -1093
-; RV64IZBA-NEXT:    slli a0, a0, 12
+; RV64IZBA-NEXT:    lui a0, 768956
+; RV64IZBA-NEXT:    addiw a0, a0, -1093
+; RV64IZBA-NEXT:    slli.uw a0, a0, 12
 ; RV64IZBA-NEXT:    addi a0, a0, 1911
 ; RV64IZBA-NEXT:    ret
 ;
@@ -1638,11 +1637,9 @@ define i64 @imm_12900918536874() {
 ;
 ; RV64IZBA-LABEL: imm_12900918536874:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    lui a0, 188
-; RV64IZBA-NEXT:    addiw a0, a0, -1093
-; RV64IZBA-NEXT:    slli a0, a0, 12
-; RV64IZBA-NEXT:    addi a0, a0, -1365
-; RV64IZBA-NEXT:    slli a0, a0, 12
+; RV64IZBA-NEXT:    lui a0, 768955
+; RV64IZBA-NEXT:    addiw a0, a0, -1365
+; RV64IZBA-NEXT:    slli.uw a0, a0, 12
 ; RV64IZBA-NEXT:    addi a0, a0, -1366
 ; RV64IZBA-NEXT:    ret
 ;
@@ -1679,11 +1676,9 @@ define i64 @imm_12900925247761() {
 ;
 ; RV64IZBA-LABEL: imm_12900925247761:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    lui a0, 188
-; RV64IZBA-NEXT:    addiw a0, a0, -1093
-; RV64IZBA-NEXT:    slli a0, a0, 12
-; RV64IZBA-NEXT:    addi a0, a0, 273
-; RV64IZBA-NEXT:    slli a0, a0, 12
+; RV64IZBA-NEXT:    lui a0, 768955
+; RV64IZBA-NEXT:    addiw a0, a0, 273
+; RV64IZBA-NEXT:    slli.uw a0, a0, 12
 ; RV64IZBA-NEXT:    addi a0, a0, 273
 ; RV64IZBA-NEXT:    ret
 ;
diff --git a/llvm/test/MC/RISCV/rv64zba-aliases-valid.s b/llvm/test/MC/RISCV/rv64zba-aliases-valid.s
index 1ee4567b6c620..d7606f805a1b1 100644
--- a/llvm/test/MC/RISCV/rv64zba-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv64zba-aliases-valid.s
@@ -87,42 +87,32 @@ li x6, 16116864687
 # CHECK-S-OBJ-NEXT: sh3add t1, t1, t1
 li x6, -16116864687
 
-# CHECK-S-OBJ-NOALIASZBS: lui t2, 192239
-# CHECK-S-OBJ-NOALIASZBS-NEXT: slli t2, t2, 2
-# CHECK-S-OBJ-NOALIASZBS-NEXT: addi t2, t2, -1093
-# CHECK-S-OBJ-NOALIASZBS-NEXT: slli t2, t2, 12
+# CHECK-S-OBJ-NOALIASZBS: lui t2, 768956
+# CHECK-S-OBJ-NOALIASZBS-NEXT: addiw t2, t2, -1093
+# CHECK-S-OBJ-NOALIASZBS-NEXT: slli.uw t2, t2, 12
 # CHECK-S-OBJ-NOALIASZBS-NEXT: addi t2, t2, 1911
-# CHECK-S-OBJ: lui t2, 192239
-# CHECK-S-OBJ-NEXT: slli t2, t2, 2
-# CHECK-S-OBJ-NEXT: addi t2, t2, -1093
-# CHECK-S-OBJ-NEXT: slli t2, t2, 12
+# CHECK-S-OBJ: lui t2, 768956
+# CHECK-S-OBJ-NEXT: addiw t2, t2, -1093
+# CHECK-S-OBJ-NEXT: slli.uw t2, t2, 12
 # CHECK-S-OBJ-NEXT: addi t2, t2, 1911
 li x7, 12900936431479
 
-# CHECK-S-OBJ-NOALIASZBS: lui t1, 188
-# CHECK-S-OBJ-NOALIASZBS-NEXT: addiw t1, t1, -1093
-# CHECK-S-OBJ-NOALIASZBS-NEXT: slli t1, t1, 12
+# CHECK-S-OBJ-NOALIASZBS: lui t1, 768955
+# CHECK-S-OBJ-NOALIASZBS-NEXT: addiw t1, t1, 273
+# CHECK-S-OBJ-NOALIASZBS-NEXT: slli.uw t1, t1, 12
 # CHECK-S-OBJ-NOALIASZBS-NEXT: addi t1, t1, 273
-# CHECK-S-OBJ-NOALIASZBS-NEXT: slli t1, t1, 12
-# CHECK-S-OBJ-NOALIASZBS-NEXT: addi t1, t1, 273
-# CHECK-S-OBJ: lui t1, 188
-# CHECK-S-OBJ-NEXT: addiw t1, t1, -1093
-# CHECK-S-OBJ-NEXT: slli t1, t1, 12
-# CHECK-S-OBJ-NEXT: addi t1, t1, 273
-# CHECK-S-OBJ-NEXT: slli t1, t1, 12
+# CHECK-S-OBJ: lui t1, 768955
+# CHECK-S-OBJ-NEXT: addiw t1, t1, 273
+# CHECK-S-OBJ-NEXT: slli.uw t1, t1, 12
 # CHECK-S-OBJ-NEXT: addi t1, t1, 273
 li x6, 12900925247761
 
-# CHECK-S-OBJ-NOALIASZBS: lui t1, 188
-# CHECK-S-OBJ-NOALIASZBS-NEXT: addiw t1, t1, -1093
-# CHECK-S-OBJ-NOALIASZBS-NEXT: slli t1, t1, 12
-# CHECK-S-OBJ-NOALIASZBS-NEXT: addi t1, t1, -1365
-# CHECK-S-OBJ-NOALIASZBS-NEXT: slli t1, t1, 12
+# CHECK-S-OBJ-NOALIASZBS: lui t1, 768955
+# CHECK-S-OBJ-NOALIASZBS-NEXT: addiw t1, t1, -1365
+# CHECK-S-OBJ-NOALIASZBS-NEXT: slli.uw t1, t1, 12
 # CHECK-S-OBJ-NOALIASZBS-NEXT: addi t1, t1, -1366
-# CHECK-S-OBJ: lui t1, 188
-# CHECK-S-OBJ-NEXT: addiw t1, t1, -1093
-# CHECK-S-OBJ-NEXT: slli t1, t1, 12
-# CHECK-S-OBJ-NEXT: addi t1, t1, -1365
-# CHECK-S-OBJ-NEXT: slli t1, t1, 12
+# CHECK-S-OBJ: lui t1, 768955
+# CHECK-S-OBJ-NEXT: addiw t1, t1, -1365
+# CHECK-S-OBJ-NEXT: slli.uw t1, t1, 12
 # CHECK-S-OBJ-NEXT: addi t1, t1, -1366
 li x6, 12900918536874