From 9fcd605d1e3d847adb57f926a89138368f61c306 Mon Sep 17 00:00:00 2001 From: Bjorn Pettersson Date: Fri, 21 Oct 2016 09:53:42 +0000 Subject: [PATCH] [AArch64] Corrected spill size for DDD register class. NFCI Summary: The spill size was incorrectly set to 196 bits, which isn't a multiple of 8. This problem was detected when experimenting with asserts that the spill size should be a multiple of the byte size. New corrected value for the spill size is set to 192 bits. Note that tablegen (RegisterInfoEmitter) will divide the size set in the RegisterClass definition by 8. So this change should not have any impact on the tablegen output (trunc(192/8) == trunc(196/8) == 24 bytes). Reviewers: t.p.northover Subscribers: llvm-commits, aemerson, rengolin Differential Revision: https://reviews.llvm.org/D25818 llvm-svn: 284814 --- llvm/lib/Target/AArch64/AArch64RegisterInfo.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td index 5fbaff00a5e71..7e29ee5e9bafe 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td @@ -422,7 +422,7 @@ def DD : RegisterClass<"AArch64", [untyped], 64, (add DSeqPairs)> { let Size = 128; } def DDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqTriples)> { - let Size = 196; + let Size = 192; } def DDDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqQuads)> { let Size = 256;