diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index bdb9d0317942b..265eb831998e8 100644 --- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -1649,6 +1649,49 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, MCRegister &RegNo, RegKind = SparcOperand::rk_Special; return true; } + + // JPS1 extension - aliases for ASRs + // Section A.51 - Read State Register + if (name.equals("pcr")) { + RegNo = Sparc::ASR16; + RegKind = SparcOperand::rk_Special; + return true; + } + if (name.equals("pic")) { + RegNo = Sparc::ASR17; + RegKind = SparcOperand::rk_Special; + return true; + } + if (name.equals("dcr")) { + RegNo = Sparc::ASR18; + RegKind = SparcOperand::rk_Special; + return true; + } + if (name.equals("gsr")) { + RegNo = Sparc::ASR19; + RegKind = SparcOperand::rk_Special; + return true; + } + if (name.equals("softint")) { + RegNo = Sparc::ASR22; + RegKind = SparcOperand::rk_Special; + return true; + } + if (name.equals("tick_cmpr")) { + RegNo = Sparc::ASR23; + RegKind = SparcOperand::rk_Special; + return true; + } + if (name.equals("stick") || name.equals("sys_tick")) { + RegNo = Sparc::ASR24; + RegKind = SparcOperand::rk_Special; + return true; + } + if (name.equals("stick_cmpr") || name.equals("sys_tick_cmpr")) { + RegNo = Sparc::ASR25; + RegKind = SparcOperand::rk_Special; + return true; + } } return false; } diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td b/llvm/lib/Target/Sparc/SparcInstrAliases.td index 26ea043149d62..dcc6ec3c97145 100644 --- a/llvm/lib/Target/Sparc/SparcInstrAliases.td +++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td @@ -350,6 +350,8 @@ defm : int_cond_alias<"vs", 0b0111>; let EmitPriority = 0 in { defm : int_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual + defm : int_cond_alias<"gt", 0b1010>; // same as g; gnu asm, not in manual + defm : int_cond_alias<"lt", 0b0011>; // same as l; gnu asm, not in manual defm : int_cond_alias<"nz", 0b1001>; // same as ne defm : int_cond_alias<"eq", 0b0001>; // same as e defm : int_cond_alias<"z", 0b0001>; // same as e @@ -537,6 +539,11 @@ def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>; // End of Section A.3 +// or imm, reg, rd -> or reg, imm, rd +// Nonstandard GNU extension. +let EmitPriority = 0 in + def : InstAlias<"or $simm13, $rs1, $rd", (ORri IntRegs:$rd, IntRegs:$rs1, simm13Op:$simm13)>; + // wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg // (aka: omit the first arg when it's g0. This is not in the manual, but is // supported by gnu and solaris as) @@ -579,7 +586,14 @@ def : MnemonicAlias<"stsh", "sth">; def : MnemonicAlias<"stuha", "stha">; def : MnemonicAlias<"stsha", "stha">; + def : MnemonicAlias<"stw", "st">, Requires<[HasV9]>; +def : MnemonicAlias<"stuw", "st">, Requires<[HasV9]>; +def : MnemonicAlias<"stsw", "st">, Requires<[HasV9]>; + +def : MnemonicAlias<"stwa", "sta">, Requires<[HasV9]>; +def : MnemonicAlias<"stuwa", "sta">, Requires<[HasV9]>; +def : MnemonicAlias<"stswa", "sta">, Requires<[HasV9]>; def : MnemonicAlias<"lduw", "ld">, Requires<[HasV9]>; def : MnemonicAlias<"lduwa", "lda">, Requires<[HasV9]>; diff --git a/llvm/test/MC/Sparc/sparc-ctrl-instructions.s b/llvm/test/MC/Sparc/sparc-ctrl-instructions.s index 74356b40720d1..ef65bbe2c7893 100644 --- a/llvm/test/MC/Sparc/sparc-ctrl-instructions.s +++ b/llvm/test/MC/Sparc/sparc-ctrl-instructions.s @@ -79,6 +79,10 @@ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 bg .BB0 + ! CHECK: bg .BB0 ! encoding: [0x14,0b10AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + bgt .BB0 + ! CHECK: ble .BB0 ! encoding: [0x04,0b10AAAAAA,A,A] ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 ble .BB0 @@ -91,6 +95,10 @@ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 bl .BB0 + ! CHECK: bl .BB0 ! encoding: [0x06,0b10AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + blt .BB0 + ! CHECK: bgu .BB0 ! encoding: [0x18,0b10AAAAAA,A,A] ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 bgu .BB0 diff --git a/llvm/test/MC/Sparc/sparc-synthetic-instructions.s b/llvm/test/MC/Sparc/sparc-synthetic-instructions.s index f83c8c2893acd..3cea9fe48bc85 100644 --- a/llvm/test/MC/Sparc/sparc-synthetic-instructions.s +++ b/llvm/test/MC/Sparc/sparc-synthetic-instructions.s @@ -163,6 +163,8 @@ wr %i0, %tbr ! CHECK: wr %g0, 5, %tbr ! encoding: [0x81,0x98,0x20,0x05] wr 5, %tbr + ! CHECK: or %g2, 4, %g2 ! encoding: [0x84,0x10,0xa0,0x04] + or 4, %g2, %g2 ! The following tests exercise 'set' in such a way that its output differs ! depending on whether targeting V8 or V9. diff --git a/llvm/test/MC/Sparc/sparcv9-instructions.s b/llvm/test/MC/Sparc/sparcv9-instructions.s index c4c44060ed3df..5fc31d1e939fd 100644 --- a/llvm/test/MC/Sparc/sparcv9-instructions.s +++ b/llvm/test/MC/Sparc/sparcv9-instructions.s @@ -495,6 +495,17 @@ ! V9: st %o1, [%o0] ! encoding: [0xd2,0x22,0x00,0x00] stw %o1, [%o0] + ! V9: st %o1, [%o0] ! encoding: [0xd2,0x22,0x00,0x00] + stuw %o1, [%o0] + ! V9: st %o1, [%o0] ! encoding: [0xd2,0x22,0x00,0x00] + stsw %o1, [%o0] + + ! V9: sta %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xa6,0x10,0x76] + stwa %o2, [%i0 + %l6] 131 + ! V9: sta %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xa6,0x10,0x76] + stuwa %o2, [%i0 + %l6] 131 + ! V9: sta %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xa6,0x10,0x76] + stswa %o2, [%i0 + %l6] 131 !! SPARCv9 provides a new variant of ASI-tagged memory accesses. ! V9: ldxa [%g2] %asi, %g0 ! encoding: [0xc0,0xd8,0xa0,0x00]