diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index c6a2d03f5d31a7..b5a0d13145f132 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -4726,7 +4726,7 @@ SDValue RISCVTargetLowering::lowerShiftLeftParts(SDValue Op, SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT); SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT); SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen); - SDValue XLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, XLenMinus1); + SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt); SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); @@ -4776,7 +4776,7 @@ SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT); SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT); SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen); - SDValue XLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, XLenMinus1); + SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt); SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One); diff --git a/llvm/test/CodeGen/RISCV/alu64.ll b/llvm/test/CodeGen/RISCV/alu64.ll index 2552442936326e..5b7510ab982b76 100644 --- a/llvm/test/CodeGen/RISCV/alu64.ll +++ b/llvm/test/CodeGen/RISCV/alu64.ll @@ -215,7 +215,7 @@ define i64 @sll(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: j .LBB11_3 ; RV32I-NEXT: .LBB11_2: ; RV32I-NEXT: sll a1, a1, a2 -; RV32I-NEXT: xori a2, a2, 31 +; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srl a0, a0, a2 ; RV32I-NEXT: or a1, a1, a0 @@ -303,7 +303,7 @@ define i64 @srl(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: j .LBB15_3 ; RV32I-NEXT: .LBB15_2: ; RV32I-NEXT: srl a0, a0, a2 -; RV32I-NEXT: xori a2, a2, 31 +; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: sll a1, a1, a2 ; RV32I-NEXT: or a0, a0, a1 @@ -335,7 +335,7 @@ define i64 @sra(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: ret ; RV32I-NEXT: .LBB16_2: ; RV32I-NEXT: srl a0, a0, a2 -; RV32I-NEXT: xori a2, a2, 31 +; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: slli a3, a3, 1 ; RV32I-NEXT: sll a2, a3, a2 ; RV32I-NEXT: or a0, a0, a2 diff --git a/llvm/test/CodeGen/RISCV/rotl-rotr.ll b/llvm/test/CodeGen/RISCV/rotl-rotr.ll index b0e4e18307fc5c..f735d217751143 100644 --- a/llvm/test/CodeGen/RISCV/rotl-rotr.ll +++ b/llvm/test/CodeGen/RISCV/rotl-rotr.ll @@ -93,7 +93,7 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind { ; RV32I-NEXT: j .LBB2_3 ; RV32I-NEXT: .LBB2_2: ; RV32I-NEXT: sll a3, a1, a2 -; RV32I-NEXT: xori a6, a2, 31 +; RV32I-NEXT: not a6, a2 ; RV32I-NEXT: srli a7, a0, 1 ; RV32I-NEXT: srl a6, a7, a6 ; RV32I-NEXT: or a3, a3, a6 @@ -111,7 +111,7 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind { ; RV32I-NEXT: srl a0, a0, a7 ; RV32I-NEXT: li a7, 64 ; RV32I-NEXT: sub a2, a7, a2 -; RV32I-NEXT: xori a2, a2, 31 +; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: sll a1, a1, a2 ; RV32I-NEXT: or a0, a0, a1 @@ -143,7 +143,7 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind { ; RV32ZBB-NEXT: j .LBB2_3 ; RV32ZBB-NEXT: .LBB2_2: ; RV32ZBB-NEXT: sll a3, a1, a2 -; RV32ZBB-NEXT: xori a6, a2, 31 +; RV32ZBB-NEXT: not a6, a2 ; RV32ZBB-NEXT: srli a7, a0, 1 ; RV32ZBB-NEXT: srl a6, a7, a6 ; RV32ZBB-NEXT: or a3, a3, a6 @@ -161,7 +161,7 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind { ; RV32ZBB-NEXT: srl a0, a0, a7 ; RV32ZBB-NEXT: li a7, 64 ; RV32ZBB-NEXT: sub a2, a7, a2 -; RV32ZBB-NEXT: xori a2, a2, 31 +; RV32ZBB-NEXT: not a2, a2 ; RV32ZBB-NEXT: slli a1, a1, 1 ; RV32ZBB-NEXT: sll a1, a1, a2 ; RV32ZBB-NEXT: or a0, a0, a1 @@ -197,7 +197,7 @@ define i64 @rotr_64(i64 %x, i64 %y) nounwind { ; RV32I-NEXT: j .LBB3_3 ; RV32I-NEXT: .LBB3_2: ; RV32I-NEXT: srl a3, a0, a2 -; RV32I-NEXT: xori a6, a2, 31 +; RV32I-NEXT: not a6, a2 ; RV32I-NEXT: slli a7, a1, 1 ; RV32I-NEXT: sll a6, a7, a6 ; RV32I-NEXT: or a3, a3, a6 @@ -215,7 +215,7 @@ define i64 @rotr_64(i64 %x, i64 %y) nounwind { ; RV32I-NEXT: sll a1, a1, a7 ; RV32I-NEXT: li a7, 64 ; RV32I-NEXT: sub a2, a7, a2 -; RV32I-NEXT: xori a2, a2, 31 +; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srl a0, a0, a2 ; RV32I-NEXT: or a1, a1, a0 @@ -247,7 +247,7 @@ define i64 @rotr_64(i64 %x, i64 %y) nounwind { ; RV32ZBB-NEXT: j .LBB3_3 ; RV32ZBB-NEXT: .LBB3_2: ; RV32ZBB-NEXT: srl a3, a0, a2 -; RV32ZBB-NEXT: xori a6, a2, 31 +; RV32ZBB-NEXT: not a6, a2 ; RV32ZBB-NEXT: slli a7, a1, 1 ; RV32ZBB-NEXT: sll a6, a7, a6 ; RV32ZBB-NEXT: or a3, a3, a6 @@ -265,7 +265,7 @@ define i64 @rotr_64(i64 %x, i64 %y) nounwind { ; RV32ZBB-NEXT: sll a1, a1, a7 ; RV32ZBB-NEXT: li a7, 64 ; RV32ZBB-NEXT: sub a2, a7, a2 -; RV32ZBB-NEXT: xori a2, a2, 31 +; RV32ZBB-NEXT: not a2, a2 ; RV32ZBB-NEXT: srli a0, a0, 1 ; RV32ZBB-NEXT: srl a0, a0, a2 ; RV32ZBB-NEXT: or a1, a1, a0 @@ -511,7 +511,7 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind { ; RV32I-NEXT: j .LBB10_3 ; RV32I-NEXT: .LBB10_2: ; RV32I-NEXT: sll a3, a1, a2 -; RV32I-NEXT: xori a6, a2, 31 +; RV32I-NEXT: not a6, a2 ; RV32I-NEXT: srli a7, a0, 1 ; RV32I-NEXT: srl a6, a7, a6 ; RV32I-NEXT: or a3, a3, a6 @@ -532,7 +532,7 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind { ; RV32I-NEXT: j .LBB10_6 ; RV32I-NEXT: .LBB10_5: ; RV32I-NEXT: srl a0, a0, a6 -; RV32I-NEXT: xori a5, a5, 31 +; RV32I-NEXT: not a5, a5 ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: sll a1, a1, a5 ; RV32I-NEXT: or a0, a0, a1 @@ -559,7 +559,7 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind { ; RV32ZBB-NEXT: j .LBB10_3 ; RV32ZBB-NEXT: .LBB10_2: ; RV32ZBB-NEXT: sll a3, a1, a2 -; RV32ZBB-NEXT: xori a6, a2, 31 +; RV32ZBB-NEXT: not a6, a2 ; RV32ZBB-NEXT: srli a7, a0, 1 ; RV32ZBB-NEXT: srl a6, a7, a6 ; RV32ZBB-NEXT: or a3, a3, a6 @@ -580,7 +580,7 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind { ; RV32ZBB-NEXT: j .LBB10_6 ; RV32ZBB-NEXT: .LBB10_5: ; RV32ZBB-NEXT: srl a0, a0, a6 -; RV32ZBB-NEXT: xori a5, a5, 31 +; RV32ZBB-NEXT: not a5, a5 ; RV32ZBB-NEXT: slli a1, a1, 1 ; RV32ZBB-NEXT: sll a1, a1, a5 ; RV32ZBB-NEXT: or a0, a0, a1 @@ -613,7 +613,7 @@ define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind { ; RV32I-NEXT: .LBB11_2: ; RV32I-NEXT: sll a5, a1, a2 ; RV32I-NEXT: srli a6, a0, 1 -; RV32I-NEXT: xori a3, a3, 31 +; RV32I-NEXT: not a3, a3 ; RV32I-NEXT: srl a3, a6, a3 ; RV32I-NEXT: or a3, a5, a3 ; RV32I-NEXT: .LBB11_3: @@ -634,7 +634,7 @@ define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind { ; RV32I-NEXT: j .LBB11_6 ; RV32I-NEXT: .LBB11_5: ; RV32I-NEXT: srl a0, a0, a6 -; RV32I-NEXT: xori a5, a5, 31 +; RV32I-NEXT: not a5, a5 ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: sll a1, a1, a5 ; RV32I-NEXT: or a0, a0, a1 @@ -662,7 +662,7 @@ define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind { ; RV32ZBB-NEXT: .LBB11_2: ; RV32ZBB-NEXT: sll a5, a1, a2 ; RV32ZBB-NEXT: srli a6, a0, 1 -; RV32ZBB-NEXT: xori a3, a3, 31 +; RV32ZBB-NEXT: not a3, a3 ; RV32ZBB-NEXT: srl a3, a6, a3 ; RV32ZBB-NEXT: or a3, a5, a3 ; RV32ZBB-NEXT: .LBB11_3: @@ -683,7 +683,7 @@ define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind { ; RV32ZBB-NEXT: j .LBB11_6 ; RV32ZBB-NEXT: .LBB11_5: ; RV32ZBB-NEXT: srl a0, a0, a6 -; RV32ZBB-NEXT: xori a5, a5, 31 +; RV32ZBB-NEXT: not a5, a5 ; RV32ZBB-NEXT: slli a1, a1, 1 ; RV32ZBB-NEXT: sll a1, a1, a5 ; RV32ZBB-NEXT: or a0, a0, a1 @@ -758,7 +758,7 @@ define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind { ; RV32I-NEXT: j .LBB13_3 ; RV32I-NEXT: .LBB13_2: ; RV32I-NEXT: srl a3, a0, a2 -; RV32I-NEXT: xori a6, a2, 31 +; RV32I-NEXT: not a6, a2 ; RV32I-NEXT: slli a7, a1, 1 ; RV32I-NEXT: sll a6, a7, a6 ; RV32I-NEXT: or a3, a3, a6 @@ -773,7 +773,7 @@ define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind { ; RV32I-NEXT: j .LBB13_6 ; RV32I-NEXT: .LBB13_5: ; RV32I-NEXT: sll a1, a1, a6 -; RV32I-NEXT: xori a4, t0, 31 +; RV32I-NEXT: not a4, t0 ; RV32I-NEXT: srli a5, a0, 1 ; RV32I-NEXT: srl a4, a5, a4 ; RV32I-NEXT: or a1, a1, a4 @@ -806,7 +806,7 @@ define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind { ; RV32ZBB-NEXT: j .LBB13_3 ; RV32ZBB-NEXT: .LBB13_2: ; RV32ZBB-NEXT: srl a3, a0, a2 -; RV32ZBB-NEXT: xori a6, a2, 31 +; RV32ZBB-NEXT: not a6, a2 ; RV32ZBB-NEXT: slli a7, a1, 1 ; RV32ZBB-NEXT: sll a6, a7, a6 ; RV32ZBB-NEXT: or a3, a3, a6 @@ -821,7 +821,7 @@ define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind { ; RV32ZBB-NEXT: j .LBB13_6 ; RV32ZBB-NEXT: .LBB13_5: ; RV32ZBB-NEXT: sll a1, a1, a6 -; RV32ZBB-NEXT: xori a4, t0, 31 +; RV32ZBB-NEXT: not a4, t0 ; RV32ZBB-NEXT: srli a5, a0, 1 ; RV32ZBB-NEXT: srl a4, a5, a4 ; RV32ZBB-NEXT: or a1, a1, a4 @@ -861,7 +861,7 @@ define i64 @rotr_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind { ; RV32I-NEXT: .LBB14_2: ; RV32I-NEXT: srl a6, a0, a2 ; RV32I-NEXT: slli a7, a1, 1 -; RV32I-NEXT: xori a3, a3, 31 +; RV32I-NEXT: not a3, a3 ; RV32I-NEXT: sll a3, a7, a3 ; RV32I-NEXT: or a3, a6, a3 ; RV32I-NEXT: .LBB14_3: @@ -875,7 +875,7 @@ define i64 @rotr_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind { ; RV32I-NEXT: j .LBB14_6 ; RV32I-NEXT: .LBB14_5: ; RV32I-NEXT: sll a1, a1, a6 -; RV32I-NEXT: xori a4, t0, 31 +; RV32I-NEXT: not a4, t0 ; RV32I-NEXT: srli a5, a0, 1 ; RV32I-NEXT: srl a4, a5, a4 ; RV32I-NEXT: or a1, a1, a4 @@ -910,7 +910,7 @@ define i64 @rotr_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind { ; RV32ZBB-NEXT: .LBB14_2: ; RV32ZBB-NEXT: srl a6, a0, a2 ; RV32ZBB-NEXT: slli a7, a1, 1 -; RV32ZBB-NEXT: xori a3, a3, 31 +; RV32ZBB-NEXT: not a3, a3 ; RV32ZBB-NEXT: sll a3, a7, a3 ; RV32ZBB-NEXT: or a3, a6, a3 ; RV32ZBB-NEXT: .LBB14_3: @@ -924,7 +924,7 @@ define i64 @rotr_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind { ; RV32ZBB-NEXT: j .LBB14_6 ; RV32ZBB-NEXT: .LBB14_5: ; RV32ZBB-NEXT: sll a1, a1, a6 -; RV32ZBB-NEXT: xori a4, t0, 31 +; RV32ZBB-NEXT: not a4, t0 ; RV32ZBB-NEXT: srli a5, a0, 1 ; RV32ZBB-NEXT: srl a4, a5, a4 ; RV32ZBB-NEXT: or a1, a1, a4 @@ -1066,7 +1066,7 @@ define signext i64 @rotl_64_mask_shared(i64 signext %a, i64 signext %b, i64 sign ; RV32I-NEXT: .LBB17_6: ; RV32I-NEXT: sll a3, a3, a4 ; RV32I-NEXT: srli a7, a2, 1 -; RV32I-NEXT: xori a6, a6, 31 +; RV32I-NEXT: not a6, a6 ; RV32I-NEXT: srl a6, a7, a6 ; RV32I-NEXT: or a3, a3, a6 ; RV32I-NEXT: .LBB17_7: @@ -1121,7 +1121,7 @@ define signext i64 @rotl_64_mask_shared(i64 signext %a, i64 signext %b, i64 sign ; RV32ZBB-NEXT: .LBB17_6: ; RV32ZBB-NEXT: sll a3, a3, a4 ; RV32ZBB-NEXT: srli a7, a2, 1 -; RV32ZBB-NEXT: xori a6, a6, 31 +; RV32ZBB-NEXT: not a6, a6 ; RV32ZBB-NEXT: srl a6, a7, a6 ; RV32ZBB-NEXT: or a3, a3, a6 ; RV32ZBB-NEXT: .LBB17_7: @@ -1222,7 +1222,7 @@ define signext i64 @rotr_64_mask_shared(i64 signext %a, i64 signext %b, i64 sign ; RV32I-NEXT: .LBB19_6: ; RV32I-NEXT: sll a3, a3, a4 ; RV32I-NEXT: srli a7, a2, 1 -; RV32I-NEXT: xori a5, a5, 31 +; RV32I-NEXT: not a5, a5 ; RV32I-NEXT: srl a5, a7, a5 ; RV32I-NEXT: or a3, a3, a5 ; RV32I-NEXT: .LBB19_7: @@ -1276,7 +1276,7 @@ define signext i64 @rotr_64_mask_shared(i64 signext %a, i64 signext %b, i64 sign ; RV32ZBB-NEXT: .LBB19_6: ; RV32ZBB-NEXT: sll a3, a3, a4 ; RV32ZBB-NEXT: srli a7, a2, 1 -; RV32ZBB-NEXT: xori a5, a5, 31 +; RV32ZBB-NEXT: not a5, a5 ; RV32ZBB-NEXT: srl a5, a7, a5 ; RV32ZBB-NEXT: or a3, a3, a5 ; RV32ZBB-NEXT: .LBB19_7: @@ -1638,7 +1638,7 @@ define i64 @rotl_64_zext(i64 %x, i32 %y) nounwind { ; RV32I-NEXT: j .LBB24_3 ; RV32I-NEXT: .LBB24_2: ; RV32I-NEXT: sll a3, a1, a2 -; RV32I-NEXT: xori a7, a2, 31 +; RV32I-NEXT: not a7, a2 ; RV32I-NEXT: srli t0, a0, 1 ; RV32I-NEXT: srl a7, t0, a7 ; RV32I-NEXT: or a3, a3, a7 @@ -1655,7 +1655,7 @@ define i64 @rotl_64_zext(i64 %x, i32 %y) nounwind { ; RV32I-NEXT: li t0, 64 ; RV32I-NEXT: sub a2, t0, a2 ; RV32I-NEXT: srl a0, a0, a4 -; RV32I-NEXT: xori a2, a2, 31 +; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: sll a1, a1, a2 ; RV32I-NEXT: or a0, a0, a1 @@ -1688,7 +1688,7 @@ define i64 @rotl_64_zext(i64 %x, i32 %y) nounwind { ; RV32ZBB-NEXT: j .LBB24_3 ; RV32ZBB-NEXT: .LBB24_2: ; RV32ZBB-NEXT: sll a3, a1, a2 -; RV32ZBB-NEXT: xori a7, a2, 31 +; RV32ZBB-NEXT: not a7, a2 ; RV32ZBB-NEXT: srli t0, a0, 1 ; RV32ZBB-NEXT: srl a7, t0, a7 ; RV32ZBB-NEXT: or a3, a3, a7 @@ -1705,7 +1705,7 @@ define i64 @rotl_64_zext(i64 %x, i32 %y) nounwind { ; RV32ZBB-NEXT: li t0, 64 ; RV32ZBB-NEXT: sub a2, t0, a2 ; RV32ZBB-NEXT: srl a0, a0, a4 -; RV32ZBB-NEXT: xori a2, a2, 31 +; RV32ZBB-NEXT: not a2, a2 ; RV32ZBB-NEXT: slli a1, a1, 1 ; RV32ZBB-NEXT: sll a1, a1, a2 ; RV32ZBB-NEXT: or a0, a0, a1 @@ -1744,7 +1744,7 @@ define i64 @rotr_64_zext(i64 %x, i32 %y) nounwind { ; RV32I-NEXT: j .LBB25_3 ; RV32I-NEXT: .LBB25_2: ; RV32I-NEXT: srl a3, a0, a2 -; RV32I-NEXT: xori a7, a2, 31 +; RV32I-NEXT: not a7, a2 ; RV32I-NEXT: slli t0, a1, 1 ; RV32I-NEXT: sll a7, t0, a7 ; RV32I-NEXT: or a3, a3, a7 @@ -1761,7 +1761,7 @@ define i64 @rotr_64_zext(i64 %x, i32 %y) nounwind { ; RV32I-NEXT: li t0, 64 ; RV32I-NEXT: sub a2, t0, a2 ; RV32I-NEXT: sll a1, a1, a4 -; RV32I-NEXT: xori a2, a2, 31 +; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srl a0, a0, a2 ; RV32I-NEXT: or a1, a1, a0 @@ -1794,7 +1794,7 @@ define i64 @rotr_64_zext(i64 %x, i32 %y) nounwind { ; RV32ZBB-NEXT: j .LBB25_3 ; RV32ZBB-NEXT: .LBB25_2: ; RV32ZBB-NEXT: srl a3, a0, a2 -; RV32ZBB-NEXT: xori a7, a2, 31 +; RV32ZBB-NEXT: not a7, a2 ; RV32ZBB-NEXT: slli t0, a1, 1 ; RV32ZBB-NEXT: sll a7, t0, a7 ; RV32ZBB-NEXT: or a3, a3, a7 @@ -1811,7 +1811,7 @@ define i64 @rotr_64_zext(i64 %x, i32 %y) nounwind { ; RV32ZBB-NEXT: li t0, 64 ; RV32ZBB-NEXT: sub a2, t0, a2 ; RV32ZBB-NEXT: sll a1, a1, a4 -; RV32ZBB-NEXT: xori a2, a2, 31 +; RV32ZBB-NEXT: not a2, a2 ; RV32ZBB-NEXT: srli a0, a0, 1 ; RV32ZBB-NEXT: srl a0, a0, a2 ; RV32ZBB-NEXT: or a1, a1, a0 diff --git a/llvm/test/CodeGen/RISCV/rv32zbs.ll b/llvm/test/CodeGen/RISCV/rv32zbs.ll index e151465af9ce81..c53e9dbfcdbf30 100644 --- a/llvm/test/CodeGen/RISCV/rv32zbs.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbs.ll @@ -291,7 +291,7 @@ define i64 @bext_i64(i64 %a, i64 %b) nounwind { ; CHECK-NEXT: .LBB12_2: ; CHECK-NEXT: srl a0, a0, a2 ; CHECK-NEXT: slli a1, a1, 1 -; CHECK-NEXT: xori a2, a3, 31 +; CHECK-NEXT: not a2, a3 ; CHECK-NEXT: sll a1, a1, a2 ; CHECK-NEXT: or a0, a0, a1 ; CHECK-NEXT: .LBB12_3: diff --git a/llvm/test/CodeGen/RISCV/shift-amount-mod.ll b/llvm/test/CodeGen/RISCV/shift-amount-mod.ll index ef69758f7a95a6..c57d2b25e08922 100644 --- a/llvm/test/CodeGen/RISCV/shift-amount-mod.ll +++ b/llvm/test/CodeGen/RISCV/shift-amount-mod.ll @@ -36,7 +36,7 @@ define i64 @shl_by_complemented_64(i64 %x) { ; RV32I-NEXT: sll a1, a1, a4 ; RV32I-NEXT: li a4, 63 ; RV32I-NEXT: sub a4, a4, a0 -; RV32I-NEXT: xori a4, a4, 31 +; RV32I-NEXT: not a4, a4 ; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srl a0, a0, a4 ; RV32I-NEXT: or a1, a1, a0 @@ -88,7 +88,7 @@ define i64 @lshr_by_complemented_64(i64 %x) { ; RV32I-NEXT: srl a4, a0, a4 ; RV32I-NEXT: li a5, 63 ; RV32I-NEXT: sub a5, a5, a0 -; RV32I-NEXT: xori a0, a5, 31 +; RV32I-NEXT: not a0, a5 ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: sll a0, a1, a0 ; RV32I-NEXT: or a0, a4, a0 @@ -141,7 +141,7 @@ define i64 @ashr_by_complemented_64(i64 %x) { ; RV32I-NEXT: srl a3, a2, a3 ; RV32I-NEXT: li a4, 63 ; RV32I-NEXT: sub a4, a4, a2 -; RV32I-NEXT: xori a2, a4, 31 +; RV32I-NEXT: not a2, a4 ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: sll a1, a1, a2 ; RV32I-NEXT: or a3, a3, a1 @@ -191,7 +191,7 @@ define i64 @shl_by_masked_complemented_64(i64 %x) { ; RV32I-NEXT: j .LBB7_3 ; RV32I-NEXT: .LBB7_2: ; RV32I-NEXT: sll a1, a1, a3 -; RV32I-NEXT: xori a4, a4, 31 +; RV32I-NEXT: not a4, a4 ; RV32I-NEXT: srli a5, a0, 1 ; RV32I-NEXT: srl a4, a5, a4 ; RV32I-NEXT: or a1, a1, a4 @@ -227,7 +227,7 @@ define i64 @lshr_by_masked_complemented_64(i64 %x) { ; RV32I-NEXT: j .LBB8_3 ; RV32I-NEXT: .LBB8_2: ; RV32I-NEXT: srl a0, a0, a3 -; RV32I-NEXT: xori a4, a4, 31 +; RV32I-NEXT: not a4, a4 ; RV32I-NEXT: slli a5, a1, 1 ; RV32I-NEXT: sll a4, a5, a4 ; RV32I-NEXT: or a0, a0, a4 @@ -266,7 +266,7 @@ define i64 @ashr_by_masked_complemented_64(i64 %x) { ; RV32I-NEXT: not a4, a0 ; RV32I-NEXT: sra a1, a2, a4 ; RV32I-NEXT: srl a0, a0, a4 -; RV32I-NEXT: xori a3, a3, 31 +; RV32I-NEXT: not a3, a3 ; RV32I-NEXT: slli a2, a2, 1 ; RV32I-NEXT: sll a2, a2, a3 ; RV32I-NEXT: or a0, a0, a2 diff --git a/llvm/test/CodeGen/RISCV/shift-masked-shamt.ll b/llvm/test/CodeGen/RISCV/shift-masked-shamt.ll index 96da493be5115a..ad1e0e0153bd69 100644 --- a/llvm/test/CodeGen/RISCV/shift-masked-shamt.ll +++ b/llvm/test/CodeGen/RISCV/shift-masked-shamt.ll @@ -170,7 +170,7 @@ define i64 @sll_redundant_mask_zeros_i64(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: .LBB9_2: ; RV32I-NEXT: sll a1, a1, a2 ; RV32I-NEXT: srli a5, a0, 1 -; RV32I-NEXT: xori a4, a4, 31 +; RV32I-NEXT: not a4, a4 ; RV32I-NEXT: srl a4, a5, a4 ; RV32I-NEXT: or a1, a1, a4 ; RV32I-NEXT: .LBB9_3: @@ -204,7 +204,7 @@ define i64 @srl_redundant_mask_zeros_i64(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: .LBB10_2: ; RV32I-NEXT: srl a0, a0, a2 ; RV32I-NEXT: slli a5, a1, 1 -; RV32I-NEXT: xori a4, a4, 31 +; RV32I-NEXT: not a4, a4 ; RV32I-NEXT: sll a4, a5, a4 ; RV32I-NEXT: or a0, a0, a4 ; RV32I-NEXT: .LBB10_3: @@ -239,7 +239,7 @@ define i64 @sra_redundant_mask_zeros_i64(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: .LBB11_2: ; RV32I-NEXT: srl a0, a0, a2 ; RV32I-NEXT: slli a4, a1, 1 -; RV32I-NEXT: xori a3, a3, 31 +; RV32I-NEXT: not a3, a3 ; RV32I-NEXT: sll a3, a4, a3 ; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: sra a1, a1, a2 diff --git a/llvm/test/CodeGen/RISCV/shifts.ll b/llvm/test/CodeGen/RISCV/shifts.ll index c720b63d3d9e77..ddb8305f9e3516 100644 --- a/llvm/test/CodeGen/RISCV/shifts.ll +++ b/llvm/test/CodeGen/RISCV/shifts.ll @@ -21,7 +21,7 @@ define i64 @lshr64(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: j .LBB0_3 ; RV32I-NEXT: .LBB0_2: ; RV32I-NEXT: srl a0, a0, a2 -; RV32I-NEXT: xori a2, a2, 31 +; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: sll a1, a1, a2 ; RV32I-NEXT: or a0, a0, a1 @@ -71,7 +71,7 @@ define i64 @ashr64(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: ret ; RV32I-NEXT: .LBB2_2: ; RV32I-NEXT: srl a0, a0, a2 -; RV32I-NEXT: xori a2, a2, 31 +; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: slli a3, a3, 1 ; RV32I-NEXT: sll a2, a3, a2 ; RV32I-NEXT: or a0, a0, a2 @@ -114,7 +114,7 @@ define i64 @shl64(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: j .LBB4_3 ; RV32I-NEXT: .LBB4_2: ; RV32I-NEXT: sll a1, a1, a2 -; RV32I-NEXT: xori a2, a2, 31 +; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srl a0, a0, a2 ; RV32I-NEXT: or a1, a1, a0 @@ -162,86 +162,69 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind { ; RV32I-NEXT: neg a3, a2 ; RV32I-NEXT: li t0, 64 ; RV32I-NEXT: li a4, 32 -; RV32I-NEXT: sub a6, a4, a2 +; RV32I-NEXT: sub a7, a4, a2 ; RV32I-NEXT: sll a5, t3, a3 -; RV32I-NEXT: bltz a6, .LBB6_2 +; RV32I-NEXT: bltz a7, .LBB6_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: mv t1, a5 ; RV32I-NEXT: j .LBB6_3 ; RV32I-NEXT: .LBB6_2: ; RV32I-NEXT: sll a3, t2, a3 ; RV32I-NEXT: sub a4, t0, a2 -; RV32I-NEXT: xori a4, a4, 31 -; RV32I-NEXT: srli a7, t3, 1 -; RV32I-NEXT: srl a4, a7, a4 +; RV32I-NEXT: not a4, a4 +; RV32I-NEXT: srli a6, t3, 1 +; RV32I-NEXT: srl a4, a6, a4 ; RV32I-NEXT: or t1, a3, a4 ; RV32I-NEXT: .LBB6_3: ; RV32I-NEXT: srl t4, t5, a2 -; RV32I-NEXT: addi a7, a2, -32 -; RV32I-NEXT: slti a3, a7, 0 +; RV32I-NEXT: addi a6, a2, -32 +; RV32I-NEXT: slti a3, a6, 0 ; RV32I-NEXT: neg a3, a3 ; RV32I-NEXT: srl a4, t2, a2 -; RV32I-NEXT: addi s0, a2, -96 +; RV32I-NEXT: addi t6, a2, -96 ; RV32I-NEXT: bltu a2, t0, .LBB6_5 ; RV32I-NEXT: # %bb.4: -; RV32I-NEXT: slti t1, s0, 0 -; RV32I-NEXT: neg t1, t1 -; RV32I-NEXT: and t6, t1, a4 +; RV32I-NEXT: slti t1, t6, 0 +; RV32I-NEXT: neg s0, t1 +; RV32I-NEXT: and s0, s0, a4 ; RV32I-NEXT: mv t1, t5 ; RV32I-NEXT: bnez a2, .LBB6_6 ; RV32I-NEXT: j .LBB6_7 ; RV32I-NEXT: .LBB6_5: -; RV32I-NEXT: and t6, a3, t4 -; RV32I-NEXT: or t6, t6, t1 +; RV32I-NEXT: and s0, a3, t4 +; RV32I-NEXT: or s0, s0, t1 ; RV32I-NEXT: mv t1, t5 ; RV32I-NEXT: beqz a2, .LBB6_7 ; RV32I-NEXT: .LBB6_6: -; RV32I-NEXT: mv t1, t6 +; RV32I-NEXT: mv t1, s0 ; RV32I-NEXT: .LBB6_7: ; RV32I-NEXT: lw a1, 0(a1) -; RV32I-NEXT: xori t6, a2, 31 -; RV32I-NEXT: bgez a7, .LBB6_9 +; RV32I-NEXT: not s0, a2 +; RV32I-NEXT: bgez a6, .LBB6_9 ; RV32I-NEXT: # %bb.8: ; RV32I-NEXT: srl t4, a1, a2 ; RV32I-NEXT: slli t5, t5, 1 -; RV32I-NEXT: sll t5, t5, t6 +; RV32I-NEXT: sll t5, t5, s0 ; RV32I-NEXT: or t4, t4, t5 ; RV32I-NEXT: .LBB6_9: ; RV32I-NEXT: srl t3, t3, a2 ; RV32I-NEXT: slli t2, t2, 1 -; RV32I-NEXT: bltz s0, .LBB6_11 +; RV32I-NEXT: sll t2, t2, s0 +; RV32I-NEXT: or t2, t3, t2 +; RV32I-NEXT: mv t3, t2 +; RV32I-NEXT: bgez t6, .LBB6_15 ; RV32I-NEXT: # %bb.10: -; RV32I-NEXT: mv t5, a4 -; RV32I-NEXT: bltu a2, t0, .LBB6_12 -; RV32I-NEXT: j .LBB6_13 +; RV32I-NEXT: bltu a2, t0, .LBB6_16 ; RV32I-NEXT: .LBB6_11: -; RV32I-NEXT: addi t5, a2, -64 -; RV32I-NEXT: xori t5, t5, 31 -; RV32I-NEXT: sll t5, t2, t5 -; RV32I-NEXT: or t5, t3, t5 -; RV32I-NEXT: bgeu a2, t0, .LBB6_13 +; RV32I-NEXT: bnez a2, .LBB6_17 ; RV32I-NEXT: .LBB6_12: -; RV32I-NEXT: slti a6, a6, 0 -; RV32I-NEXT: neg a6, a6 -; RV32I-NEXT: and a5, a6, a5 -; RV32I-NEXT: or t5, t4, a5 +; RV32I-NEXT: bltz a6, .LBB6_14 ; RV32I-NEXT: .LBB6_13: -; RV32I-NEXT: bnez a2, .LBB6_16 -; RV32I-NEXT: # %bb.14: -; RV32I-NEXT: bltz a7, .LBB6_17 -; RV32I-NEXT: .LBB6_15: -; RV32I-NEXT: mv a5, a4 -; RV32I-NEXT: j .LBB6_18 -; RV32I-NEXT: .LBB6_16: -; RV32I-NEXT: mv a1, t5 -; RV32I-NEXT: bgez a7, .LBB6_15 -; RV32I-NEXT: .LBB6_17: -; RV32I-NEXT: sll a5, t2, t6 -; RV32I-NEXT: or a5, t3, a5 -; RV32I-NEXT: .LBB6_18: +; RV32I-NEXT: mv t2, a4 +; RV32I-NEXT: .LBB6_14: ; RV32I-NEXT: sltiu a2, a2, 64 ; RV32I-NEXT: neg a2, a2 -; RV32I-NEXT: and a5, a2, a5 +; RV32I-NEXT: and a5, a2, t2 ; RV32I-NEXT: and a3, a3, a4 ; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: sw a2, 12(a0) @@ -251,6 +234,19 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind { ; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB6_15: +; RV32I-NEXT: mv t3, a4 +; RV32I-NEXT: bgeu a2, t0, .LBB6_11 +; RV32I-NEXT: .LBB6_16: +; RV32I-NEXT: slti a7, a7, 0 +; RV32I-NEXT: neg a7, a7 +; RV32I-NEXT: and a5, a7, a5 +; RV32I-NEXT: or t3, t4, a5 +; RV32I-NEXT: beqz a2, .LBB6_12 +; RV32I-NEXT: .LBB6_17: +; RV32I-NEXT: mv a1, t3 +; RV32I-NEXT: bgez a6, .LBB6_13 +; RV32I-NEXT: j .LBB6_14 ; ; RV64I-LABEL: lshr128: ; RV64I: # %bb.0: @@ -262,7 +258,7 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind { ; RV64I-NEXT: j .LBB6_3 ; RV64I-NEXT: .LBB6_2: ; RV64I-NEXT: srl a0, a0, a2 -; RV64I-NEXT: xori a2, a2, 63 +; RV64I-NEXT: not a2, a2 ; RV64I-NEXT: slli a1, a1, 1 ; RV64I-NEXT: sll a1, a1, a2 ; RV64I-NEXT: or a0, a0, a1 @@ -295,96 +291,93 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind { ; RV32I-NEXT: .LBB7_2: ; RV32I-NEXT: sll a4, t2, a4 ; RV32I-NEXT: sub a5, a3, a2 -; RV32I-NEXT: xori a5, a5, 31 +; RV32I-NEXT: not a5, a5 ; RV32I-NEXT: srli a6, t3, 1 ; RV32I-NEXT: srl a5, a6, a5 ; RV32I-NEXT: or a7, a4, a5 ; RV32I-NEXT: .LBB7_3: -; RV32I-NEXT: lw s0, 4(a1) +; RV32I-NEXT: lw t6, 4(a1) ; RV32I-NEXT: sra a4, t2, a2 -; RV32I-NEXT: addi t6, a2, -96 +; RV32I-NEXT: addi t4, a2, -96 ; RV32I-NEXT: srai a5, t2, 31 -; RV32I-NEXT: mv t5, a4 -; RV32I-NEXT: bltz t6, .LBB7_5 +; RV32I-NEXT: mv s0, a4 +; RV32I-NEXT: bltz t4, .LBB7_5 ; RV32I-NEXT: # %bb.4: -; RV32I-NEXT: mv t5, a5 +; RV32I-NEXT: mv s0, a5 ; RV32I-NEXT: .LBB7_5: ; RV32I-NEXT: addi a6, a2, -32 -; RV32I-NEXT: srl t4, s0, a2 +; RV32I-NEXT: srl t5, t6, a2 ; RV32I-NEXT: bgeu a2, a3, .LBB7_7 ; RV32I-NEXT: # %bb.6: -; RV32I-NEXT: slti t5, a6, 0 -; RV32I-NEXT: neg t5, t5 -; RV32I-NEXT: and t5, t5, t4 -; RV32I-NEXT: or t5, t5, a7 +; RV32I-NEXT: slti s0, a6, 0 +; RV32I-NEXT: neg s0, s0 +; RV32I-NEXT: and s0, s0, t5 +; RV32I-NEXT: or s0, s0, a7 ; RV32I-NEXT: .LBB7_7: -; RV32I-NEXT: mv a7, s0 +; RV32I-NEXT: mv a7, t6 ; RV32I-NEXT: beqz a2, .LBB7_9 ; RV32I-NEXT: # %bb.8: -; RV32I-NEXT: mv a7, t5 +; RV32I-NEXT: mv a7, s0 ; RV32I-NEXT: .LBB7_9: ; RV32I-NEXT: lw a1, 0(a1) -; RV32I-NEXT: xori t5, a2, 31 +; RV32I-NEXT: not s0, a2 ; RV32I-NEXT: bgez a6, .LBB7_11 ; RV32I-NEXT: # %bb.10: -; RV32I-NEXT: srl t4, a1, a2 -; RV32I-NEXT: slli s0, s0, 1 -; RV32I-NEXT: sll s0, s0, t5 -; RV32I-NEXT: or t4, t4, s0 +; RV32I-NEXT: srl t5, a1, a2 +; RV32I-NEXT: slli t6, t6, 1 +; RV32I-NEXT: sll t6, t6, s0 +; RV32I-NEXT: or t5, t5, t6 ; RV32I-NEXT: .LBB7_11: ; RV32I-NEXT: srl t3, t3, a2 ; RV32I-NEXT: slli t2, t2, 1 -; RV32I-NEXT: bltz t6, .LBB7_13 +; RV32I-NEXT: sll t2, t2, s0 +; RV32I-NEXT: or t2, t3, t2 +; RV32I-NEXT: mv t3, t2 +; RV32I-NEXT: bgez t4, .LBB7_20 ; RV32I-NEXT: # %bb.12: -; RV32I-NEXT: mv t6, a4 -; RV32I-NEXT: bltu a2, a3, .LBB7_14 -; RV32I-NEXT: j .LBB7_15 +; RV32I-NEXT: bltu a2, a3, .LBB7_21 ; RV32I-NEXT: .LBB7_13: -; RV32I-NEXT: addi t6, a2, -64 -; RV32I-NEXT: xori t6, t6, 31 -; RV32I-NEXT: sll t6, t2, t6 -; RV32I-NEXT: or t6, t3, t6 -; RV32I-NEXT: bgeu a2, a3, .LBB7_15 +; RV32I-NEXT: bnez a2, .LBB7_22 ; RV32I-NEXT: .LBB7_14: -; RV32I-NEXT: slti t1, t1, 0 -; RV32I-NEXT: neg t1, t1 -; RV32I-NEXT: and t0, t1, t0 -; RV32I-NEXT: or t6, t4, t0 +; RV32I-NEXT: bgez a6, .LBB7_23 ; RV32I-NEXT: .LBB7_15: -; RV32I-NEXT: bnez a2, .LBB7_18 -; RV32I-NEXT: # %bb.16: -; RV32I-NEXT: bltz a6, .LBB7_19 +; RV32I-NEXT: bgeu a2, a3, .LBB7_24 +; RV32I-NEXT: .LBB7_16: +; RV32I-NEXT: bgez a6, .LBB7_25 ; RV32I-NEXT: .LBB7_17: -; RV32I-NEXT: mv t0, a4 -; RV32I-NEXT: bgeu a2, a3, .LBB7_20 -; RV32I-NEXT: j .LBB7_21 +; RV32I-NEXT: bltu a2, a3, .LBB7_19 ; RV32I-NEXT: .LBB7_18: -; RV32I-NEXT: mv a1, t6 -; RV32I-NEXT: bgez a6, .LBB7_17 -; RV32I-NEXT: .LBB7_19: -; RV32I-NEXT: sll t0, t2, t5 -; RV32I-NEXT: or t0, t3, t0 -; RV32I-NEXT: bltu a2, a3, .LBB7_21 -; RV32I-NEXT: .LBB7_20: -; RV32I-NEXT: mv t0, a5 -; RV32I-NEXT: .LBB7_21: -; RV32I-NEXT: bgez a6, .LBB7_25 -; RV32I-NEXT: # %bb.22: -; RV32I-NEXT: bltu a2, a3, .LBB7_24 -; RV32I-NEXT: .LBB7_23: ; RV32I-NEXT: mv a4, a5 -; RV32I-NEXT: .LBB7_24: +; RV32I-NEXT: .LBB7_19: ; RV32I-NEXT: sw a4, 12(a0) -; RV32I-NEXT: sw t0, 8(a0) +; RV32I-NEXT: sw t2, 8(a0) ; RV32I-NEXT: sw a1, 0(a0) ; RV32I-NEXT: sw a7, 4(a0) ; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB7_20: +; RV32I-NEXT: mv t3, a4 +; RV32I-NEXT: bgeu a2, a3, .LBB7_13 +; RV32I-NEXT: .LBB7_21: +; RV32I-NEXT: slti t1, t1, 0 +; RV32I-NEXT: neg t1, t1 +; RV32I-NEXT: and t0, t1, t0 +; RV32I-NEXT: or t3, t5, t0 +; RV32I-NEXT: beqz a2, .LBB7_14 +; RV32I-NEXT: .LBB7_22: +; RV32I-NEXT: mv a1, t3 +; RV32I-NEXT: bltz a6, .LBB7_15 +; RV32I-NEXT: .LBB7_23: +; RV32I-NEXT: mv t2, a4 +; RV32I-NEXT: bltu a2, a3, .LBB7_16 +; RV32I-NEXT: .LBB7_24: +; RV32I-NEXT: mv t2, a5 +; RV32I-NEXT: bltz a6, .LBB7_17 ; RV32I-NEXT: .LBB7_25: ; RV32I-NEXT: mv a4, a5 -; RV32I-NEXT: bgeu a2, a3, .LBB7_23 -; RV32I-NEXT: j .LBB7_24 +; RV32I-NEXT: bgeu a2, a3, .LBB7_18 +; RV32I-NEXT: j .LBB7_19 ; ; RV64I-LABEL: ashr128: ; RV64I: # %bb.0: @@ -399,7 +392,7 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind { ; RV64I-NEXT: ret ; RV64I-NEXT: .LBB7_2: ; RV64I-NEXT: srl a0, a0, a2 -; RV64I-NEXT: xori a2, a2, 63 +; RV64I-NEXT: not a2, a2 ; RV64I-NEXT: slli a3, a3, 1 ; RV64I-NEXT: sll a2, a3, a2 ; RV64I-NEXT: or a0, a0, a2 @@ -414,7 +407,7 @@ define i128 @shl128(i128 %a, i128 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a2, 0(a2) -; RV32I-NEXT: lw t6, 8(a1) +; RV32I-NEXT: lw t5, 8(a1) ; RV32I-NEXT: lw t3, 4(a1) ; RV32I-NEXT: lw t2, 0(a1) ; RV32I-NEXT: neg a3, a2 @@ -424,87 +417,86 @@ define i128 @shl128(i128 %a, i128 %b) nounwind { ; RV32I-NEXT: srl a5, t3, a3 ; RV32I-NEXT: bltz a6, .LBB8_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: mv t0, a5 +; RV32I-NEXT: mv t1, a5 ; RV32I-NEXT: j .LBB8_3 ; RV32I-NEXT: .LBB8_2: ; RV32I-NEXT: srl a3, t2, a3 ; RV32I-NEXT: sub a4, a7, a2 -; RV32I-NEXT: xori a4, a4, 31 +; RV32I-NEXT: not a4, a4 ; RV32I-NEXT: slli t0, t3, 1 ; RV32I-NEXT: sll a4, t0, a4 -; RV32I-NEXT: or t0, a3, a4 +; RV32I-NEXT: or t1, a3, a4 ; RV32I-NEXT: .LBB8_3: -; RV32I-NEXT: sll t4, t6, a2 -; RV32I-NEXT: addi a4, a2, -32 -; RV32I-NEXT: slti a3, a4, 0 -; RV32I-NEXT: neg t1, a3 -; RV32I-NEXT: sll a3, t2, a2 -; RV32I-NEXT: addi s0, a2, -96 +; RV32I-NEXT: sll t4, t5, a2 +; RV32I-NEXT: addi a3, a2, -32 +; RV32I-NEXT: slti a4, a3, 0 +; RV32I-NEXT: neg t0, a4 +; RV32I-NEXT: sll a4, t2, a2 +; RV32I-NEXT: addi t6, a2, -96 ; RV32I-NEXT: bltu a2, a7, .LBB8_5 ; RV32I-NEXT: # %bb.4: -; RV32I-NEXT: slti t0, s0, 0 -; RV32I-NEXT: neg t0, t0 -; RV32I-NEXT: and t5, t0, a3 -; RV32I-NEXT: mv t0, t6 +; RV32I-NEXT: slti t1, t6, 0 +; RV32I-NEXT: neg s0, t1 +; RV32I-NEXT: and s0, s0, a4 +; RV32I-NEXT: mv t1, t5 ; RV32I-NEXT: bnez a2, .LBB8_6 ; RV32I-NEXT: j .LBB8_7 ; RV32I-NEXT: .LBB8_5: -; RV32I-NEXT: and t5, t1, t4 -; RV32I-NEXT: or t5, t5, t0 -; RV32I-NEXT: mv t0, t6 +; RV32I-NEXT: and s0, t0, t4 +; RV32I-NEXT: or s0, s0, t1 +; RV32I-NEXT: mv t1, t5 ; RV32I-NEXT: beqz a2, .LBB8_7 ; RV32I-NEXT: .LBB8_6: -; RV32I-NEXT: mv t0, t5 +; RV32I-NEXT: mv t1, s0 ; RV32I-NEXT: .LBB8_7: ; RV32I-NEXT: lw a1, 12(a1) -; RV32I-NEXT: xori t5, a2, 31 -; RV32I-NEXT: bgez a4, .LBB8_9 +; RV32I-NEXT: not s0, a2 +; RV32I-NEXT: bgez a3, .LBB8_9 ; RV32I-NEXT: # %bb.8: ; RV32I-NEXT: sll t4, a1, a2 -; RV32I-NEXT: srli t6, t6, 1 -; RV32I-NEXT: srl t6, t6, t5 -; RV32I-NEXT: or t4, t4, t6 +; RV32I-NEXT: srli t5, t5, 1 +; RV32I-NEXT: srl t5, t5, s0 +; RV32I-NEXT: or t4, t4, t5 ; RV32I-NEXT: .LBB8_9: ; RV32I-NEXT: sll t3, t3, a2 ; RV32I-NEXT: srli t2, t2, 1 -; RV32I-NEXT: bltz s0, .LBB8_11 +; RV32I-NEXT: srl t2, t2, s0 +; RV32I-NEXT: or t2, t3, t2 +; RV32I-NEXT: mv t3, t2 +; RV32I-NEXT: bgez t6, .LBB8_16 ; RV32I-NEXT: # %bb.10: -; RV32I-NEXT: mv t6, a3 -; RV32I-NEXT: bltu a2, a7, .LBB8_12 -; RV32I-NEXT: j .LBB8_13 +; RV32I-NEXT: bltu a2, a7, .LBB8_17 ; RV32I-NEXT: .LBB8_11: -; RV32I-NEXT: addi t6, a2, -64 -; RV32I-NEXT: xori t6, t6, 31 -; RV32I-NEXT: srl t6, t2, t6 -; RV32I-NEXT: or t6, t3, t6 -; RV32I-NEXT: bgeu a2, a7, .LBB8_13 +; RV32I-NEXT: beqz a2, .LBB8_13 ; RV32I-NEXT: .LBB8_12: -; RV32I-NEXT: slti a6, a6, 0 -; RV32I-NEXT: neg a6, a6 -; RV32I-NEXT: and a5, a6, a5 -; RV32I-NEXT: or t6, t4, a5 +; RV32I-NEXT: mv a1, t3 ; RV32I-NEXT: .LBB8_13: -; RV32I-NEXT: beqz a2, .LBB8_15 -; RV32I-NEXT: # %bb.14: -; RV32I-NEXT: mv a1, t6 -; RV32I-NEXT: .LBB8_15: -; RV32I-NEXT: and a6, t1, a3 +; RV32I-NEXT: and a6, t0, a4 ; RV32I-NEXT: sltiu a2, a2, 64 ; RV32I-NEXT: neg a5, a2 ; RV32I-NEXT: and a2, a5, a6 -; RV32I-NEXT: bgez a4, .LBB8_17 -; RV32I-NEXT: # %bb.16: -; RV32I-NEXT: srl a3, t2, t5 -; RV32I-NEXT: or a3, t3, a3 -; RV32I-NEXT: .LBB8_17: -; RV32I-NEXT: and a3, a5, a3 +; RV32I-NEXT: bltz a3, .LBB8_15 +; RV32I-NEXT: # %bb.14: +; RV32I-NEXT: mv t2, a4 +; RV32I-NEXT: .LBB8_15: +; RV32I-NEXT: and a3, a5, t2 ; RV32I-NEXT: sw a3, 4(a0) ; RV32I-NEXT: sw a2, 0(a0) ; RV32I-NEXT: sw a1, 12(a0) -; RV32I-NEXT: sw t0, 8(a0) +; RV32I-NEXT: sw t1, 8(a0) ; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB8_16: +; RV32I-NEXT: mv t3, a4 +; RV32I-NEXT: bgeu a2, a7, .LBB8_11 +; RV32I-NEXT: .LBB8_17: +; RV32I-NEXT: slti a6, a6, 0 +; RV32I-NEXT: neg a6, a6 +; RV32I-NEXT: and a5, a6, a5 +; RV32I-NEXT: or t3, t4, a5 +; RV32I-NEXT: bnez a2, .LBB8_12 +; RV32I-NEXT: j .LBB8_13 ; ; RV64I-LABEL: shl128: ; RV64I: # %bb.0: @@ -516,7 +508,7 @@ define i128 @shl128(i128 %a, i128 %b) nounwind { ; RV64I-NEXT: j .LBB8_3 ; RV64I-NEXT: .LBB8_2: ; RV64I-NEXT: sll a1, a1, a2 -; RV64I-NEXT: xori a2, a2, 63 +; RV64I-NEXT: not a2, a2 ; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srl a0, a0, a2 ; RV64I-NEXT: or a1, a1, a0 diff --git a/llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll b/llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll index 7ef84779923a44..bef25876b4fe58 100644 --- a/llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll +++ b/llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll @@ -303,7 +303,7 @@ define void @lshr_8bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: or a0, a0, a6 ; RV32I-NEXT: srl a0, a0, a5 ; RV32I-NEXT: slli a3, a3, 1 -; RV32I-NEXT: xori a5, a5, 31 +; RV32I-NEXT: not a5, a5 ; RV32I-NEXT: sll a3, a3, a5 ; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: .LBB3_3: @@ -440,7 +440,7 @@ define void @shl_8bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: or a0, a0, a6 ; RV32I-NEXT: sll a0, a0, a5 ; RV32I-NEXT: srli a3, a3, 1 -; RV32I-NEXT: xori a5, a5, 31 +; RV32I-NEXT: not a5, a5 ; RV32I-NEXT: srl a3, a3, a5 ; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: .LBB4_3: @@ -579,7 +579,7 @@ define void @ashr_8bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: or a0, a0, a5 ; RV32I-NEXT: srl a0, a0, a4 ; RV32I-NEXT: slli a3, a3, 1 -; RV32I-NEXT: xori a4, a4, 31 +; RV32I-NEXT: not a4, a4 ; RV32I-NEXT: sll a3, a3, a4 ; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: .LBB5_3: @@ -684,7 +684,7 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: or a0, a0, a6 ; RV64I-NEXT: or a0, a0, t1 ; RV64I-NEXT: srl a0, a0, a5 -; RV64I-NEXT: xori a5, a5, 63 +; RV64I-NEXT: not a5, a5 ; RV64I-NEXT: slli a3, a3, 1 ; RV64I-NEXT: sll a3, a3, a5 ; RV64I-NEXT: or a0, a0, a3 @@ -729,8 +729,6 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: lbu a3, 5(a0) ; RV32I-NEXT: lbu a4, 4(a0) ; RV32I-NEXT: lbu a5, 6(a0) @@ -744,32 +742,32 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: lbu a4, 1(a0) ; RV32I-NEXT: lbu a5, 0(a0) ; RV32I-NEXT: lbu a6, 2(a0) -; RV32I-NEXT: lbu a7, 3(a0) +; RV32I-NEXT: lbu t0, 3(a0) ; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or t0, a4, a5 +; RV32I-NEXT: or a7, a4, a5 ; RV32I-NEXT: slli a6, a6, 16 -; RV32I-NEXT: slli a7, a7, 24 -; RV32I-NEXT: or t1, a7, a6 +; RV32I-NEXT: slli t0, t0, 24 +; RV32I-NEXT: or t2, t0, a6 ; RV32I-NEXT: lbu a4, 13(a0) ; RV32I-NEXT: lbu a5, 12(a0) ; RV32I-NEXT: lbu a6, 14(a0) -; RV32I-NEXT: lbu a7, 15(a0) +; RV32I-NEXT: lbu t0, 15(a0) ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: or a4, a4, a5 ; RV32I-NEXT: slli a6, a6, 16 -; RV32I-NEXT: slli a7, a7, 24 +; RV32I-NEXT: slli t0, t0, 24 ; RV32I-NEXT: or a4, a6, a4 -; RV32I-NEXT: or a7, a7, a4 +; RV32I-NEXT: or a6, t0, a4 ; RV32I-NEXT: lbu a4, 9(a0) ; RV32I-NEXT: lbu a5, 8(a0) -; RV32I-NEXT: lbu a6, 10(a0) +; RV32I-NEXT: lbu t0, 10(a0) ; RV32I-NEXT: lbu a0, 11(a0) ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: or a4, a4, a5 -; RV32I-NEXT: slli a6, a6, 16 +; RV32I-NEXT: slli t0, t0, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a4, a6, a4 -; RV32I-NEXT: or t2, a0, a4 +; RV32I-NEXT: or a4, t0, a4 +; RV32I-NEXT: or t0, a0, a4 ; RV32I-NEXT: lbu a0, 1(a1) ; RV32I-NEXT: lbu a4, 0(a1) ; RV32I-NEXT: lbu a5, 2(a1) @@ -781,99 +779,92 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: slli a1, a0, 3 -; RV32I-NEXT: srl a5, t2, a1 -; RV32I-NEXT: slli a6, a7, 1 -; RV32I-NEXT: addi t3, a1, -96 -; RV32I-NEXT: srl a4, a7, a1 -; RV32I-NEXT: bltz t3, .LBB6_2 +; RV32I-NEXT: srl a0, t0, a1 +; RV32I-NEXT: slli a4, a6, 1 +; RV32I-NEXT: not t4, a1 +; RV32I-NEXT: sll a4, a4, t4 +; RV32I-NEXT: or a4, a0, a4 +; RV32I-NEXT: addi t1, a1, -96 +; RV32I-NEXT: srl a5, a6, a1 +; RV32I-NEXT: mv t3, a4 +; RV32I-NEXT: bltz t1, .LBB6_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: mv t5, a4 -; RV32I-NEXT: j .LBB6_3 +; RV32I-NEXT: mv t3, a5 ; RV32I-NEXT: .LBB6_2: -; RV32I-NEXT: addi a0, a1, -64 -; RV32I-NEXT: xori a0, a0, 31 -; RV32I-NEXT: sll a0, a6, a0 -; RV32I-NEXT: or t5, a5, a0 -; RV32I-NEXT: .LBB6_3: -; RV32I-NEXT: or a0, t1, t0 -; RV32I-NEXT: xori t0, a1, 31 -; RV32I-NEXT: addi t1, a1, -32 -; RV32I-NEXT: srl t4, a3, a1 -; RV32I-NEXT: bltz t1, .LBB6_5 -; RV32I-NEXT: # %bb.4: -; RV32I-NEXT: mv s3, t4 -; RV32I-NEXT: j .LBB6_6 +; RV32I-NEXT: or a0, t2, a7 +; RV32I-NEXT: addi a7, a1, -32 +; RV32I-NEXT: srl t2, a3, a1 +; RV32I-NEXT: bltz a7, .LBB6_4 +; RV32I-NEXT: # %bb.3: +; RV32I-NEXT: mv s1, t2 +; RV32I-NEXT: j .LBB6_5 +; RV32I-NEXT: .LBB6_4: +; RV32I-NEXT: srl t5, a0, a1 +; RV32I-NEXT: slli t6, a3, 1 +; RV32I-NEXT: sll t4, t6, t4 +; RV32I-NEXT: or s1, t5, t4 ; RV32I-NEXT: .LBB6_5: -; RV32I-NEXT: srl t6, a0, a1 -; RV32I-NEXT: slli s0, a3, 1 -; RV32I-NEXT: sll s0, s0, t0 -; RV32I-NEXT: or s3, t6, s0 -; RV32I-NEXT: .LBB6_6: -; RV32I-NEXT: neg s1, a1 -; RV32I-NEXT: sll t6, t2, s1 -; RV32I-NEXT: li s2, 32 -; RV32I-NEXT: li s0, 64 -; RV32I-NEXT: sub s2, s2, a1 -; RV32I-NEXT: bltu a1, s0, .LBB6_12 -; RV32I-NEXT: # %bb.7: -; RV32I-NEXT: bnez a1, .LBB6_13 +; RV32I-NEXT: neg t6, a1 +; RV32I-NEXT: sll t4, t0, t6 +; RV32I-NEXT: li s0, 32 +; RV32I-NEXT: li t5, 64 +; RV32I-NEXT: sub s0, s0, a1 +; RV32I-NEXT: bltu a1, t5, .LBB6_11 +; RV32I-NEXT: # %bb.6: +; RV32I-NEXT: bnez a1, .LBB6_12 +; RV32I-NEXT: .LBB6_7: +; RV32I-NEXT: bgez s0, .LBB6_9 ; RV32I-NEXT: .LBB6_8: -; RV32I-NEXT: bgez s2, .LBB6_10 +; RV32I-NEXT: sll a6, a6, t6 +; RV32I-NEXT: srli t0, t0, 1 +; RV32I-NEXT: sub t3, t5, a1 +; RV32I-NEXT: not t3, t3 +; RV32I-NEXT: srl t0, t0, t3 +; RV32I-NEXT: or t4, a6, t0 ; RV32I-NEXT: .LBB6_9: -; RV32I-NEXT: sll a7, a7, s1 -; RV32I-NEXT: srli t2, t2, 1 -; RV32I-NEXT: sub t5, s0, a1 -; RV32I-NEXT: xori t5, t5, 31 -; RV32I-NEXT: srl t2, t2, t5 -; RV32I-NEXT: or t6, a7, t2 -; RV32I-NEXT: .LBB6_10: -; RV32I-NEXT: slti a7, t1, 0 -; RV32I-NEXT: neg a7, a7 -; RV32I-NEXT: bltu a1, s0, .LBB6_14 -; RV32I-NEXT: # %bb.11: -; RV32I-NEXT: slti t2, t3, 0 -; RV32I-NEXT: neg t2, t2 -; RV32I-NEXT: and t2, t2, a4 -; RV32I-NEXT: bnez a1, .LBB6_15 -; RV32I-NEXT: j .LBB6_16 +; RV32I-NEXT: slti a6, a7, 0 +; RV32I-NEXT: neg a6, a6 +; RV32I-NEXT: bltu a1, t5, .LBB6_13 +; RV32I-NEXT: # %bb.10: +; RV32I-NEXT: slti t0, t1, 0 +; RV32I-NEXT: neg t0, t0 +; RV32I-NEXT: and t0, t0, a5 +; RV32I-NEXT: bnez a1, .LBB6_14 +; RV32I-NEXT: j .LBB6_15 +; RV32I-NEXT: .LBB6_11: +; RV32I-NEXT: slti t3, s0, 0 +; RV32I-NEXT: neg t3, t3 +; RV32I-NEXT: and t3, t3, t4 +; RV32I-NEXT: or t3, s1, t3 +; RV32I-NEXT: beqz a1, .LBB6_7 ; RV32I-NEXT: .LBB6_12: -; RV32I-NEXT: slti t5, s2, 0 -; RV32I-NEXT: neg t5, t5 -; RV32I-NEXT: and t5, t5, t6 -; RV32I-NEXT: or t5, s3, t5 -; RV32I-NEXT: beqz a1, .LBB6_8 +; RV32I-NEXT: mv a0, t3 +; RV32I-NEXT: bltz s0, .LBB6_8 +; RV32I-NEXT: j .LBB6_9 ; RV32I-NEXT: .LBB6_13: -; RV32I-NEXT: mv a0, t5 -; RV32I-NEXT: bltz s2, .LBB6_9 -; RV32I-NEXT: j .LBB6_10 +; RV32I-NEXT: and t0, a6, t2 +; RV32I-NEXT: or t0, t0, t4 +; RV32I-NEXT: beqz a1, .LBB6_15 ; RV32I-NEXT: .LBB6_14: -; RV32I-NEXT: and t2, a7, t4 -; RV32I-NEXT: or t2, t2, t6 -; RV32I-NEXT: beqz a1, .LBB6_16 +; RV32I-NEXT: mv a3, t0 ; RV32I-NEXT: .LBB6_15: -; RV32I-NEXT: mv a3, t2 -; RV32I-NEXT: .LBB6_16: -; RV32I-NEXT: bltz t1, .LBB6_18 -; RV32I-NEXT: # %bb.17: -; RV32I-NEXT: mv a5, a4 -; RV32I-NEXT: j .LBB6_19 -; RV32I-NEXT: .LBB6_18: -; RV32I-NEXT: sll a6, a6, t0 -; RV32I-NEXT: or a5, a5, a6 -; RV32I-NEXT: .LBB6_19: +; RV32I-NEXT: bltz a7, .LBB6_17 +; RV32I-NEXT: # %bb.16: +; RV32I-NEXT: mv a4, a5 +; RV32I-NEXT: .LBB6_17: ; RV32I-NEXT: sltiu a1, a1, 64 ; RV32I-NEXT: neg a1, a1 -; RV32I-NEXT: and a5, a1, a5 -; RV32I-NEXT: and a4, a7, a4 -; RV32I-NEXT: and a1, a1, a4 -; RV32I-NEXT: sb a5, 8(a2) +; RV32I-NEXT: and a4, a1, a4 +; RV32I-NEXT: and a5, a6, a5 +; RV32I-NEXT: and a1, a1, a5 +; RV32I-NEXT: sb a4, 8(a2) ; RV32I-NEXT: sb a1, 12(a2) -; RV32I-NEXT: srli a4, a5, 16 -; RV32I-NEXT: sb a4, 10(a2) -; RV32I-NEXT: srli a4, a5, 24 -; RV32I-NEXT: sb a4, 11(a2) -; RV32I-NEXT: srli a5, a5, 8 -; RV32I-NEXT: sb a5, 9(a2) +; RV32I-NEXT: srli a5, a4, 16 +; RV32I-NEXT: sb a5, 10(a2) +; RV32I-NEXT: srli a5, a4, 24 +; RV32I-NEXT: sb a5, 11(a2) +; RV32I-NEXT: srli a4, a4, 8 +; RV32I-NEXT: sb a4, 9(a2) ; RV32I-NEXT: srli a4, a1, 16 ; RV32I-NEXT: sb a4, 14(a2) ; RV32I-NEXT: srli a4, a1, 24 @@ -896,8 +887,6 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sb a3, 5(a2) ; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s3, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret %src = load i128, ptr %src.ptr, align 1 @@ -985,7 +974,7 @@ define void @shl_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: or a0, a0, a6 ; RV64I-NEXT: or a0, a0, t1 ; RV64I-NEXT: sll a0, a0, a5 -; RV64I-NEXT: xori a5, a5, 63 +; RV64I-NEXT: not a5, a5 ; RV64I-NEXT: srli a3, a3, 1 ; RV64I-NEXT: srl a3, a3, a5 ; RV64I-NEXT: or a0, a0, a3 @@ -1030,8 +1019,6 @@ define void @shl_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: lbu a3, 9(a0) ; RV32I-NEXT: lbu a4, 8(a0) ; RV32I-NEXT: lbu a5, 10(a0) @@ -1045,32 +1032,32 @@ define void @shl_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: lbu a4, 13(a0) ; RV32I-NEXT: lbu a5, 12(a0) ; RV32I-NEXT: lbu a6, 14(a0) -; RV32I-NEXT: lbu a7, 15(a0) +; RV32I-NEXT: lbu t0, 15(a0) ; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or t0, a4, a5 +; RV32I-NEXT: or a7, a4, a5 ; RV32I-NEXT: slli a6, a6, 16 -; RV32I-NEXT: slli a7, a7, 24 -; RV32I-NEXT: or t1, a7, a6 +; RV32I-NEXT: slli t0, t0, 24 +; RV32I-NEXT: or t2, t0, a6 ; RV32I-NEXT: lbu a4, 1(a0) ; RV32I-NEXT: lbu a5, 0(a0) ; RV32I-NEXT: lbu a6, 2(a0) -; RV32I-NEXT: lbu a7, 3(a0) +; RV32I-NEXT: lbu t0, 3(a0) ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: or a4, a4, a5 ; RV32I-NEXT: slli a6, a6, 16 -; RV32I-NEXT: slli a7, a7, 24 +; RV32I-NEXT: slli t0, t0, 24 ; RV32I-NEXT: or a4, a6, a4 -; RV32I-NEXT: or a7, a7, a4 +; RV32I-NEXT: or a6, t0, a4 ; RV32I-NEXT: lbu a4, 5(a0) ; RV32I-NEXT: lbu a5, 4(a0) -; RV32I-NEXT: lbu a6, 6(a0) +; RV32I-NEXT: lbu t0, 6(a0) ; RV32I-NEXT: lbu a0, 7(a0) ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: or a4, a4, a5 -; RV32I-NEXT: slli a6, a6, 16 +; RV32I-NEXT: slli t0, t0, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a4, a6, a4 -; RV32I-NEXT: or t2, a0, a4 +; RV32I-NEXT: or a4, t0, a4 +; RV32I-NEXT: or t0, a0, a4 ; RV32I-NEXT: lbu a0, 1(a1) ; RV32I-NEXT: lbu a4, 0(a1) ; RV32I-NEXT: lbu a5, 2(a1) @@ -1082,105 +1069,98 @@ define void @shl_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: slli a1, a0, 3 -; RV32I-NEXT: sll a5, t2, a1 -; RV32I-NEXT: srli a6, a7, 1 -; RV32I-NEXT: addi t3, a1, -96 -; RV32I-NEXT: sll a4, a7, a1 -; RV32I-NEXT: bltz t3, .LBB7_2 +; RV32I-NEXT: sll a0, t0, a1 +; RV32I-NEXT: srli a4, a6, 1 +; RV32I-NEXT: not t4, a1 +; RV32I-NEXT: srl a4, a4, t4 +; RV32I-NEXT: or a4, a0, a4 +; RV32I-NEXT: addi t1, a1, -96 +; RV32I-NEXT: sll a5, a6, a1 +; RV32I-NEXT: mv t3, a4 +; RV32I-NEXT: bltz t1, .LBB7_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: mv t5, a4 -; RV32I-NEXT: j .LBB7_3 +; RV32I-NEXT: mv t3, a5 ; RV32I-NEXT: .LBB7_2: -; RV32I-NEXT: addi a0, a1, -64 -; RV32I-NEXT: xori a0, a0, 31 -; RV32I-NEXT: srl a0, a6, a0 -; RV32I-NEXT: or t5, a5, a0 -; RV32I-NEXT: .LBB7_3: -; RV32I-NEXT: or a0, t1, t0 -; RV32I-NEXT: xori t0, a1, 31 -; RV32I-NEXT: addi t1, a1, -32 -; RV32I-NEXT: sll t4, a3, a1 -; RV32I-NEXT: bltz t1, .LBB7_5 -; RV32I-NEXT: # %bb.4: -; RV32I-NEXT: mv s3, t4 -; RV32I-NEXT: j .LBB7_6 +; RV32I-NEXT: or a0, t2, a7 +; RV32I-NEXT: addi a7, a1, -32 +; RV32I-NEXT: sll t2, a3, a1 +; RV32I-NEXT: bltz a7, .LBB7_4 +; RV32I-NEXT: # %bb.3: +; RV32I-NEXT: mv s1, t2 +; RV32I-NEXT: j .LBB7_5 +; RV32I-NEXT: .LBB7_4: +; RV32I-NEXT: sll t5, a0, a1 +; RV32I-NEXT: srli t6, a3, 1 +; RV32I-NEXT: srl t4, t6, t4 +; RV32I-NEXT: or s1, t5, t4 ; RV32I-NEXT: .LBB7_5: -; RV32I-NEXT: sll t6, a0, a1 -; RV32I-NEXT: srli s0, a3, 1 -; RV32I-NEXT: srl s0, s0, t0 -; RV32I-NEXT: or s3, t6, s0 -; RV32I-NEXT: .LBB7_6: -; RV32I-NEXT: neg s1, a1 -; RV32I-NEXT: srl t6, t2, s1 -; RV32I-NEXT: li s2, 32 -; RV32I-NEXT: li s0, 64 -; RV32I-NEXT: sub s2, s2, a1 -; RV32I-NEXT: bltu a1, s0, .LBB7_12 -; RV32I-NEXT: # %bb.7: -; RV32I-NEXT: bnez a1, .LBB7_13 +; RV32I-NEXT: neg t6, a1 +; RV32I-NEXT: srl t4, t0, t6 +; RV32I-NEXT: li s0, 32 +; RV32I-NEXT: li t5, 64 +; RV32I-NEXT: sub s0, s0, a1 +; RV32I-NEXT: bltu a1, t5, .LBB7_11 +; RV32I-NEXT: # %bb.6: +; RV32I-NEXT: bnez a1, .LBB7_12 +; RV32I-NEXT: .LBB7_7: +; RV32I-NEXT: bgez s0, .LBB7_9 ; RV32I-NEXT: .LBB7_8: -; RV32I-NEXT: bgez s2, .LBB7_10 +; RV32I-NEXT: srl a6, a6, t6 +; RV32I-NEXT: slli t0, t0, 1 +; RV32I-NEXT: sub t3, t5, a1 +; RV32I-NEXT: not t3, t3 +; RV32I-NEXT: sll t0, t0, t3 +; RV32I-NEXT: or t4, a6, t0 ; RV32I-NEXT: .LBB7_9: -; RV32I-NEXT: srl a7, a7, s1 -; RV32I-NEXT: slli t2, t2, 1 -; RV32I-NEXT: sub t5, s0, a1 -; RV32I-NEXT: xori t5, t5, 31 -; RV32I-NEXT: sll t2, t2, t5 -; RV32I-NEXT: or t6, a7, t2 -; RV32I-NEXT: .LBB7_10: -; RV32I-NEXT: slti a7, t1, 0 -; RV32I-NEXT: neg a7, a7 -; RV32I-NEXT: bltu a1, s0, .LBB7_14 -; RV32I-NEXT: # %bb.11: -; RV32I-NEXT: slti t2, t3, 0 -; RV32I-NEXT: neg t2, t2 -; RV32I-NEXT: and t2, t2, a4 -; RV32I-NEXT: bnez a1, .LBB7_15 -; RV32I-NEXT: j .LBB7_16 +; RV32I-NEXT: slti a6, a7, 0 +; RV32I-NEXT: neg a6, a6 +; RV32I-NEXT: bltu a1, t5, .LBB7_13 +; RV32I-NEXT: # %bb.10: +; RV32I-NEXT: slti t0, t1, 0 +; RV32I-NEXT: neg t0, t0 +; RV32I-NEXT: and t0, t0, a5 +; RV32I-NEXT: bnez a1, .LBB7_14 +; RV32I-NEXT: j .LBB7_15 +; RV32I-NEXT: .LBB7_11: +; RV32I-NEXT: slti t3, s0, 0 +; RV32I-NEXT: neg t3, t3 +; RV32I-NEXT: and t3, t3, t4 +; RV32I-NEXT: or t3, s1, t3 +; RV32I-NEXT: beqz a1, .LBB7_7 ; RV32I-NEXT: .LBB7_12: -; RV32I-NEXT: slti t5, s2, 0 -; RV32I-NEXT: neg t5, t5 -; RV32I-NEXT: and t5, t5, t6 -; RV32I-NEXT: or t5, s3, t5 -; RV32I-NEXT: beqz a1, .LBB7_8 +; RV32I-NEXT: mv a0, t3 +; RV32I-NEXT: bltz s0, .LBB7_8 +; RV32I-NEXT: j .LBB7_9 ; RV32I-NEXT: .LBB7_13: -; RV32I-NEXT: mv a0, t5 -; RV32I-NEXT: bltz s2, .LBB7_9 -; RV32I-NEXT: j .LBB7_10 +; RV32I-NEXT: and t0, a6, t2 +; RV32I-NEXT: or t0, t0, t4 +; RV32I-NEXT: beqz a1, .LBB7_15 ; RV32I-NEXT: .LBB7_14: -; RV32I-NEXT: and t2, a7, t4 -; RV32I-NEXT: or t2, t2, t6 -; RV32I-NEXT: beqz a1, .LBB7_16 +; RV32I-NEXT: mv a3, t0 ; RV32I-NEXT: .LBB7_15: -; RV32I-NEXT: mv a3, t2 -; RV32I-NEXT: .LBB7_16: -; RV32I-NEXT: bltz t1, .LBB7_18 -; RV32I-NEXT: # %bb.17: -; RV32I-NEXT: mv a5, a4 -; RV32I-NEXT: j .LBB7_19 -; RV32I-NEXT: .LBB7_18: -; RV32I-NEXT: srl a6, a6, t0 -; RV32I-NEXT: or a5, a5, a6 -; RV32I-NEXT: .LBB7_19: +; RV32I-NEXT: bltz a7, .LBB7_17 +; RV32I-NEXT: # %bb.16: +; RV32I-NEXT: mv a4, a5 +; RV32I-NEXT: .LBB7_17: ; RV32I-NEXT: sltiu a1, a1, 64 ; RV32I-NEXT: neg a1, a1 -; RV32I-NEXT: and a5, a1, a5 -; RV32I-NEXT: and a4, a7, a4 -; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: and a4, a1, a4 +; RV32I-NEXT: and a5, a6, a5 +; RV32I-NEXT: and a1, a1, a5 ; RV32I-NEXT: sb a1, 0(a2) -; RV32I-NEXT: sb a5, 4(a2) -; RV32I-NEXT: srli a4, a1, 16 -; RV32I-NEXT: sb a4, 2(a2) -; RV32I-NEXT: srli a4, a1, 24 -; RV32I-NEXT: sb a4, 3(a2) +; RV32I-NEXT: sb a4, 4(a2) +; RV32I-NEXT: srli a5, a1, 16 +; RV32I-NEXT: sb a5, 2(a2) +; RV32I-NEXT: srli a5, a1, 24 +; RV32I-NEXT: sb a5, 3(a2) ; RV32I-NEXT: srli a1, a1, 8 ; RV32I-NEXT: sb a1, 1(a2) -; RV32I-NEXT: srli a1, a5, 16 +; RV32I-NEXT: srli a1, a4, 16 ; RV32I-NEXT: sb a1, 6(a2) -; RV32I-NEXT: srli a1, a5, 24 +; RV32I-NEXT: srli a1, a4, 24 ; RV32I-NEXT: sb a1, 7(a2) -; RV32I-NEXT: srli a5, a5, 8 -; RV32I-NEXT: sb a5, 5(a2) +; RV32I-NEXT: srli a4, a4, 8 +; RV32I-NEXT: sb a4, 5(a2) ; RV32I-NEXT: sb a0, 12(a2) ; RV32I-NEXT: sb a3, 8(a2) ; RV32I-NEXT: srli a1, a0, 16 @@ -1197,8 +1177,6 @@ define void @shl_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sb a3, 9(a2) ; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s3, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret %src = load i128, ptr %src.ptr, align 1 @@ -1288,7 +1266,7 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: or a0, a0, a4 ; RV64I-NEXT: or a0, a0, t0 ; RV64I-NEXT: srl a0, a0, a5 -; RV64I-NEXT: xori a4, a5, 63 +; RV64I-NEXT: not a4, a5 ; RV64I-NEXT: slli a3, a3, 1 ; RV64I-NEXT: sll a3, a3, a4 ; RV64I-NEXT: or a0, a0, a3 @@ -1327,12 +1305,10 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; ; RV32I-LABEL: ashr_16bytes: ; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -32 -; RV32I-NEXT: sw s0, 28(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 24(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 20(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 16(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s4, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: lbu a3, 5(a0) ; RV32I-NEXT: lbu a4, 4(a0) ; RV32I-NEXT: lbu a5, 6(a0) @@ -1346,32 +1322,32 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: lbu a4, 1(a0) ; RV32I-NEXT: lbu a5, 0(a0) ; RV32I-NEXT: lbu a6, 2(a0) -; RV32I-NEXT: lbu a7, 3(a0) +; RV32I-NEXT: lbu t0, 3(a0) ; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or t0, a4, a5 +; RV32I-NEXT: or a7, a4, a5 ; RV32I-NEXT: slli a6, a6, 16 -; RV32I-NEXT: slli a7, a7, 24 -; RV32I-NEXT: or t1, a7, a6 +; RV32I-NEXT: slli t0, t0, 24 +; RV32I-NEXT: or t0, t0, a6 ; RV32I-NEXT: lbu a4, 13(a0) ; RV32I-NEXT: lbu a5, 12(a0) ; RV32I-NEXT: lbu a6, 14(a0) -; RV32I-NEXT: lbu a7, 15(a0) +; RV32I-NEXT: lbu t1, 15(a0) ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: or a4, a4, a5 -; RV32I-NEXT: slli a6, a6, 16 -; RV32I-NEXT: slli a7, a7, 24 -; RV32I-NEXT: or a4, a6, a4 -; RV32I-NEXT: or t2, a7, a4 +; RV32I-NEXT: slli a5, a6, 16 +; RV32I-NEXT: slli a6, t1, 24 +; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: or t1, a6, a4 ; RV32I-NEXT: lbu a4, 9(a0) ; RV32I-NEXT: lbu a5, 8(a0) -; RV32I-NEXT: lbu a6, 10(a0) +; RV32I-NEXT: lbu t2, 10(a0) ; RV32I-NEXT: lbu a0, 11(a0) ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: or a4, a4, a5 -; RV32I-NEXT: slli a6, a6, 16 +; RV32I-NEXT: slli t2, t2, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a4, a6, a4 -; RV32I-NEXT: or t4, a0, a4 +; RV32I-NEXT: or a4, t2, a4 +; RV32I-NEXT: or t2, a0, a4 ; RV32I-NEXT: lbu a0, 1(a1) ; RV32I-NEXT: lbu a4, 0(a1) ; RV32I-NEXT: lbu a5, 2(a1) @@ -1382,122 +1358,89 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a1, a0 -; RV32I-NEXT: slli a4, a0, 3 -; RV32I-NEXT: srl a5, t4, a4 -; RV32I-NEXT: slli a6, t2, 1 -; RV32I-NEXT: addi t5, a4, -96 -; RV32I-NEXT: sra a1, t2, a4 -; RV32I-NEXT: bltz t5, .LBB8_2 +; RV32I-NEXT: slli a5, a0, 3 +; RV32I-NEXT: srl a0, t2, a5 +; RV32I-NEXT: slli a1, t1, 1 +; RV32I-NEXT: not t5, a5 +; RV32I-NEXT: sll a1, a1, t5 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: addi t3, a5, -96 +; RV32I-NEXT: sra a4, t1, a5 +; RV32I-NEXT: mv t6, a0 +; RV32I-NEXT: bltz t3, .LBB8_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: mv s1, a1 -; RV32I-NEXT: j .LBB8_3 +; RV32I-NEXT: mv t6, a4 ; RV32I-NEXT: .LBB8_2: -; RV32I-NEXT: addi a0, a4, -64 -; RV32I-NEXT: xori a0, a0, 31 -; RV32I-NEXT: sll s1, a6, a0 -; RV32I-NEXT: or s1, a5, s1 -; RV32I-NEXT: .LBB8_3: -; RV32I-NEXT: or a0, t1, t0 -; RV32I-NEXT: xori t3, a4, 31 -; RV32I-NEXT: addi t0, a4, -32 -; RV32I-NEXT: srl t6, a3, a4 -; RV32I-NEXT: bltz t0, .LBB8_5 -; RV32I-NEXT: # %bb.4: -; RV32I-NEXT: mv s4, t6 -; RV32I-NEXT: j .LBB8_6 -; RV32I-NEXT: .LBB8_5: -; RV32I-NEXT: srl t1, a0, a4 +; RV32I-NEXT: or a1, t0, a7 +; RV32I-NEXT: addi a7, a5, -32 +; RV32I-NEXT: srl t4, a3, a5 +; RV32I-NEXT: bltz a7, .LBB8_4 +; RV32I-NEXT: # %bb.3: +; RV32I-NEXT: mv s2, t4 +; RV32I-NEXT: j .LBB8_5 +; RV32I-NEXT: .LBB8_4: +; RV32I-NEXT: srl t0, a1, a5 ; RV32I-NEXT: slli s0, a3, 1 -; RV32I-NEXT: sll s0, s0, t3 -; RV32I-NEXT: or s4, t1, s0 -; RV32I-NEXT: .LBB8_6: -; RV32I-NEXT: neg s2, a4 -; RV32I-NEXT: sll s0, t4, s2 -; RV32I-NEXT: li s3, 32 -; RV32I-NEXT: li t1, 64 -; RV32I-NEXT: sub s3, s3, a4 -; RV32I-NEXT: bltu a4, t1, .LBB8_15 -; RV32I-NEXT: # %bb.7: -; RV32I-NEXT: bnez a4, .LBB8_16 +; RV32I-NEXT: sll t5, s0, t5 +; RV32I-NEXT: or s2, t0, t5 +; RV32I-NEXT: .LBB8_5: +; RV32I-NEXT: neg s0, a5 +; RV32I-NEXT: sll t5, t2, s0 +; RV32I-NEXT: li s1, 32 +; RV32I-NEXT: li t0, 64 +; RV32I-NEXT: sub s1, s1, a5 +; RV32I-NEXT: bltu a5, t0, .LBB8_18 +; RV32I-NEXT: # %bb.6: +; RV32I-NEXT: bnez a5, .LBB8_19 +; RV32I-NEXT: .LBB8_7: +; RV32I-NEXT: bgez s1, .LBB8_9 ; RV32I-NEXT: .LBB8_8: -; RV32I-NEXT: bgez s3, .LBB8_10 +; RV32I-NEXT: sll t1, t1, s0 +; RV32I-NEXT: srli t2, t2, 1 +; RV32I-NEXT: sub t5, t0, a5 +; RV32I-NEXT: not t5, t5 +; RV32I-NEXT: srl t2, t2, t5 +; RV32I-NEXT: or t5, t1, t2 ; RV32I-NEXT: .LBB8_9: -; RV32I-NEXT: sll t2, t2, s2 -; RV32I-NEXT: srli t4, t4, 1 -; RV32I-NEXT: sub s0, t1, a4 -; RV32I-NEXT: xori s0, s0, 31 -; RV32I-NEXT: srl t4, t4, s0 -; RV32I-NEXT: or s0, t2, t4 -; RV32I-NEXT: .LBB8_10: -; RV32I-NEXT: srai a7, a7, 31 -; RV32I-NEXT: mv t2, a1 -; RV32I-NEXT: bgez t5, .LBB8_17 -; RV32I-NEXT: # %bb.11: -; RV32I-NEXT: bltu a4, t1, .LBB8_18 +; RV32I-NEXT: srai a6, a6, 31 +; RV32I-NEXT: mv t1, a4 +; RV32I-NEXT: bgez t3, .LBB8_20 +; RV32I-NEXT: # %bb.10: +; RV32I-NEXT: bltu a5, t0, .LBB8_21 +; RV32I-NEXT: .LBB8_11: +; RV32I-NEXT: bnez a5, .LBB8_22 ; RV32I-NEXT: .LBB8_12: -; RV32I-NEXT: bnez a4, .LBB8_19 +; RV32I-NEXT: bgez a7, .LBB8_23 ; RV32I-NEXT: .LBB8_13: -; RV32I-NEXT: bltz t0, .LBB8_20 +; RV32I-NEXT: bgeu a5, t0, .LBB8_24 ; RV32I-NEXT: .LBB8_14: -; RV32I-NEXT: mv a5, a1 -; RV32I-NEXT: bgeu a4, t1, .LBB8_21 -; RV32I-NEXT: j .LBB8_22 +; RV32I-NEXT: bgez a7, .LBB8_25 ; RV32I-NEXT: .LBB8_15: -; RV32I-NEXT: slti s1, s3, 0 -; RV32I-NEXT: neg s1, s1 -; RV32I-NEXT: and s1, s1, s0 -; RV32I-NEXT: or s1, s4, s1 -; RV32I-NEXT: beqz a4, .LBB8_8 +; RV32I-NEXT: bltu a5, t0, .LBB8_17 ; RV32I-NEXT: .LBB8_16: -; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: bltz s3, .LBB8_9 -; RV32I-NEXT: j .LBB8_10 +; RV32I-NEXT: mv a4, a6 ; RV32I-NEXT: .LBB8_17: -; RV32I-NEXT: mv t2, a7 -; RV32I-NEXT: bgeu a4, t1, .LBB8_12 -; RV32I-NEXT: .LBB8_18: -; RV32I-NEXT: slti t2, t0, 0 -; RV32I-NEXT: neg t2, t2 -; RV32I-NEXT: and t2, t2, t6 -; RV32I-NEXT: or t2, t2, s0 -; RV32I-NEXT: beqz a4, .LBB8_13 -; RV32I-NEXT: .LBB8_19: -; RV32I-NEXT: mv a3, t2 -; RV32I-NEXT: bgez t0, .LBB8_14 -; RV32I-NEXT: .LBB8_20: -; RV32I-NEXT: sll a6, a6, t3 -; RV32I-NEXT: or a5, a5, a6 -; RV32I-NEXT: bltu a4, t1, .LBB8_22 -; RV32I-NEXT: .LBB8_21: -; RV32I-NEXT: mv a5, a7 -; RV32I-NEXT: .LBB8_22: -; RV32I-NEXT: bgez t0, .LBB8_26 -; RV32I-NEXT: # %bb.23: -; RV32I-NEXT: bltu a4, t1, .LBB8_25 -; RV32I-NEXT: .LBB8_24: -; RV32I-NEXT: mv a1, a7 -; RV32I-NEXT: .LBB8_25: -; RV32I-NEXT: sb a1, 12(a2) -; RV32I-NEXT: srli a4, a1, 16 -; RV32I-NEXT: sb a4, 14(a2) -; RV32I-NEXT: srli a4, a1, 24 -; RV32I-NEXT: sb a4, 15(a2) -; RV32I-NEXT: srli a1, a1, 8 -; RV32I-NEXT: sb a1, 13(a2) -; RV32I-NEXT: sb a5, 8(a2) -; RV32I-NEXT: srli a1, a5, 16 -; RV32I-NEXT: sb a1, 10(a2) -; RV32I-NEXT: srli a1, a5, 24 -; RV32I-NEXT: sb a1, 11(a2) -; RV32I-NEXT: srli a5, a5, 8 -; RV32I-NEXT: sb a5, 9(a2) -; RV32I-NEXT: sb a0, 0(a2) -; RV32I-NEXT: srli a1, a0, 16 -; RV32I-NEXT: sb a1, 2(a2) -; RV32I-NEXT: srli a1, a0, 24 -; RV32I-NEXT: sb a1, 3(a2) +; RV32I-NEXT: sb a4, 12(a2) +; RV32I-NEXT: srli a5, a4, 16 +; RV32I-NEXT: sb a5, 14(a2) +; RV32I-NEXT: srli a5, a4, 24 +; RV32I-NEXT: sb a5, 15(a2) +; RV32I-NEXT: srli a4, a4, 8 +; RV32I-NEXT: sb a4, 13(a2) +; RV32I-NEXT: sb a0, 8(a2) +; RV32I-NEXT: srli a4, a0, 16 +; RV32I-NEXT: sb a4, 10(a2) +; RV32I-NEXT: srli a4, a0, 24 +; RV32I-NEXT: sb a4, 11(a2) ; RV32I-NEXT: srli a0, a0, 8 -; RV32I-NEXT: sb a0, 1(a2) +; RV32I-NEXT: sb a0, 9(a2) +; RV32I-NEXT: sb a1, 0(a2) +; RV32I-NEXT: srli a0, a1, 16 +; RV32I-NEXT: sb a0, 2(a2) +; RV32I-NEXT: srli a0, a1, 24 +; RV32I-NEXT: sb a0, 3(a2) +; RV32I-NEXT: srli a1, a1, 8 +; RV32I-NEXT: sb a1, 1(a2) ; RV32I-NEXT: sb a3, 4(a2) ; RV32I-NEXT: srli a0, a3, 16 ; RV32I-NEXT: sb a0, 6(a2) @@ -1505,17 +1448,43 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sb a0, 7(a2) ; RV32I-NEXT: srli a3, a3, 8 ; RV32I-NEXT: sb a3, 5(a2) -; RV32I-NEXT: lw s0, 28(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 24(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 20(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s3, 16(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s4, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 32 +; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB8_26: -; RV32I-NEXT: mv a1, a7 -; RV32I-NEXT: bgeu a4, t1, .LBB8_24 -; RV32I-NEXT: j .LBB8_25 +; RV32I-NEXT: .LBB8_18: +; RV32I-NEXT: slti t6, s1, 0 +; RV32I-NEXT: neg t6, t6 +; RV32I-NEXT: and t6, t6, t5 +; RV32I-NEXT: or t6, s2, t6 +; RV32I-NEXT: beqz a5, .LBB8_7 +; RV32I-NEXT: .LBB8_19: +; RV32I-NEXT: mv a1, t6 +; RV32I-NEXT: bltz s1, .LBB8_8 +; RV32I-NEXT: j .LBB8_9 +; RV32I-NEXT: .LBB8_20: +; RV32I-NEXT: mv t1, a6 +; RV32I-NEXT: bgeu a5, t0, .LBB8_11 +; RV32I-NEXT: .LBB8_21: +; RV32I-NEXT: slti t1, a7, 0 +; RV32I-NEXT: neg t1, t1 +; RV32I-NEXT: and t1, t1, t4 +; RV32I-NEXT: or t1, t1, t5 +; RV32I-NEXT: beqz a5, .LBB8_12 +; RV32I-NEXT: .LBB8_22: +; RV32I-NEXT: mv a3, t1 +; RV32I-NEXT: bltz a7, .LBB8_13 +; RV32I-NEXT: .LBB8_23: +; RV32I-NEXT: mv a0, a4 +; RV32I-NEXT: bltu a5, t0, .LBB8_14 +; RV32I-NEXT: .LBB8_24: +; RV32I-NEXT: mv a0, a6 +; RV32I-NEXT: bltz a7, .LBB8_15 +; RV32I-NEXT: .LBB8_25: +; RV32I-NEXT: mv a4, a6 +; RV32I-NEXT: bgeu a5, t0, .LBB8_16 +; RV32I-NEXT: j .LBB8_17 %src = load i128, ptr %src.ptr, align 1 %byteOff = load i128, ptr %byteOff.ptr, align 1 %bitOff = shl i128 %byteOff, 3 @@ -1527,11 +1496,9 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-LABEL: lshr_32bytes: ; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -32 -; RV64I-NEXT: sd s0, 24(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s1, 16(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s2, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s3, 0(sp) # 8-byte Folded Spill +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd s0, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s1, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: lbu a3, 9(a0) ; RV64I-NEXT: lbu a4, 8(a0) ; RV64I-NEXT: lbu a5, 10(a0) @@ -1563,186 +1530,179 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a6, a6, 16 ; RV64I-NEXT: slli a7, a7, 24 ; RV64I-NEXT: or a4, a6, a4 -; RV64I-NEXT: or a6, a7, a4 +; RV64I-NEXT: or a5, a7, a4 ; RV64I-NEXT: lbu a4, 5(a0) -; RV64I-NEXT: lbu a5, 4(a0) +; RV64I-NEXT: lbu a6, 4(a0) ; RV64I-NEXT: lbu a7, 6(a0) ; RV64I-NEXT: lbu t0, 7(a0) ; RV64I-NEXT: slli a4, a4, 8 -; RV64I-NEXT: or a4, a4, a5 +; RV64I-NEXT: or a4, a4, a6 ; RV64I-NEXT: slli a7, a7, 16 ; RV64I-NEXT: slli t0, t0, 24 ; RV64I-NEXT: or a4, a7, a4 -; RV64I-NEXT: lbu a5, 25(a0) -; RV64I-NEXT: lbu a7, 24(a0) -; RV64I-NEXT: lbu t1, 26(a0) -; RV64I-NEXT: or a4, t0, a4 -; RV64I-NEXT: slli a5, a5, 8 -; RV64I-NEXT: or a5, a5, a7 -; RV64I-NEXT: slli t1, t1, 16 -; RV64I-NEXT: lbu a7, 29(a0) -; RV64I-NEXT: lbu t0, 27(a0) -; RV64I-NEXT: or a5, t1, a5 -; RV64I-NEXT: lbu t1, 28(a0) -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: or t0, t0, a4 +; RV64I-NEXT: slli t0, t0, 32 +; RV64I-NEXT: lbu a4, 25(a0) +; RV64I-NEXT: lbu a6, 24(a0) +; RV64I-NEXT: lbu a7, 26(a0) +; RV64I-NEXT: lbu t1, 27(a0) +; RV64I-NEXT: slli a4, a4, 8 +; RV64I-NEXT: or a4, a4, a6 +; RV64I-NEXT: slli a7, a7, 16 +; RV64I-NEXT: slli t1, t1, 24 +; RV64I-NEXT: or a4, a7, a4 +; RV64I-NEXT: lbu a6, 29(a0) +; RV64I-NEXT: lbu a7, 28(a0) ; RV64I-NEXT: lbu t2, 30(a0) ; RV64I-NEXT: lbu t3, 31(a0) -; RV64I-NEXT: or a7, a7, t1 -; RV64I-NEXT: slli t0, t0, 24 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: or a6, a6, a7 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or a7, t2, a7 -; RV64I-NEXT: or a7, t3, a7 -; RV64I-NEXT: slli a7, a7, 32 -; RV64I-NEXT: or a5, a7, a5 -; RV64I-NEXT: lbu a7, 17(a0) -; RV64I-NEXT: lbu t1, 16(a0) -; RV64I-NEXT: lbu t2, 18(a0) -; RV64I-NEXT: or a5, a5, t0 -; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a7, a7, t1 -; RV64I-NEXT: slli t2, t2, 16 -; RV64I-NEXT: lbu t0, 21(a0) -; RV64I-NEXT: lbu t1, 20(a0) -; RV64I-NEXT: or a7, t2, a7 +; RV64I-NEXT: or a6, t2, a6 +; RV64I-NEXT: or a6, t3, a6 +; RV64I-NEXT: slli a6, a6, 32 +; RV64I-NEXT: or a4, a6, a4 +; RV64I-NEXT: or a4, a4, t1 +; RV64I-NEXT: lbu a6, 17(a0) +; RV64I-NEXT: lbu a7, 16(a0) +; RV64I-NEXT: lbu t1, 18(a0) ; RV64I-NEXT: lbu t2, 19(a0) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t1 -; RV64I-NEXT: lbu t1, 22(a0) -; RV64I-NEXT: lbu t3, 23(a0) -; RV64I-NEXT: slli a0, a4, 32 -; RV64I-NEXT: slli t2, t2, 24 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: or a6, a6, a7 ; RV64I-NEXT: slli t1, t1, 16 -; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or a4, t1, t0 -; RV64I-NEXT: or a4, t3, a4 -; RV64I-NEXT: slli a4, a4, 32 -; RV64I-NEXT: or a4, a4, a7 -; RV64I-NEXT: or t1, a4, t2 -; RV64I-NEXT: lbu a4, 5(a1) -; RV64I-NEXT: lbu a7, 4(a1) -; RV64I-NEXT: lbu t0, 6(a1) +; RV64I-NEXT: slli t2, t2, 24 +; RV64I-NEXT: or a6, t1, a6 +; RV64I-NEXT: lbu a7, 21(a0) +; RV64I-NEXT: lbu t1, 20(a0) +; RV64I-NEXT: lbu t3, 22(a0) +; RV64I-NEXT: lbu a0, 23(a0) +; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: or a7, a7, t1 +; RV64I-NEXT: slli t3, t3, 16 +; RV64I-NEXT: slli a0, a0, 24 +; RV64I-NEXT: or a7, t3, a7 +; RV64I-NEXT: or a0, a0, a7 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: or t1, a0, t2 +; RV64I-NEXT: lbu a0, 5(a1) +; RV64I-NEXT: lbu a6, 4(a1) +; RV64I-NEXT: lbu a7, 6(a1) ; RV64I-NEXT: lbu t2, 7(a1) -; RV64I-NEXT: slli a4, a4, 8 -; RV64I-NEXT: or a4, a4, a7 -; RV64I-NEXT: slli t0, t0, 16 +; RV64I-NEXT: slli a0, a0, 8 +; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: slli a7, a7, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a4, t0, a4 -; RV64I-NEXT: or a4, t2, a4 -; RV64I-NEXT: lbu a7, 1(a1) -; RV64I-NEXT: lbu t0, 0(a1) +; RV64I-NEXT: or a0, a7, a0 +; RV64I-NEXT: or a0, t2, a0 +; RV64I-NEXT: lbu a6, 1(a1) +; RV64I-NEXT: lbu a7, 0(a1) ; RV64I-NEXT: lbu t2, 2(a1) ; RV64I-NEXT: lbu a1, 3(a1) -; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a7, a7, t0 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: or a6, a6, a7 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a7, t2, a7 -; RV64I-NEXT: or a1, a1, a7 +; RV64I-NEXT: or a6, t2, a6 +; RV64I-NEXT: or a1, a1, a6 ; RV64I-NEXT: slli a1, a1, 3 -; RV64I-NEXT: slli a4, a4, 35 -; RV64I-NEXT: or a1, a4, a1 -; RV64I-NEXT: srl a7, t1, a1 -; RV64I-NEXT: slli t0, a5, 1 -; RV64I-NEXT: addi t3, a1, -192 -; RV64I-NEXT: srl a4, a5, a1 -; RV64I-NEXT: bltz t3, .LBB9_2 +; RV64I-NEXT: slli a0, a0, 35 +; RV64I-NEXT: or a1, a0, a1 +; RV64I-NEXT: srl a0, t1, a1 +; RV64I-NEXT: not t4, a1 +; RV64I-NEXT: slli a6, a4, 1 +; RV64I-NEXT: sll a6, a6, t4 +; RV64I-NEXT: or a6, a0, a6 +; RV64I-NEXT: addi t2, a1, -192 +; RV64I-NEXT: srl a7, a4, a1 +; RV64I-NEXT: mv t3, a6 +; RV64I-NEXT: bltz t2, .LBB9_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv t5, a4 -; RV64I-NEXT: j .LBB9_3 +; RV64I-NEXT: mv t3, a7 ; RV64I-NEXT: .LBB9_2: -; RV64I-NEXT: addiw t2, a1, -128 -; RV64I-NEXT: xori t2, t2, 63 -; RV64I-NEXT: sll t2, t0, t2 -; RV64I-NEXT: or t5, a7, t2 -; RV64I-NEXT: .LBB9_3: -; RV64I-NEXT: or a0, a0, a6 -; RV64I-NEXT: xori a6, a1, 63 -; RV64I-NEXT: addi t2, a1, -64 -; RV64I-NEXT: srl t4, a3, a1 -; RV64I-NEXT: bltz t2, .LBB9_5 -; RV64I-NEXT: # %bb.4: -; RV64I-NEXT: mv s3, t4 -; RV64I-NEXT: j .LBB9_6 +; RV64I-NEXT: or a0, t0, a5 +; RV64I-NEXT: addi a5, a1, -64 +; RV64I-NEXT: srl t0, a3, a1 +; RV64I-NEXT: bltz a5, .LBB9_4 +; RV64I-NEXT: # %bb.3: +; RV64I-NEXT: mv s1, t0 +; RV64I-NEXT: j .LBB9_5 +; RV64I-NEXT: .LBB9_4: +; RV64I-NEXT: srl t5, a0, a1 +; RV64I-NEXT: slli t6, a3, 1 +; RV64I-NEXT: sll t4, t6, t4 +; RV64I-NEXT: or s1, t5, t4 ; RV64I-NEXT: .LBB9_5: -; RV64I-NEXT: srl t6, a0, a1 -; RV64I-NEXT: slli s0, a3, 1 -; RV64I-NEXT: sll s0, s0, a6 -; RV64I-NEXT: or s3, t6, s0 -; RV64I-NEXT: .LBB9_6: -; RV64I-NEXT: negw s1, a1 -; RV64I-NEXT: sll t6, t1, s1 -; RV64I-NEXT: li s2, 64 -; RV64I-NEXT: li s0, 128 -; RV64I-NEXT: sub s2, s2, a1 -; RV64I-NEXT: bltu a1, s0, .LBB9_12 -; RV64I-NEXT: # %bb.7: -; RV64I-NEXT: bnez a1, .LBB9_13 +; RV64I-NEXT: negw t6, a1 +; RV64I-NEXT: sll t4, t1, t6 +; RV64I-NEXT: li s0, 64 +; RV64I-NEXT: li t5, 128 +; RV64I-NEXT: sub s0, s0, a1 +; RV64I-NEXT: bltu a1, t5, .LBB9_11 +; RV64I-NEXT: # %bb.6: +; RV64I-NEXT: bnez a1, .LBB9_12 +; RV64I-NEXT: .LBB9_7: +; RV64I-NEXT: bgez s0, .LBB9_9 ; RV64I-NEXT: .LBB9_8: -; RV64I-NEXT: bgez s2, .LBB9_10 -; RV64I-NEXT: .LBB9_9: -; RV64I-NEXT: sll a5, a5, s1 +; RV64I-NEXT: sll a4, a4, t6 ; RV64I-NEXT: srli t1, t1, 1 -; RV64I-NEXT: subw t5, s0, a1 -; RV64I-NEXT: xori t5, t5, 63 -; RV64I-NEXT: srl t1, t1, t5 -; RV64I-NEXT: or t6, a5, t1 -; RV64I-NEXT: .LBB9_10: -; RV64I-NEXT: slti a5, t2, 0 -; RV64I-NEXT: neg a5, a5 -; RV64I-NEXT: bltu a1, s0, .LBB9_14 -; RV64I-NEXT: # %bb.11: -; RV64I-NEXT: slti t1, t3, 0 -; RV64I-NEXT: neg t1, t1 -; RV64I-NEXT: and t1, t1, a4 -; RV64I-NEXT: bnez a1, .LBB9_15 -; RV64I-NEXT: j .LBB9_16 +; RV64I-NEXT: subw t3, t5, a1 +; RV64I-NEXT: not t3, t3 +; RV64I-NEXT: srl t1, t1, t3 +; RV64I-NEXT: or t4, a4, t1 +; RV64I-NEXT: .LBB9_9: +; RV64I-NEXT: slti a4, a5, 0 +; RV64I-NEXT: neg a4, a4 +; RV64I-NEXT: bltu a1, t5, .LBB9_13 +; RV64I-NEXT: # %bb.10: +; RV64I-NEXT: slti t0, t2, 0 +; RV64I-NEXT: neg t0, t0 +; RV64I-NEXT: and t0, t0, a7 +; RV64I-NEXT: bnez a1, .LBB9_14 +; RV64I-NEXT: j .LBB9_15 +; RV64I-NEXT: .LBB9_11: +; RV64I-NEXT: slti t3, s0, 0 +; RV64I-NEXT: neg t3, t3 +; RV64I-NEXT: and t3, t3, t4 +; RV64I-NEXT: or t3, s1, t3 +; RV64I-NEXT: beqz a1, .LBB9_7 ; RV64I-NEXT: .LBB9_12: -; RV64I-NEXT: slti t5, s2, 0 -; RV64I-NEXT: neg t5, t5 -; RV64I-NEXT: and t5, t5, t6 -; RV64I-NEXT: or t5, s3, t5 -; RV64I-NEXT: beqz a1, .LBB9_8 +; RV64I-NEXT: mv a0, t3 +; RV64I-NEXT: bltz s0, .LBB9_8 +; RV64I-NEXT: j .LBB9_9 ; RV64I-NEXT: .LBB9_13: -; RV64I-NEXT: mv a0, t5 -; RV64I-NEXT: bltz s2, .LBB9_9 -; RV64I-NEXT: j .LBB9_10 +; RV64I-NEXT: and t0, a4, t0 +; RV64I-NEXT: or t0, t0, t4 +; RV64I-NEXT: beqz a1, .LBB9_15 ; RV64I-NEXT: .LBB9_14: -; RV64I-NEXT: and t1, a5, t4 -; RV64I-NEXT: or t1, t1, t6 -; RV64I-NEXT: beqz a1, .LBB9_16 +; RV64I-NEXT: mv a3, t0 ; RV64I-NEXT: .LBB9_15: -; RV64I-NEXT: mv a3, t1 -; RV64I-NEXT: .LBB9_16: -; RV64I-NEXT: bltz t2, .LBB9_18 -; RV64I-NEXT: # %bb.17: -; RV64I-NEXT: mv a6, a4 -; RV64I-NEXT: j .LBB9_19 -; RV64I-NEXT: .LBB9_18: -; RV64I-NEXT: sll a6, t0, a6 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: .LBB9_19: +; RV64I-NEXT: bltz a5, .LBB9_17 +; RV64I-NEXT: # %bb.16: +; RV64I-NEXT: mv a6, a7 +; RV64I-NEXT: .LBB9_17: ; RV64I-NEXT: sltiu a1, a1, 128 ; RV64I-NEXT: neg a1, a1 -; RV64I-NEXT: and a6, a1, a6 -; RV64I-NEXT: and a4, a5, a4 +; RV64I-NEXT: and a5, a1, a6 +; RV64I-NEXT: and a4, a4, a7 ; RV64I-NEXT: and a1, a1, a4 -; RV64I-NEXT: sb a6, 16(a2) +; RV64I-NEXT: sb a5, 16(a2) ; RV64I-NEXT: sb a1, 24(a2) -; RV64I-NEXT: srli a4, a6, 56 +; RV64I-NEXT: srli a4, a5, 56 ; RV64I-NEXT: sb a4, 23(a2) -; RV64I-NEXT: srli a4, a6, 48 +; RV64I-NEXT: srli a4, a5, 48 ; RV64I-NEXT: sb a4, 22(a2) -; RV64I-NEXT: srli a4, a6, 40 +; RV64I-NEXT: srli a4, a5, 40 ; RV64I-NEXT: sb a4, 21(a2) -; RV64I-NEXT: srli a4, a6, 32 +; RV64I-NEXT: srli a4, a5, 32 ; RV64I-NEXT: sb a4, 20(a2) -; RV64I-NEXT: srli a4, a6, 24 +; RV64I-NEXT: srli a4, a5, 24 ; RV64I-NEXT: sb a4, 19(a2) -; RV64I-NEXT: srli a4, a6, 16 +; RV64I-NEXT: srli a4, a5, 16 ; RV64I-NEXT: sb a4, 18(a2) -; RV64I-NEXT: srli a4, a6, 8 -; RV64I-NEXT: sb a4, 17(a2) +; RV64I-NEXT: srli a5, a5, 8 +; RV64I-NEXT: sb a5, 17(a2) ; RV64I-NEXT: srli a4, a1, 56 ; RV64I-NEXT: sb a4, 31(a2) ; RV64I-NEXT: srli a4, a1, 48 @@ -1787,597 +1747,573 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: sb a0, 10(a2) ; RV64I-NEXT: srli a3, a3, 8 ; RV64I-NEXT: sb a3, 9(a2) -; RV64I-NEXT: ld s0, 24(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s1, 16(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s2, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s3, 0(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 32 +; RV64I-NEXT: ld s0, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s1, 0(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; ; RV32I-LABEL: lshr_32bytes: ; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -144 -; RV32I-NEXT: sw ra, 140(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 136(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 132(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 128(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 124(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s4, 120(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s5, 116(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s6, 112(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s7, 108(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s8, 104(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s9, 100(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s10, 96(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s11, 92(sp) # 4-byte Folded Spill -; RV32I-NEXT: lbu a7, 4(a0) +; RV32I-NEXT: addi sp, sp, -112 +; RV32I-NEXT: sw ra, 108(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 104(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 100(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 96(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s3, 92(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s4, 88(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s5, 84(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s6, 80(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s7, 76(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s8, 72(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s9, 68(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s10, 64(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s11, 60(sp) # 4-byte Folded Spill +; RV32I-NEXT: lbu a6, 4(a0) ; RV32I-NEXT: lbu t4, 5(a0) -; RV32I-NEXT: lbu t5, 6(a0) +; RV32I-NEXT: lbu t6, 6(a0) ; RV32I-NEXT: lbu s0, 7(a0) -; RV32I-NEXT: lbu t0, 0(a0) -; RV32I-NEXT: lbu t1, 1(a0) -; RV32I-NEXT: lbu t2, 2(a0) +; RV32I-NEXT: lbu a7, 0(a0) +; RV32I-NEXT: lbu t0, 1(a0) +; RV32I-NEXT: lbu t1, 2(a0) ; RV32I-NEXT: lbu t3, 3(a0) ; RV32I-NEXT: lbu s1, 12(a0) -; RV32I-NEXT: lbu t6, 13(a0) +; RV32I-NEXT: lbu t5, 13(a0) ; RV32I-NEXT: lbu s3, 14(a0) -; RV32I-NEXT: lbu s4, 15(a0) +; RV32I-NEXT: lbu s6, 15(a0) ; RV32I-NEXT: lbu s2, 8(a0) -; RV32I-NEXT: lbu s5, 9(a0) -; RV32I-NEXT: lbu s6, 10(a0) -; RV32I-NEXT: lbu s7, 11(a0) +; RV32I-NEXT: lbu s7, 9(a0) +; RV32I-NEXT: lbu s8, 10(a0) +; RV32I-NEXT: lbu s9, 11(a0) ; RV32I-NEXT: lbu a3, 21(a0) ; RV32I-NEXT: lbu a4, 20(a0) ; RV32I-NEXT: lbu a5, 22(a0) -; RV32I-NEXT: lbu a6, 23(a0) +; RV32I-NEXT: lbu t2, 23(a0) ; RV32I-NEXT: slli a3, a3, 8 ; RV32I-NEXT: or a3, a3, a4 ; RV32I-NEXT: slli a5, a5, 16 -; RV32I-NEXT: slli a6, a6, 24 +; RV32I-NEXT: slli t2, t2, 24 ; RV32I-NEXT: or a3, a5, a3 -; RV32I-NEXT: or a3, a6, a3 +; RV32I-NEXT: or a3, t2, a3 ; RV32I-NEXT: lbu a4, 17(a0) ; RV32I-NEXT: lbu a5, 16(a0) -; RV32I-NEXT: lbu a6, 18(a0) -; RV32I-NEXT: lbu s8, 19(a0) +; RV32I-NEXT: lbu t2, 18(a0) +; RV32I-NEXT: lbu s4, 19(a0) ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: or a4, a4, a5 -; RV32I-NEXT: slli a6, a6, 16 -; RV32I-NEXT: slli s8, s8, 24 -; RV32I-NEXT: or a4, a6, a4 -; RV32I-NEXT: or a5, s8, a4 +; RV32I-NEXT: slli t2, t2, 16 +; RV32I-NEXT: slli s4, s4, 24 +; RV32I-NEXT: or a4, t2, a4 +; RV32I-NEXT: or s10, s4, a4 ; RV32I-NEXT: lbu a4, 29(a0) -; RV32I-NEXT: lbu a6, 28(a0) -; RV32I-NEXT: lbu s8, 30(a0) -; RV32I-NEXT: lbu s9, 31(a0) +; RV32I-NEXT: lbu a5, 28(a0) +; RV32I-NEXT: lbu t2, 30(a0) +; RV32I-NEXT: lbu s4, 31(a0) ; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a4, a4, a6 -; RV32I-NEXT: slli s8, s8, 16 -; RV32I-NEXT: slli s9, s9, 24 -; RV32I-NEXT: or a4, s8, a4 -; RV32I-NEXT: or s10, s9, a4 +; RV32I-NEXT: or a4, a4, a5 +; RV32I-NEXT: slli t2, t2, 16 +; RV32I-NEXT: slli s4, s4, 24 +; RV32I-NEXT: or a4, t2, a4 +; RV32I-NEXT: or s11, s4, a4 ; RV32I-NEXT: lbu a4, 25(a0) -; RV32I-NEXT: lbu a6, 24(a0) -; RV32I-NEXT: lbu s8, 26(a0) +; RV32I-NEXT: lbu a5, 24(a0) +; RV32I-NEXT: lbu t2, 26(a0) ; RV32I-NEXT: lbu a0, 27(a0) ; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a4, a4, a6 -; RV32I-NEXT: slli s8, s8, 16 +; RV32I-NEXT: or a4, a4, a5 +; RV32I-NEXT: slli t2, t2, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a4, s8, a4 -; RV32I-NEXT: or s9, a0, a4 +; RV32I-NEXT: or a4, t2, a4 +; RV32I-NEXT: or s5, a0, a4 ; RV32I-NEXT: lbu a0, 1(a1) ; RV32I-NEXT: lbu a4, 0(a1) -; RV32I-NEXT: lbu a6, 2(a1) +; RV32I-NEXT: lbu a5, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a0, a0, 8 ; RV32I-NEXT: or a0, a0, a4 -; RV32I-NEXT: slli a6, a6, 16 +; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a0, a6, a0 +; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a1, a0 -; RV32I-NEXT: slli a6, a0, 3 -; RV32I-NEXT: srl a1, s9, a6 -; RV32I-NEXT: slli a4, s10, 1 -; RV32I-NEXT: addi s8, a6, -224 -; RV32I-NEXT: sw s10, 84(sp) # 4-byte Folded Spill -; RV32I-NEXT: srl a0, s10, a6 -; RV32I-NEXT: sw s8, 28(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a0, 88(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a1, 68(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a4, 64(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgez s8, .LBB9_2 +; RV32I-NEXT: slli a5, a0, 3 +; RV32I-NEXT: srl a0, s5, a5 +; RV32I-NEXT: slli a1, s11, 1 +; RV32I-NEXT: not s4, a5 +; RV32I-NEXT: sll a1, a1, s4 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: addi a4, a5, -224 +; RV32I-NEXT: sw s11, 44(sp) # 4-byte Folded Spill +; RV32I-NEXT: srl a1, s11, a5 +; RV32I-NEXT: sw a0, 52(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a4, 20(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz a4, .LBB9_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: addi a0, a6, -192 -; RV32I-NEXT: xori a0, a0, 31 -; RV32I-NEXT: sll a0, a4, a0 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: .LBB9_2: -; RV32I-NEXT: slli a4, t6, 8 +; RV32I-NEXT: sw a1, 56(sp) # 4-byte Folded Spill +; RV32I-NEXT: slli t2, t5, 8 ; RV32I-NEXT: slli s3, s3, 16 -; RV32I-NEXT: slli s4, s4, 24 -; RV32I-NEXT: slli s5, s5, 8 -; RV32I-NEXT: slli s6, s6, 16 -; RV32I-NEXT: slli s8, s7, 24 -; RV32I-NEXT: srl s10, a5, a6 -; RV32I-NEXT: slli a1, a3, 1 -; RV32I-NEXT: addi s11, a6, -128 -; RV32I-NEXT: xori t6, s11, 31 -; RV32I-NEXT: addi ra, a6, -160 -; RV32I-NEXT: srl s7, a3, a6 -; RV32I-NEXT: sw ra, 72(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s7, 60(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a1, 44(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz ra, .LBB9_4 +; RV32I-NEXT: slli s11, s6, 24 +; RV32I-NEXT: slli ra, s7, 8 +; RV32I-NEXT: slli s8, s8, 16 +; RV32I-NEXT: slli s9, s9, 24 +; RV32I-NEXT: srl a1, s10, a5 +; RV32I-NEXT: slli t5, a3, 1 +; RV32I-NEXT: sll a4, t5, s4 +; RV32I-NEXT: or s6, a1, a4 +; RV32I-NEXT: addi s7, a5, -160 +; RV32I-NEXT: srl a1, a3, a5 +; RV32I-NEXT: sw a1, 48(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s6, 32(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz s7, .LBB9_4 ; RV32I-NEXT: # %bb.3: -; RV32I-NEXT: mv ra, t6 -; RV32I-NEXT: j .LBB9_5 +; RV32I-NEXT: lw s6, 48(sp) # 4-byte Folded Reload ; RV32I-NEXT: .LBB9_4: -; RV32I-NEXT: mv ra, t6 -; RV32I-NEXT: sll a1, a1, t6 -; RV32I-NEXT: or s7, s10, a1 -; RV32I-NEXT: .LBB9_5: -; RV32I-NEXT: slli t4, t4, 8 -; RV32I-NEXT: slli a1, t5, 16 +; RV32I-NEXT: slli a4, t4, 8 +; RV32I-NEXT: slli t6, t6, 16 ; RV32I-NEXT: slli s0, s0, 24 -; RV32I-NEXT: or a4, a4, s1 -; RV32I-NEXT: or s1, s4, s3 -; RV32I-NEXT: or s2, s5, s2 -; RV32I-NEXT: or s3, s8, s6 -; RV32I-NEXT: neg s4, a6 -; RV32I-NEXT: sll s6, s9, s4 -; RV32I-NEXT: li s5, 160 -; RV32I-NEXT: li t5, 64 -; RV32I-NEXT: sub t6, s5, a6 -; RV32I-NEXT: sw s6, 80(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgeu s11, t5, .LBB9_7 -; RV32I-NEXT: # %bb.6: -; RV32I-NEXT: slti a0, t6, 0 +; RV32I-NEXT: or t2, t2, s1 +; RV32I-NEXT: or s1, s11, s3 +; RV32I-NEXT: or s2, ra, s2 +; RV32I-NEXT: or s3, s9, s8 +; RV32I-NEXT: neg s11, a5 +; RV32I-NEXT: sll t4, s5, s11 +; RV32I-NEXT: li a1, 160 +; RV32I-NEXT: addi s8, a5, -128 +; RV32I-NEXT: li s9, 64 +; RV32I-NEXT: sub a1, a1, a5 +; RV32I-NEXT: bltu s8, s9, .LBB9_6 +; RV32I-NEXT: # %bb.5: +; RV32I-NEXT: mv ra, t4 +; RV32I-NEXT: j .LBB9_7 +; RV32I-NEXT: .LBB9_6: +; RV32I-NEXT: slti a0, a1, 0 ; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: and a0, a0, s6 -; RV32I-NEXT: or a0, s7, a0 +; RV32I-NEXT: mv ra, t4 +; RV32I-NEXT: and a0, a0, t4 +; RV32I-NEXT: or a0, s6, a0 ; RV32I-NEXT: .LBB9_7: -; RV32I-NEXT: sw s10, 36(sp) # 4-byte Folded Spill -; RV32I-NEXT: slli t1, t1, 8 -; RV32I-NEXT: slli t2, t2, 16 -; RV32I-NEXT: slli s5, t3, 24 -; RV32I-NEXT: or t3, t4, a7 -; RV32I-NEXT: or a1, s0, a1 -; RV32I-NEXT: or a7, s1, a4 -; RV32I-NEXT: or s1, s3, s2 -; RV32I-NEXT: mv s8, a5 -; RV32I-NEXT: beqz s11, .LBB9_9 +; RV32I-NEXT: sw a1, 28(sp) # 4-byte Folded Spill +; RV32I-NEXT: slli t0, t0, 8 +; RV32I-NEXT: slli t1, t1, 16 +; RV32I-NEXT: slli s6, t3, 24 +; RV32I-NEXT: or t3, a4, a6 +; RV32I-NEXT: or t6, s0, t6 +; RV32I-NEXT: or a6, s1, t2 +; RV32I-NEXT: or s3, s3, s2 +; RV32I-NEXT: mv s9, s10 +; RV32I-NEXT: beqz s8, .LBB9_9 ; RV32I-NEXT: # %bb.8: -; RV32I-NEXT: mv s8, a0 +; RV32I-NEXT: mv s9, a0 ; RV32I-NEXT: .LBB9_9: -; RV32I-NEXT: or a0, t1, t0 -; RV32I-NEXT: or t0, s5, t2 -; RV32I-NEXT: or a1, a1, t3 -; RV32I-NEXT: srl s6, s1, a6 -; RV32I-NEXT: slli s10, a7, 1 -; RV32I-NEXT: addi a4, a6, -64 -; RV32I-NEXT: xori a4, a4, 31 -; RV32I-NEXT: addi t1, a6, -96 -; RV32I-NEXT: srl t2, a7, a6 -; RV32I-NEXT: sw t1, 76(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a4, 32(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw t2, 48(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz t1, .LBB9_11 +; RV32I-NEXT: or a4, t0, a7 +; RV32I-NEXT: or t0, s6, t1 +; RV32I-NEXT: or a0, t6, t3 +; RV32I-NEXT: srl a1, s3, a5 +; RV32I-NEXT: slli a7, a6, 1 +; RV32I-NEXT: sll a7, a7, s4 +; RV32I-NEXT: or s2, a1, a7 +; RV32I-NEXT: addi t2, a5, -96 +; RV32I-NEXT: srl a1, a6, a5 +; RV32I-NEXT: sw a1, 40(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv a7, s2 +; RV32I-NEXT: bltz t2, .LBB9_11 ; RV32I-NEXT: # %bb.10: -; RV32I-NEXT: mv a4, t2 -; RV32I-NEXT: j .LBB9_12 +; RV32I-NEXT: lw a7, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: .LBB9_11: -; RV32I-NEXT: sll a4, s10, a4 -; RV32I-NEXT: or a4, s6, a4 -; RV32I-NEXT: .LBB9_12: -; RV32I-NEXT: or t2, t0, a0 -; RV32I-NEXT: xori t1, a6, 31 -; RV32I-NEXT: addi s2, a6, -32 -; RV32I-NEXT: srl s0, a1, a6 -; RV32I-NEXT: sw t1, 56(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz s2, .LBB9_14 -; RV32I-NEXT: # %bb.13: -; RV32I-NEXT: mv t0, s0 -; RV32I-NEXT: j .LBB9_15 -; RV32I-NEXT: .LBB9_14: -; RV32I-NEXT: srl a0, t2, a6 -; RV32I-NEXT: slli t0, a1, 1 -; RV32I-NEXT: sll t0, t0, t1 -; RV32I-NEXT: or t0, a0, t0 +; RV32I-NEXT: or t0, t0, a4 +; RV32I-NEXT: addi t6, a5, -32 +; RV32I-NEXT: srl t1, a0, a5 +; RV32I-NEXT: sw t1, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgez t6, .LBB9_13 +; RV32I-NEXT: # %bb.12: +; RV32I-NEXT: srl a1, t0, a5 +; RV32I-NEXT: slli a4, a0, 1 +; RV32I-NEXT: sll a4, a4, s4 +; RV32I-NEXT: or t1, a1, a4 +; RV32I-NEXT: .LBB9_13: +; RV32I-NEXT: sll t3, s3, s11 +; RV32I-NEXT: li a4, 32 +; RV32I-NEXT: sub s0, a4, a5 +; RV32I-NEXT: slti a1, s0, 0 +; RV32I-NEXT: neg s1, a1 +; RV32I-NEXT: li a1, 64 +; RV32I-NEXT: bgeu a5, a1, .LBB9_15 +; RV32I-NEXT: # %bb.14: +; RV32I-NEXT: and a1, s1, t3 +; RV32I-NEXT: or a7, t1, a1 ; RV32I-NEXT: .LBB9_15: -; RV32I-NEXT: sll t4, s1, s4 -; RV32I-NEXT: li a0, 32 -; RV32I-NEXT: sub s3, a0, a6 -; RV32I-NEXT: slti t1, s3, 0 -; RV32I-NEXT: neg t1, t1 -; RV32I-NEXT: bgeu a6, t5, .LBB9_17 +; RV32I-NEXT: mv t4, s7 +; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv s4, t0 +; RV32I-NEXT: beqz a5, .LBB9_17 ; RV32I-NEXT: # %bb.16: -; RV32I-NEXT: and a4, t1, t4 -; RV32I-NEXT: or a4, t0, a4 +; RV32I-NEXT: mv s4, a7 ; RV32I-NEXT: .LBB9_17: -; RV32I-NEXT: sw t6, 40(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw t1, 52(sp) # 4-byte Folded Spill -; RV32I-NEXT: mv t0, t2 -; RV32I-NEXT: beqz a6, .LBB9_19 +; RV32I-NEXT: sll s1, s10, s11 +; RV32I-NEXT: li a1, 96 +; RV32I-NEXT: sub s6, a1, a5 +; RV32I-NEXT: slti a1, s6, 0 +; RV32I-NEXT: neg a7, a1 +; RV32I-NEXT: li s7, 128 +; RV32I-NEXT: sub t1, s7, a5 +; RV32I-NEXT: sltiu a1, t1, 64 +; RV32I-NEXT: neg a1, a1 +; RV32I-NEXT: sw a1, 4(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgeu a5, s7, .LBB9_19 ; RV32I-NEXT: # %bb.18: -; RV32I-NEXT: mv t0, a4 +; RV32I-NEXT: mv s7, a1 +; RV32I-NEXT: and a1, a7, s1 +; RV32I-NEXT: and a1, s7, a1 +; RV32I-NEXT: or s9, s4, a1 ; RV32I-NEXT: .LBB9_19: -; RV32I-NEXT: sll s5, a5, s4 -; RV32I-NEXT: li a4, 96 -; RV32I-NEXT: sub s7, a4, a6 -; RV32I-NEXT: slti a4, s7, 0 -; RV32I-NEXT: neg a4, a4 -; RV32I-NEXT: li t6, 128 -; RV32I-NEXT: sub t1, t6, a6 -; RV32I-NEXT: sltiu t3, t1, 64 -; RV32I-NEXT: neg t3, t3 -; RV32I-NEXT: sw t3, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgeu a6, t6, .LBB9_21 +; RV32I-NEXT: mv s4, ra +; RV32I-NEXT: mv s7, t4 +; RV32I-NEXT: li ra, 64 +; RV32I-NEXT: beqz a5, .LBB9_21 ; RV32I-NEXT: # %bb.20: -; RV32I-NEXT: mv t6, t3 -; RV32I-NEXT: and t3, a4, s5 -; RV32I-NEXT: and t3, t6, t3 -; RV32I-NEXT: or s8, t0, t3 +; RV32I-NEXT: mv t0, s9 ; RV32I-NEXT: .LBB9_21: -; RV32I-NEXT: beqz a6, .LBB9_23 +; RV32I-NEXT: neg a1, t1 +; RV32I-NEXT: sub a4, a4, t1 +; RV32I-NEXT: srl t4, a3, a1 +; RV32I-NEXT: sw a4, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz a4, .LBB9_24 ; RV32I-NEXT: # %bb.22: -; RV32I-NEXT: mv t2, s8 +; RV32I-NEXT: mv a1, t4 +; RV32I-NEXT: lw t5, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgeu t1, ra, .LBB9_25 ; RV32I-NEXT: .LBB9_23: -; RV32I-NEXT: neg t0, t1 -; RV32I-NEXT: sub t3, a0, t1 -; RV32I-NEXT: srl a0, a3, t0 -; RV32I-NEXT: sw t3, 20(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgez t3, .LBB9_25 -; RV32I-NEXT: # %bb.24: -; RV32I-NEXT: srl a0, a5, t0 -; RV32I-NEXT: sub t0, t5, t1 -; RV32I-NEXT: xori t0, t0, 31 -; RV32I-NEXT: lw t3, 44(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll t0, t3, t0 -; RV32I-NEXT: or a0, a0, t0 +; RV32I-NEXT: and a4, a7, s4 +; RV32I-NEXT: or a7, a4, a1 +; RV32I-NEXT: mv a4, s5 +; RV32I-NEXT: bnez t1, .LBB9_26 +; RV32I-NEXT: j .LBB9_27 +; RV32I-NEXT: .LBB9_24: +; RV32I-NEXT: srl a1, s10, a1 +; RV32I-NEXT: sub a4, ra, t1 +; RV32I-NEXT: not a4, a4 +; RV32I-NEXT: sll a4, t5, a4 +; RV32I-NEXT: or a1, a1, a4 +; RV32I-NEXT: lw t5, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltu t1, ra, .LBB9_23 ; RV32I-NEXT: .LBB9_25: -; RV32I-NEXT: bltu t1, t5, .LBB9_27 -; RV32I-NEXT: # %bb.26: -; RV32I-NEXT: lw a0, 52(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a0, s5 -; RV32I-NEXT: mv a0, s9 -; RV32I-NEXT: bnez t1, .LBB9_28 -; RV32I-NEXT: j .LBB9_29 +; RV32I-NEXT: lw a1, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a7, a1, s1 +; RV32I-NEXT: mv a4, s5 +; RV32I-NEXT: beqz t1, .LBB9_27 +; RV32I-NEXT: .LBB9_26: +; RV32I-NEXT: mv a4, a7 ; RV32I-NEXT: .LBB9_27: -; RV32I-NEXT: lw t0, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a4, t0 -; RV32I-NEXT: or a4, a4, a0 -; RV32I-NEXT: mv a0, s9 -; RV32I-NEXT: beqz t1, .LBB9_29 -; RV32I-NEXT: .LBB9_28: -; RV32I-NEXT: mv a0, a4 +; RV32I-NEXT: bltz t6, .LBB9_29 +; RV32I-NEXT: # %bb.28: +; RV32I-NEXT: lw s2, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: .LBB9_29: -; RV32I-NEXT: bltz s2, .LBB9_31 +; RV32I-NEXT: sltiu a1, a5, 64 +; RV32I-NEXT: mv a7, t5 +; RV32I-NEXT: bltz s7, .LBB9_31 ; RV32I-NEXT: # %bb.30: -; RV32I-NEXT: lw a4, 48(sp) # 4-byte Folded Reload -; RV32I-NEXT: j .LBB9_32 +; RV32I-NEXT: lw a7, 56(sp) # 4-byte Folded Reload ; RV32I-NEXT: .LBB9_31: -; RV32I-NEXT: lw a4, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a4, s10, a4 -; RV32I-NEXT: or a4, s6, a4 -; RV32I-NEXT: .LBB9_32: -; RV32I-NEXT: sltiu t0, a6, 64 -; RV32I-NEXT: lw t3, 72(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz t3, .LBB9_34 -; RV32I-NEXT: # %bb.33: -; RV32I-NEXT: lw t3, 88(sp) # 4-byte Folded Reload +; RV32I-NEXT: neg s9, a1 +; RV32I-NEXT: sltiu a1, s8, 64 +; RV32I-NEXT: neg t5, a1 +; RV32I-NEXT: li a1, 128 +; RV32I-NEXT: bltu a5, a1, .LBB9_33 +; RV32I-NEXT: # %bb.32: +; RV32I-NEXT: and a4, t5, a7 +; RV32I-NEXT: mv s2, s3 +; RV32I-NEXT: bnez a5, .LBB9_34 ; RV32I-NEXT: j .LBB9_35 +; RV32I-NEXT: .LBB9_33: +; RV32I-NEXT: and a1, s9, s2 +; RV32I-NEXT: or a4, a1, a4 +; RV32I-NEXT: mv s2, s3 +; RV32I-NEXT: beqz a5, .LBB9_35 ; RV32I-NEXT: .LBB9_34: -; RV32I-NEXT: lw t3, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll t3, t3, ra -; RV32I-NEXT: lw t6, 68(sp) # 4-byte Folded Reload -; RV32I-NEXT: or t3, t6, t3 +; RV32I-NEXT: mv s2, a4 ; RV32I-NEXT: .LBB9_35: -; RV32I-NEXT: neg t6, t0 -; RV32I-NEXT: sltiu t0, s11, 64 -; RV32I-NEXT: neg s6, t0 -; RV32I-NEXT: li t0, 128 -; RV32I-NEXT: sw s6, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltu a6, t0, .LBB9_37 +; RV32I-NEXT: sub a1, ra, a5 +; RV32I-NEXT: not a7, a1 +; RV32I-NEXT: bgez s0, .LBB9_37 ; RV32I-NEXT: # %bb.36: -; RV32I-NEXT: and a0, s6, t3 -; RV32I-NEXT: mv s6, s1 -; RV32I-NEXT: bnez a6, .LBB9_38 -; RV32I-NEXT: j .LBB9_39 +; RV32I-NEXT: sll a1, a6, s11 +; RV32I-NEXT: srli a4, s3, 1 +; RV32I-NEXT: srl a4, a4, a7 +; RV32I-NEXT: or t3, a1, a4 ; RV32I-NEXT: .LBB9_37: -; RV32I-NEXT: and a4, t6, a4 -; RV32I-NEXT: or a0, a4, a0 -; RV32I-NEXT: mv s6, s1 -; RV32I-NEXT: beqz a6, .LBB9_39 -; RV32I-NEXT: .LBB9_38: -; RV32I-NEXT: mv s6, a0 +; RV32I-NEXT: slti a1, t6, 0 +; RV32I-NEXT: neg s3, a1 +; RV32I-NEXT: slti a1, t2, 0 +; RV32I-NEXT: neg a4, a1 +; RV32I-NEXT: sw a7, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a4, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltu a5, ra, .LBB9_39 +; RV32I-NEXT: # %bb.38: +; RV32I-NEXT: lw a1, 40(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a4, a4, a1 +; RV32I-NEXT: j .LBB9_40 ; RV32I-NEXT: .LBB9_39: -; RV32I-NEXT: sub a0, t5, a6 -; RV32I-NEXT: xori s10, a0, 31 -; RV32I-NEXT: bgez s3, .LBB9_41 -; RV32I-NEXT: # %bb.40: -; RV32I-NEXT: sll a0, a7, s4 -; RV32I-NEXT: srli s1, s1, 1 -; RV32I-NEXT: srl a4, s1, s10 -; RV32I-NEXT: or t4, a0, a4 -; RV32I-NEXT: .LBB9_41: -; RV32I-NEXT: slti a0, s2, 0 -; RV32I-NEXT: neg s1, a0 -; RV32I-NEXT: lw a0, 76(sp) # 4-byte Folded Reload -; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: neg a4, a0 -; RV32I-NEXT: sw a4, 16(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltu a6, t5, .LBB9_43 -; RV32I-NEXT: # %bb.42: -; RV32I-NEXT: lw a0, 48(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a4, a0 -; RV32I-NEXT: mv t0, a1 -; RV32I-NEXT: bnez a6, .LBB9_44 +; RV32I-NEXT: lw a1, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, s3, a1 +; RV32I-NEXT: or a4, a1, t3 +; RV32I-NEXT: .LBB9_40: +; RV32I-NEXT: sw t5, 0(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t4, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv a7, a0 +; RV32I-NEXT: beqz a5, .LBB9_42 +; RV32I-NEXT: # %bb.41: +; RV32I-NEXT: mv a7, a4 +; RV32I-NEXT: .LBB9_42: +; RV32I-NEXT: mv t4, t2 +; RV32I-NEXT: mv ra, s4 +; RV32I-NEXT: sll s4, a3, s11 +; RV32I-NEXT: srli a4, s10, 1 +; RV32I-NEXT: not t5, t1 +; RV32I-NEXT: bltz s6, .LBB9_44 +; RV32I-NEXT: # %bb.43: +; RV32I-NEXT: mv t2, s1 ; RV32I-NEXT: j .LBB9_45 -; RV32I-NEXT: .LBB9_43: -; RV32I-NEXT: and s0, s1, s0 -; RV32I-NEXT: or a0, s0, t4 -; RV32I-NEXT: mv t0, a1 -; RV32I-NEXT: beqz a6, .LBB9_45 ; RV32I-NEXT: .LBB9_44: -; RV32I-NEXT: mv t0, a0 +; RV32I-NEXT: srl a1, a4, t5 +; RV32I-NEXT: or t2, s4, a1 ; RV32I-NEXT: .LBB9_45: -; RV32I-NEXT: sll s8, a3, s4 -; RV32I-NEXT: srli a4, a5, 1 -; RV32I-NEXT: xori a0, t1, 31 -; RV32I-NEXT: bltz s7, .LBB9_47 +; RV32I-NEXT: lw a1, 44(sp) # 4-byte Folded Reload +; RV32I-NEXT: sll t3, a1, s11 +; RV32I-NEXT: srli s5, s5, 1 +; RV32I-NEXT: lw a1, 28(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a1, .LBB9_47 ; RV32I-NEXT: # %bb.46: -; RV32I-NEXT: mv t3, s5 +; RV32I-NEXT: mv s11, ra ; RV32I-NEXT: j .LBB9_48 ; RV32I-NEXT: .LBB9_47: -; RV32I-NEXT: srl t3, a4, a0 -; RV32I-NEXT: or t3, s8, t3 +; RV32I-NEXT: li a1, 192 +; RV32I-NEXT: sub a1, a1, a5 +; RV32I-NEXT: not a1, a1 +; RV32I-NEXT: srl a1, s5, a1 +; RV32I-NEXT: or s11, t3, a1 ; RV32I-NEXT: .LBB9_48: -; RV32I-NEXT: lw t4, 84(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll s0, t4, s4 -; RV32I-NEXT: srli s4, s9, 1 -; RV32I-NEXT: lw t4, 40(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz t4, .LBB9_50 +; RV32I-NEXT: slti a1, s7, 0 +; RV32I-NEXT: neg s7, a1 +; RV32I-NEXT: li a1, 64 +; RV32I-NEXT: bltu s8, a1, .LBB9_50 ; RV32I-NEXT: # %bb.49: -; RV32I-NEXT: lw s9, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: j .LBB9_51 +; RV32I-NEXT: lw a1, 20(sp) # 4-byte Folded Reload +; RV32I-NEXT: slti a1, a1, 0 +; RV32I-NEXT: neg a1, a1 +; RV32I-NEXT: lw s11, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, a1, s11 +; RV32I-NEXT: mv s11, a3 +; RV32I-NEXT: bnez s8, .LBB9_51 +; RV32I-NEXT: j .LBB9_52 ; RV32I-NEXT: .LBB9_50: -; RV32I-NEXT: li t4, 192 -; RV32I-NEXT: sub t4, t4, a6 -; RV32I-NEXT: xori t4, t4, 31 -; RV32I-NEXT: srl t4, s4, t4 -; RV32I-NEXT: or s9, s0, t4 +; RV32I-NEXT: lw a1, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, s7, a1 +; RV32I-NEXT: or a1, a1, s11 +; RV32I-NEXT: mv s11, a3 +; RV32I-NEXT: beqz s8, .LBB9_52 ; RV32I-NEXT: .LBB9_51: -; RV32I-NEXT: lw t4, 72(sp) # 4-byte Folded Reload -; RV32I-NEXT: slti t4, t4, 0 -; RV32I-NEXT: neg t4, t4 -; RV32I-NEXT: bltu s11, t5, .LBB9_53 -; RV32I-NEXT: # %bb.52: -; RV32I-NEXT: lw s9, 28(sp) # 4-byte Folded Reload -; RV32I-NEXT: slti s9, s9, 0 -; RV32I-NEXT: neg s9, s9 -; RV32I-NEXT: lw ra, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: and ra, s9, ra -; RV32I-NEXT: mv s9, a3 -; RV32I-NEXT: bnez s11, .LBB9_54 -; RV32I-NEXT: j .LBB9_55 -; RV32I-NEXT: .LBB9_53: -; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload -; RV32I-NEXT: and ra, t4, ra -; RV32I-NEXT: or ra, ra, s9 -; RV32I-NEXT: mv s9, a3 -; RV32I-NEXT: beqz s11, .LBB9_55 +; RV32I-NEXT: mv s11, a1 +; RV32I-NEXT: .LBB9_52: +; RV32I-NEXT: li a1, 128 +; RV32I-NEXT: bltu a5, a1, .LBB9_57 +; RV32I-NEXT: # %bb.53: +; RV32I-NEXT: bnez a5, .LBB9_58 ; RV32I-NEXT: .LBB9_54: -; RV32I-NEXT: mv s9, ra +; RV32I-NEXT: bltz s0, .LBB9_59 ; RV32I-NEXT: .LBB9_55: -; RV32I-NEXT: li s11, 128 -; RV32I-NEXT: bgeu a6, s11, .LBB9_57 -; RV32I-NEXT: # %bb.56: -; RV32I-NEXT: lw s9, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: and t3, s9, t3 -; RV32I-NEXT: or s9, t0, t3 +; RV32I-NEXT: bltz s6, .LBB9_60 +; RV32I-NEXT: .LBB9_56: +; RV32I-NEXT: mv a4, ra +; RV32I-NEXT: j .LBB9_61 ; RV32I-NEXT: .LBB9_57: -; RV32I-NEXT: lw t3, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s11, 68(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw ra, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: bnez a6, .LBB9_61 -; RV32I-NEXT: # %bb.58: -; RV32I-NEXT: bltz s3, .LBB9_62 +; RV32I-NEXT: lw a1, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, a1, t2 +; RV32I-NEXT: or s11, a7, a1 +; RV32I-NEXT: beqz a5, .LBB9_54 +; RV32I-NEXT: .LBB9_58: +; RV32I-NEXT: mv a0, s11 +; RV32I-NEXT: bgez s0, .LBB9_55 ; RV32I-NEXT: .LBB9_59: -; RV32I-NEXT: lw s8, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz s7, .LBB9_63 +; RV32I-NEXT: lw a1, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: srl a1, a4, a1 +; RV32I-NEXT: or s1, s4, a1 +; RV32I-NEXT: bgez s6, .LBB9_56 ; RV32I-NEXT: .LBB9_60: -; RV32I-NEXT: mv a0, s8 -; RV32I-NEXT: lw t0, 60(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltu t1, t5, .LBB9_64 -; RV32I-NEXT: j .LBB9_65 +; RV32I-NEXT: srl a1, s5, t5 +; RV32I-NEXT: or a4, t3, a1 ; RV32I-NEXT: .LBB9_61: -; RV32I-NEXT: mv a1, s9 -; RV32I-NEXT: bgez s3, .LBB9_59 -; RV32I-NEXT: .LBB9_62: -; RV32I-NEXT: srl a4, a4, s10 -; RV32I-NEXT: or s5, s8, a4 -; RV32I-NEXT: lw s8, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgez s7, .LBB9_60 +; RV32I-NEXT: lw t5, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: li a1, 64 +; RV32I-NEXT: bltu t1, a1, .LBB9_65 +; RV32I-NEXT: # %bb.62: +; RV32I-NEXT: bnez t1, .LBB9_66 ; RV32I-NEXT: .LBB9_63: -; RV32I-NEXT: srl a0, s4, a0 -; RV32I-NEXT: or a0, s0, a0 -; RV32I-NEXT: lw t0, 60(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgeu t1, t5, .LBB9_65 +; RV32I-NEXT: li a1, 128 +; RV32I-NEXT: bltu a5, a1, .LBB9_67 ; RV32I-NEXT: .LBB9_64: -; RV32I-NEXT: lw a4, 20(sp) # 4-byte Folded Reload -; RV32I-NEXT: slti a4, a4, 0 -; RV32I-NEXT: neg a4, a4 -; RV32I-NEXT: lw s5, 24(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a4, s5 -; RV32I-NEXT: or s5, a0, a4 +; RV32I-NEXT: lw t2, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, s7, t2 +; RV32I-NEXT: lw a4, 0(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, a4, a1 +; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: bnez a5, .LBB9_68 +; RV32I-NEXT: j .LBB9_69 ; RV32I-NEXT: .LBB9_65: -; RV32I-NEXT: bnez t1, .LBB9_68 -; RV32I-NEXT: # %bb.66: -; RV32I-NEXT: li a0, 128 -; RV32I-NEXT: bltu a6, a0, .LBB9_69 +; RV32I-NEXT: lw a1, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: slti a1, a1, 0 +; RV32I-NEXT: neg a1, a1 +; RV32I-NEXT: lw t2, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, a1, t2 +; RV32I-NEXT: or s1, a4, a1 +; RV32I-NEXT: beqz t1, .LBB9_63 +; RV32I-NEXT: .LBB9_66: +; RV32I-NEXT: sw s1, 44(sp) # 4-byte Folded Spill +; RV32I-NEXT: li a1, 128 +; RV32I-NEXT: bgeu a5, a1, .LBB9_64 ; RV32I-NEXT: .LBB9_67: -; RV32I-NEXT: and a0, t4, t3 -; RV32I-NEXT: lw a4, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a4, a0 -; RV32I-NEXT: lw t4, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: bnez a6, .LBB9_70 -; RV32I-NEXT: j .LBB9_71 +; RV32I-NEXT: lw a1, 40(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, s3, a1 +; RV32I-NEXT: and a1, s9, a1 +; RV32I-NEXT: lw a4, 44(sp) # 4-byte Folded Reload +; RV32I-NEXT: or a1, a1, a4 +; RV32I-NEXT: lw t2, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: beqz a5, .LBB9_69 ; RV32I-NEXT: .LBB9_68: -; RV32I-NEXT: sw s5, 84(sp) # 4-byte Folded Spill -; RV32I-NEXT: li a0, 128 -; RV32I-NEXT: bgeu a6, a0, .LBB9_67 +; RV32I-NEXT: mv a6, a1 ; RV32I-NEXT: .LBB9_69: -; RV32I-NEXT: lw a0, 48(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, s1, a0 -; RV32I-NEXT: and a0, t6, a0 -; RV32I-NEXT: lw a4, 84(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a0, a0, a4 -; RV32I-NEXT: lw t4, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: beqz a6, .LBB9_71 -; RV32I-NEXT: .LBB9_70: -; RV32I-NEXT: mv a7, a0 +; RV32I-NEXT: mv a4, t5 +; RV32I-NEXT: bgez t4, .LBB9_76 +; RV32I-NEXT: # %bb.70: +; RV32I-NEXT: bgez t6, .LBB9_77 ; RV32I-NEXT: .LBB9_71: -; RV32I-NEXT: lw a0, 76(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz a0, .LBB9_74 -; RV32I-NEXT: # %bb.72: -; RV32I-NEXT: mv a0, t3 -; RV32I-NEXT: bgez s2, .LBB9_75 +; RV32I-NEXT: li t1, 64 +; RV32I-NEXT: bltu a5, t1, .LBB9_78 +; RV32I-NEXT: .LBB9_72: +; RV32I-NEXT: bnez a5, .LBB9_79 ; RV32I-NEXT: .LBB9_73: -; RV32I-NEXT: lw a4, 44(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a4, a4, t4 -; RV32I-NEXT: lw t1, 36(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a4, t1, a4 -; RV32I-NEXT: lw t1, 52(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltu a6, t5, .LBB9_76 -; RV32I-NEXT: j .LBB9_77 +; RV32I-NEXT: bltz s0, .LBB9_80 ; RV32I-NEXT: .LBB9_74: -; RV32I-NEXT: lw a0, 32(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a0, ra, a0 -; RV32I-NEXT: or a0, s11, a0 -; RV32I-NEXT: bltz s2, .LBB9_73 +; RV32I-NEXT: sltiu a4, a5, 128 +; RV32I-NEXT: bltu a5, t1, .LBB9_81 ; RV32I-NEXT: .LBB9_75: -; RV32I-NEXT: mv a4, t0 -; RV32I-NEXT: lw t1, 52(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgeu a6, t5, .LBB9_77 +; RV32I-NEXT: lw a1, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: and t1, a1, t2 +; RV32I-NEXT: neg a7, a4 +; RV32I-NEXT: bnez a5, .LBB9_82 +; RV32I-NEXT: j .LBB9_83 ; RV32I-NEXT: .LBB9_76: -; RV32I-NEXT: and a0, t1, s8 -; RV32I-NEXT: or a0, a4, a0 +; RV32I-NEXT: mv a4, t2 +; RV32I-NEXT: bltz t6, .LBB9_71 ; RV32I-NEXT: .LBB9_77: -; RV32I-NEXT: bnez a6, .LBB9_81 -; RV32I-NEXT: # %bb.78: -; RV32I-NEXT: bltz s3, .LBB9_82 +; RV32I-NEXT: lw a1, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a1, 32(sp) # 4-byte Folded Spill +; RV32I-NEXT: li t1, 64 +; RV32I-NEXT: bgeu a5, t1, .LBB9_72 +; RV32I-NEXT: .LBB9_78: +; RV32I-NEXT: and a1, s1, ra +; RV32I-NEXT: lw a4, 32(sp) # 4-byte Folded Reload +; RV32I-NEXT: or a4, a4, a1 +; RV32I-NEXT: beqz a5, .LBB9_73 ; RV32I-NEXT: .LBB9_79: -; RV32I-NEXT: sltiu a0, a6, 128 -; RV32I-NEXT: bltu a6, t5, .LBB9_83 +; RV32I-NEXT: mv s10, a4 +; RV32I-NEXT: bgez s0, .LBB9_74 ; RV32I-NEXT: .LBB9_80: -; RV32I-NEXT: lw a4, 16(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a4, t3 -; RV32I-NEXT: neg t0, a0 -; RV32I-NEXT: bnez a6, .LBB9_84 -; RV32I-NEXT: j .LBB9_85 +; RV32I-NEXT: lw a1, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: srl a1, s5, a1 +; RV32I-NEXT: or ra, t3, a1 +; RV32I-NEXT: sltiu a4, a5, 128 +; RV32I-NEXT: bgeu a5, t1, .LBB9_75 ; RV32I-NEXT: .LBB9_81: -; RV32I-NEXT: mv a5, a0 -; RV32I-NEXT: bgez s3, .LBB9_79 +; RV32I-NEXT: lw a1, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, s3, a1 +; RV32I-NEXT: or t1, a1, ra +; RV32I-NEXT: neg a7, a4 +; RV32I-NEXT: beqz a5, .LBB9_83 ; RV32I-NEXT: .LBB9_82: -; RV32I-NEXT: srl a0, s4, s10 -; RV32I-NEXT: or s8, s0, a0 -; RV32I-NEXT: sltiu a0, a6, 128 -; RV32I-NEXT: bgeu a6, t5, .LBB9_80 +; RV32I-NEXT: mv a3, t1 ; RV32I-NEXT: .LBB9_83: -; RV32I-NEXT: and a4, s1, t0 -; RV32I-NEXT: or a4, a4, s8 -; RV32I-NEXT: neg t0, a0 -; RV32I-NEXT: beqz a6, .LBB9_85 -; RV32I-NEXT: .LBB9_84: -; RV32I-NEXT: mv a3, a4 +; RV32I-NEXT: and a4, a7, s10 +; RV32I-NEXT: and a3, a7, a3 +; RV32I-NEXT: bltz t6, .LBB9_85 +; RV32I-NEXT: # %bb.84: +; RV32I-NEXT: mv t5, t2 ; RV32I-NEXT: .LBB9_85: -; RV32I-NEXT: and a4, t0, a5 -; RV32I-NEXT: and a0, t0, a3 -; RV32I-NEXT: bltz s2, .LBB9_87 -; RV32I-NEXT: # %bb.86: -; RV32I-NEXT: mv a3, t3 -; RV32I-NEXT: j .LBB9_88 -; RV32I-NEXT: .LBB9_87: -; RV32I-NEXT: sll a3, ra, t4 -; RV32I-NEXT: or a3, s11, a3 -; RV32I-NEXT: .LBB9_88: -; RV32I-NEXT: and a3, t6, a3 -; RV32I-NEXT: and a3, t0, a3 -; RV32I-NEXT: and a5, s1, t3 -; RV32I-NEXT: and a5, t6, a5 -; RV32I-NEXT: and a5, t0, a5 -; RV32I-NEXT: sb a3, 24(a2) +; RV32I-NEXT: and a1, s9, t5 +; RV32I-NEXT: and a1, a7, a1 +; RV32I-NEXT: and a5, s3, t2 +; RV32I-NEXT: and a5, s9, a5 +; RV32I-NEXT: and a5, a7, a5 +; RV32I-NEXT: sb a1, 24(a2) ; RV32I-NEXT: sb a5, 28(a2) -; RV32I-NEXT: srli a6, a3, 24 -; RV32I-NEXT: sb a6, 27(a2) -; RV32I-NEXT: srli a6, a3, 16 -; RV32I-NEXT: sb a6, 26(a2) -; RV32I-NEXT: srli a3, a3, 8 -; RV32I-NEXT: sb a3, 25(a2) -; RV32I-NEXT: srli a3, a5, 24 -; RV32I-NEXT: sb a3, 31(a2) -; RV32I-NEXT: srli a3, a5, 16 -; RV32I-NEXT: sb a3, 30(a2) +; RV32I-NEXT: srli a7, a1, 24 +; RV32I-NEXT: sb a7, 27(a2) +; RV32I-NEXT: srli a7, a1, 16 +; RV32I-NEXT: sb a7, 26(a2) +; RV32I-NEXT: srli a1, a1, 8 +; RV32I-NEXT: sb a1, 25(a2) +; RV32I-NEXT: srli a1, a5, 24 +; RV32I-NEXT: sb a1, 31(a2) +; RV32I-NEXT: srli a1, a5, 16 +; RV32I-NEXT: sb a1, 30(a2) ; RV32I-NEXT: srli a5, a5, 8 ; RV32I-NEXT: sb a5, 29(a2) ; RV32I-NEXT: sb a4, 16(a2) -; RV32I-NEXT: srli a3, a4, 24 -; RV32I-NEXT: sb a3, 19(a2) -; RV32I-NEXT: srli a3, a4, 16 -; RV32I-NEXT: sb a3, 18(a2) +; RV32I-NEXT: srli a1, a4, 24 +; RV32I-NEXT: sb a1, 19(a2) +; RV32I-NEXT: srli a1, a4, 16 +; RV32I-NEXT: sb a1, 18(a2) ; RV32I-NEXT: srli a4, a4, 8 ; RV32I-NEXT: sb a4, 17(a2) -; RV32I-NEXT: sb a0, 20(a2) -; RV32I-NEXT: srli a3, a0, 24 -; RV32I-NEXT: sb a3, 23(a2) -; RV32I-NEXT: srli a3, a0, 16 -; RV32I-NEXT: sb a3, 22(a2) +; RV32I-NEXT: sb a3, 20(a2) +; RV32I-NEXT: srli a1, a3, 24 +; RV32I-NEXT: sb a1, 23(a2) +; RV32I-NEXT: srli a1, a3, 16 +; RV32I-NEXT: sb a1, 22(a2) +; RV32I-NEXT: srli a3, a3, 8 +; RV32I-NEXT: sb a3, 21(a2) +; RV32I-NEXT: sb t0, 0(a2) +; RV32I-NEXT: sb a6, 12(a2) +; RV32I-NEXT: srli a1, t0, 24 +; RV32I-NEXT: sb a1, 3(a2) +; RV32I-NEXT: srli a1, t0, 16 +; RV32I-NEXT: sb a1, 2(a2) +; RV32I-NEXT: srli a1, t0, 8 +; RV32I-NEXT: sb a1, 1(a2) +; RV32I-NEXT: sb a0, 4(a2) +; RV32I-NEXT: sb s2, 8(a2) +; RV32I-NEXT: srli a1, a6, 24 +; RV32I-NEXT: sb a1, 15(a2) +; RV32I-NEXT: srli a1, a6, 16 +; RV32I-NEXT: sb a1, 14(a2) +; RV32I-NEXT: srli a1, a6, 8 +; RV32I-NEXT: sb a1, 13(a2) +; RV32I-NEXT: srli a1, a0, 24 +; RV32I-NEXT: sb a1, 7(a2) +; RV32I-NEXT: srli a1, a0, 16 +; RV32I-NEXT: sb a1, 6(a2) ; RV32I-NEXT: srli a0, a0, 8 -; RV32I-NEXT: sb a0, 21(a2) -; RV32I-NEXT: sb t2, 0(a2) -; RV32I-NEXT: sb a7, 12(a2) -; RV32I-NEXT: srli a0, t2, 24 -; RV32I-NEXT: sb a0, 3(a2) -; RV32I-NEXT: srli a0, t2, 16 -; RV32I-NEXT: sb a0, 2(a2) -; RV32I-NEXT: srli a0, t2, 8 -; RV32I-NEXT: sb a0, 1(a2) -; RV32I-NEXT: sb a1, 4(a2) -; RV32I-NEXT: sb s6, 8(a2) -; RV32I-NEXT: srli a0, a7, 24 -; RV32I-NEXT: sb a0, 15(a2) -; RV32I-NEXT: srli a0, a7, 16 -; RV32I-NEXT: sb a0, 14(a2) -; RV32I-NEXT: srli a0, a7, 8 -; RV32I-NEXT: sb a0, 13(a2) -; RV32I-NEXT: srli a0, a1, 24 -; RV32I-NEXT: sb a0, 7(a2) -; RV32I-NEXT: srli a0, a1, 16 -; RV32I-NEXT: sb a0, 6(a2) -; RV32I-NEXT: srli a1, a1, 8 -; RV32I-NEXT: sb a1, 5(a2) -; RV32I-NEXT: srli a0, s6, 24 +; RV32I-NEXT: sb a0, 5(a2) +; RV32I-NEXT: srli a0, s2, 24 ; RV32I-NEXT: sb a0, 11(a2) -; RV32I-NEXT: srli a0, s6, 16 +; RV32I-NEXT: srli a0, s2, 16 ; RV32I-NEXT: sb a0, 10(a2) -; RV32I-NEXT: srli a0, s6, 8 +; RV32I-NEXT: srli a0, s2, 8 ; RV32I-NEXT: sb a0, 9(a2) -; RV32I-NEXT: lw ra, 140(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 136(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 132(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 128(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s3, 124(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s4, 120(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s5, 116(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s6, 112(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s7, 108(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s8, 104(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s9, 100(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s10, 96(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s11, 92(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 144 +; RV32I-NEXT: lw ra, 108(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 104(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 100(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 96(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s3, 92(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s4, 88(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s5, 84(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s6, 80(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s7, 76(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s8, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s9, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s10, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s11, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 112 ; RV32I-NEXT: ret %src = load i256, ptr %src.ptr, align 1 %byteOff = load i256, ptr %byteOff.ptr, align 1 @@ -2389,11 +2325,9 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-LABEL: shl_32bytes: ; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -32 -; RV64I-NEXT: sd s0, 24(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s1, 16(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s2, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s3, 0(sp) # 8-byte Folded Spill +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd s0, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s1, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: lbu a3, 17(a0) ; RV64I-NEXT: lbu a4, 16(a0) ; RV64I-NEXT: lbu a5, 18(a0) @@ -2425,172 +2359,165 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a6, a6, 16 ; RV64I-NEXT: slli a7, a7, 24 ; RV64I-NEXT: or a4, a6, a4 -; RV64I-NEXT: or a6, a7, a4 +; RV64I-NEXT: or a5, a7, a4 ; RV64I-NEXT: lbu a4, 29(a0) -; RV64I-NEXT: lbu a5, 28(a0) +; RV64I-NEXT: lbu a6, 28(a0) ; RV64I-NEXT: lbu a7, 30(a0) ; RV64I-NEXT: lbu t0, 31(a0) ; RV64I-NEXT: slli a4, a4, 8 -; RV64I-NEXT: or a4, a4, a5 +; RV64I-NEXT: or a4, a4, a6 ; RV64I-NEXT: slli a7, a7, 16 ; RV64I-NEXT: slli t0, t0, 24 ; RV64I-NEXT: or a4, a7, a4 -; RV64I-NEXT: lbu a5, 1(a0) -; RV64I-NEXT: lbu a7, 0(a0) -; RV64I-NEXT: lbu t1, 2(a0) -; RV64I-NEXT: or a4, t0, a4 -; RV64I-NEXT: slli a5, a5, 8 -; RV64I-NEXT: or a5, a5, a7 -; RV64I-NEXT: slli t1, t1, 16 -; RV64I-NEXT: lbu a7, 5(a0) -; RV64I-NEXT: lbu t0, 3(a0) -; RV64I-NEXT: or a5, t1, a5 -; RV64I-NEXT: lbu t1, 4(a0) -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: or t0, t0, a4 +; RV64I-NEXT: slli t0, t0, 32 +; RV64I-NEXT: lbu a4, 1(a0) +; RV64I-NEXT: lbu a6, 0(a0) +; RV64I-NEXT: lbu a7, 2(a0) +; RV64I-NEXT: lbu t1, 3(a0) +; RV64I-NEXT: slli a4, a4, 8 +; RV64I-NEXT: or a4, a4, a6 +; RV64I-NEXT: slli a7, a7, 16 +; RV64I-NEXT: slli t1, t1, 24 +; RV64I-NEXT: or a4, a7, a4 +; RV64I-NEXT: lbu a6, 5(a0) +; RV64I-NEXT: lbu a7, 4(a0) ; RV64I-NEXT: lbu t2, 6(a0) ; RV64I-NEXT: lbu t3, 7(a0) -; RV64I-NEXT: or a7, a7, t1 -; RV64I-NEXT: slli t0, t0, 24 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: or a6, a6, a7 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or a7, t2, a7 -; RV64I-NEXT: or a7, t3, a7 -; RV64I-NEXT: slli a7, a7, 32 -; RV64I-NEXT: or a5, a7, a5 -; RV64I-NEXT: lbu a7, 9(a0) -; RV64I-NEXT: lbu t1, 8(a0) -; RV64I-NEXT: lbu t2, 10(a0) -; RV64I-NEXT: or a5, a5, t0 -; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a7, a7, t1 -; RV64I-NEXT: slli t2, t2, 16 -; RV64I-NEXT: lbu t0, 13(a0) -; RV64I-NEXT: lbu t1, 12(a0) -; RV64I-NEXT: or a7, t2, a7 +; RV64I-NEXT: or a6, t2, a6 +; RV64I-NEXT: or a6, t3, a6 +; RV64I-NEXT: slli a6, a6, 32 +; RV64I-NEXT: or a4, a6, a4 +; RV64I-NEXT: or a4, a4, t1 +; RV64I-NEXT: lbu a6, 9(a0) +; RV64I-NEXT: lbu a7, 8(a0) +; RV64I-NEXT: lbu t1, 10(a0) ; RV64I-NEXT: lbu t2, 11(a0) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t1 -; RV64I-NEXT: lbu t1, 14(a0) -; RV64I-NEXT: lbu t3, 15(a0) -; RV64I-NEXT: slli a0, a4, 32 -; RV64I-NEXT: slli t2, t2, 24 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: or a6, a6, a7 ; RV64I-NEXT: slli t1, t1, 16 -; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or a4, t1, t0 -; RV64I-NEXT: or a4, t3, a4 -; RV64I-NEXT: slli a4, a4, 32 -; RV64I-NEXT: or a4, a4, a7 -; RV64I-NEXT: or t1, a4, t2 -; RV64I-NEXT: lbu a4, 5(a1) -; RV64I-NEXT: lbu a7, 4(a1) -; RV64I-NEXT: lbu t0, 6(a1) +; RV64I-NEXT: slli t2, t2, 24 +; RV64I-NEXT: or a6, t1, a6 +; RV64I-NEXT: lbu a7, 13(a0) +; RV64I-NEXT: lbu t1, 12(a0) +; RV64I-NEXT: lbu t3, 14(a0) +; RV64I-NEXT: lbu a0, 15(a0) +; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: or a7, a7, t1 +; RV64I-NEXT: slli t3, t3, 16 +; RV64I-NEXT: slli a0, a0, 24 +; RV64I-NEXT: or a7, t3, a7 +; RV64I-NEXT: or a0, a0, a7 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: or t1, a0, t2 +; RV64I-NEXT: lbu a0, 5(a1) +; RV64I-NEXT: lbu a6, 4(a1) +; RV64I-NEXT: lbu a7, 6(a1) ; RV64I-NEXT: lbu t2, 7(a1) -; RV64I-NEXT: slli a4, a4, 8 -; RV64I-NEXT: or a4, a4, a7 -; RV64I-NEXT: slli t0, t0, 16 +; RV64I-NEXT: slli a0, a0, 8 +; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: slli a7, a7, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a4, t0, a4 -; RV64I-NEXT: or a4, t2, a4 -; RV64I-NEXT: lbu a7, 1(a1) -; RV64I-NEXT: lbu t0, 0(a1) +; RV64I-NEXT: or a0, a7, a0 +; RV64I-NEXT: or a0, t2, a0 +; RV64I-NEXT: lbu a6, 1(a1) +; RV64I-NEXT: lbu a7, 0(a1) ; RV64I-NEXT: lbu t2, 2(a1) ; RV64I-NEXT: lbu a1, 3(a1) -; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a7, a7, t0 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: or a6, a6, a7 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a7, t2, a7 -; RV64I-NEXT: or a1, a1, a7 +; RV64I-NEXT: or a6, t2, a6 +; RV64I-NEXT: or a1, a1, a6 ; RV64I-NEXT: slli a1, a1, 3 -; RV64I-NEXT: slli a4, a4, 35 -; RV64I-NEXT: or a1, a4, a1 -; RV64I-NEXT: sll a7, t1, a1 -; RV64I-NEXT: srli t0, a5, 1 -; RV64I-NEXT: addi t3, a1, -192 -; RV64I-NEXT: sll a4, a5, a1 -; RV64I-NEXT: bltz t3, .LBB10_2 +; RV64I-NEXT: slli a0, a0, 35 +; RV64I-NEXT: or a1, a0, a1 +; RV64I-NEXT: sll a0, t1, a1 +; RV64I-NEXT: not t4, a1 +; RV64I-NEXT: srli a6, a4, 1 +; RV64I-NEXT: srl a6, a6, t4 +; RV64I-NEXT: or a6, a0, a6 +; RV64I-NEXT: addi t2, a1, -192 +; RV64I-NEXT: sll a7, a4, a1 +; RV64I-NEXT: mv t3, a6 +; RV64I-NEXT: bltz t2, .LBB10_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv t5, a4 -; RV64I-NEXT: j .LBB10_3 +; RV64I-NEXT: mv t3, a7 ; RV64I-NEXT: .LBB10_2: -; RV64I-NEXT: addiw t2, a1, -128 -; RV64I-NEXT: xori t2, t2, 63 -; RV64I-NEXT: srl t2, t0, t2 -; RV64I-NEXT: or t5, a7, t2 -; RV64I-NEXT: .LBB10_3: -; RV64I-NEXT: or a0, a0, a6 -; RV64I-NEXT: xori a6, a1, 63 -; RV64I-NEXT: addi t2, a1, -64 -; RV64I-NEXT: sll t4, a3, a1 -; RV64I-NEXT: bltz t2, .LBB10_5 -; RV64I-NEXT: # %bb.4: -; RV64I-NEXT: mv s3, t4 -; RV64I-NEXT: j .LBB10_6 +; RV64I-NEXT: or a0, t0, a5 +; RV64I-NEXT: addi a5, a1, -64 +; RV64I-NEXT: sll t0, a3, a1 +; RV64I-NEXT: bltz a5, .LBB10_4 +; RV64I-NEXT: # %bb.3: +; RV64I-NEXT: mv s1, t0 +; RV64I-NEXT: j .LBB10_5 +; RV64I-NEXT: .LBB10_4: +; RV64I-NEXT: sll t5, a0, a1 +; RV64I-NEXT: srli t6, a3, 1 +; RV64I-NEXT: srl t4, t6, t4 +; RV64I-NEXT: or s1, t5, t4 ; RV64I-NEXT: .LBB10_5: -; RV64I-NEXT: sll t6, a0, a1 -; RV64I-NEXT: srli s0, a3, 1 -; RV64I-NEXT: srl s0, s0, a6 -; RV64I-NEXT: or s3, t6, s0 -; RV64I-NEXT: .LBB10_6: -; RV64I-NEXT: negw s1, a1 -; RV64I-NEXT: srl t6, t1, s1 -; RV64I-NEXT: li s2, 64 -; RV64I-NEXT: li s0, 128 -; RV64I-NEXT: sub s2, s2, a1 -; RV64I-NEXT: bltu a1, s0, .LBB10_12 -; RV64I-NEXT: # %bb.7: -; RV64I-NEXT: bnez a1, .LBB10_13 +; RV64I-NEXT: negw t6, a1 +; RV64I-NEXT: srl t4, t1, t6 +; RV64I-NEXT: li s0, 64 +; RV64I-NEXT: li t5, 128 +; RV64I-NEXT: sub s0, s0, a1 +; RV64I-NEXT: bltu a1, t5, .LBB10_11 +; RV64I-NEXT: # %bb.6: +; RV64I-NEXT: bnez a1, .LBB10_12 +; RV64I-NEXT: .LBB10_7: +; RV64I-NEXT: bgez s0, .LBB10_9 ; RV64I-NEXT: .LBB10_8: -; RV64I-NEXT: bgez s2, .LBB10_10 -; RV64I-NEXT: .LBB10_9: -; RV64I-NEXT: srl a5, a5, s1 +; RV64I-NEXT: srl a4, a4, t6 ; RV64I-NEXT: slli t1, t1, 1 -; RV64I-NEXT: subw t5, s0, a1 -; RV64I-NEXT: xori t5, t5, 63 -; RV64I-NEXT: sll t1, t1, t5 -; RV64I-NEXT: or t6, a5, t1 -; RV64I-NEXT: .LBB10_10: -; RV64I-NEXT: slti a5, t2, 0 -; RV64I-NEXT: neg a5, a5 -; RV64I-NEXT: bltu a1, s0, .LBB10_14 -; RV64I-NEXT: # %bb.11: -; RV64I-NEXT: slti t1, t3, 0 -; RV64I-NEXT: neg t1, t1 -; RV64I-NEXT: and t1, t1, a4 -; RV64I-NEXT: bnez a1, .LBB10_15 -; RV64I-NEXT: j .LBB10_16 +; RV64I-NEXT: subw t3, t5, a1 +; RV64I-NEXT: not t3, t3 +; RV64I-NEXT: sll t1, t1, t3 +; RV64I-NEXT: or t4, a4, t1 +; RV64I-NEXT: .LBB10_9: +; RV64I-NEXT: slti a4, a5, 0 +; RV64I-NEXT: neg a4, a4 +; RV64I-NEXT: bltu a1, t5, .LBB10_13 +; RV64I-NEXT: # %bb.10: +; RV64I-NEXT: slti t0, t2, 0 +; RV64I-NEXT: neg t0, t0 +; RV64I-NEXT: and t0, t0, a7 +; RV64I-NEXT: bnez a1, .LBB10_14 +; RV64I-NEXT: j .LBB10_15 +; RV64I-NEXT: .LBB10_11: +; RV64I-NEXT: slti t3, s0, 0 +; RV64I-NEXT: neg t3, t3 +; RV64I-NEXT: and t3, t3, t4 +; RV64I-NEXT: or t3, s1, t3 +; RV64I-NEXT: beqz a1, .LBB10_7 ; RV64I-NEXT: .LBB10_12: -; RV64I-NEXT: slti t5, s2, 0 -; RV64I-NEXT: neg t5, t5 -; RV64I-NEXT: and t5, t5, t6 -; RV64I-NEXT: or t5, s3, t5 -; RV64I-NEXT: beqz a1, .LBB10_8 +; RV64I-NEXT: mv a0, t3 +; RV64I-NEXT: bltz s0, .LBB10_8 +; RV64I-NEXT: j .LBB10_9 ; RV64I-NEXT: .LBB10_13: -; RV64I-NEXT: mv a0, t5 -; RV64I-NEXT: bltz s2, .LBB10_9 -; RV64I-NEXT: j .LBB10_10 +; RV64I-NEXT: and t0, a4, t0 +; RV64I-NEXT: or t0, t0, t4 +; RV64I-NEXT: beqz a1, .LBB10_15 ; RV64I-NEXT: .LBB10_14: -; RV64I-NEXT: and t1, a5, t4 -; RV64I-NEXT: or t1, t1, t6 -; RV64I-NEXT: beqz a1, .LBB10_16 +; RV64I-NEXT: mv a3, t0 ; RV64I-NEXT: .LBB10_15: -; RV64I-NEXT: mv a3, t1 -; RV64I-NEXT: .LBB10_16: -; RV64I-NEXT: bltz t2, .LBB10_18 -; RV64I-NEXT: # %bb.17: -; RV64I-NEXT: mv a6, a4 -; RV64I-NEXT: j .LBB10_19 -; RV64I-NEXT: .LBB10_18: -; RV64I-NEXT: srl a6, t0, a6 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: .LBB10_19: +; RV64I-NEXT: bltz a5, .LBB10_17 +; RV64I-NEXT: # %bb.16: +; RV64I-NEXT: mv a6, a7 +; RV64I-NEXT: .LBB10_17: ; RV64I-NEXT: sltiu a1, a1, 128 ; RV64I-NEXT: neg a1, a1 -; RV64I-NEXT: and a6, a1, a6 -; RV64I-NEXT: and a4, a5, a4 +; RV64I-NEXT: and a5, a1, a6 +; RV64I-NEXT: and a4, a4, a7 ; RV64I-NEXT: and a1, a1, a4 ; RV64I-NEXT: sb a1, 0(a2) -; RV64I-NEXT: sb a6, 8(a2) +; RV64I-NEXT: sb a5, 8(a2) ; RV64I-NEXT: srli a4, a1, 56 ; RV64I-NEXT: sb a4, 7(a2) ; RV64I-NEXT: srli a4, a1, 48 @@ -2605,20 +2532,20 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: sb a4, 2(a2) ; RV64I-NEXT: srli a1, a1, 8 ; RV64I-NEXT: sb a1, 1(a2) -; RV64I-NEXT: srli a1, a6, 56 +; RV64I-NEXT: srli a1, a5, 56 ; RV64I-NEXT: sb a1, 15(a2) -; RV64I-NEXT: srli a1, a6, 48 +; RV64I-NEXT: srli a1, a5, 48 ; RV64I-NEXT: sb a1, 14(a2) -; RV64I-NEXT: srli a1, a6, 40 +; RV64I-NEXT: srli a1, a5, 40 ; RV64I-NEXT: sb a1, 13(a2) -; RV64I-NEXT: srli a1, a6, 32 +; RV64I-NEXT: srli a1, a5, 32 ; RV64I-NEXT: sb a1, 12(a2) -; RV64I-NEXT: srli a1, a6, 24 +; RV64I-NEXT: srli a1, a5, 24 ; RV64I-NEXT: sb a1, 11(a2) -; RV64I-NEXT: srli a1, a6, 16 +; RV64I-NEXT: srli a1, a5, 16 ; RV64I-NEXT: sb a1, 10(a2) -; RV64I-NEXT: srli a1, a6, 8 -; RV64I-NEXT: sb a1, 9(a2) +; RV64I-NEXT: srli a5, a5, 8 +; RV64I-NEXT: sb a5, 9(a2) ; RV64I-NEXT: sb a0, 24(a2) ; RV64I-NEXT: sb a3, 16(a2) ; RV64I-NEXT: srli a1, a0, 56 @@ -2649,528 +2576,495 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: sb a0, 18(a2) ; RV64I-NEXT: srli a3, a3, 8 ; RV64I-NEXT: sb a3, 17(a2) -; RV64I-NEXT: ld s0, 24(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s1, 16(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s2, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s3, 0(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 32 +; RV64I-NEXT: ld s0, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s1, 0(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; ; RV32I-LABEL: shl_32bytes: ; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -144 -; RV32I-NEXT: sw ra, 140(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 136(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 132(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 128(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 124(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s4, 120(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s5, 116(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s6, 112(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s7, 108(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s8, 104(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s9, 100(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s10, 96(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s11, 92(sp) # 4-byte Folded Spill -; RV32I-NEXT: lbu a5, 24(a0) -; RV32I-NEXT: lbu t3, 25(a0) -; RV32I-NEXT: lbu t6, 26(a0) -; RV32I-NEXT: lbu s0, 27(a0) -; RV32I-NEXT: lbu a7, 28(a0) -; RV32I-NEXT: lbu t0, 29(a0) -; RV32I-NEXT: lbu t1, 30(a0) -; RV32I-NEXT: lbu t5, 31(a0) -; RV32I-NEXT: lbu s1, 16(a0) -; RV32I-NEXT: lbu t2, 17(a0) -; RV32I-NEXT: lbu t4, 18(a0) -; RV32I-NEXT: lbu s2, 19(a0) -; RV32I-NEXT: lbu a4, 20(a0) -; RV32I-NEXT: lbu s3, 21(a0) -; RV32I-NEXT: lbu s4, 22(a0) +; RV32I-NEXT: addi sp, sp, -128 +; RV32I-NEXT: sw ra, 124(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 120(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 116(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 112(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s3, 108(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s4, 104(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s5, 100(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s6, 96(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s7, 92(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s8, 88(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s9, 84(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s10, 80(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s11, 76(sp) # 4-byte Folded Spill +; RV32I-NEXT: lbu a7, 24(a0) +; RV32I-NEXT: lbu a4, 25(a0) +; RV32I-NEXT: lbu t2, 26(a0) +; RV32I-NEXT: lbu t5, 27(a0) +; RV32I-NEXT: lbu a6, 28(a0) +; RV32I-NEXT: lbu t1, 29(a0) +; RV32I-NEXT: lbu t3, 30(a0) +; RV32I-NEXT: lbu t4, 31(a0) +; RV32I-NEXT: lbu t6, 16(a0) +; RV32I-NEXT: lbu t0, 17(a0) +; RV32I-NEXT: lbu s1, 18(a0) +; RV32I-NEXT: lbu s3, 19(a0) +; RV32I-NEXT: lbu s0, 20(a0) +; RV32I-NEXT: lbu s5, 21(a0) +; RV32I-NEXT: lbu s6, 22(a0) ; RV32I-NEXT: lbu s7, 23(a0) ; RV32I-NEXT: lbu a3, 9(a0) -; RV32I-NEXT: lbu a6, 8(a0) -; RV32I-NEXT: lbu s5, 10(a0) -; RV32I-NEXT: lbu s6, 11(a0) +; RV32I-NEXT: lbu a5, 8(a0) +; RV32I-NEXT: lbu s2, 10(a0) +; RV32I-NEXT: lbu s4, 11(a0) ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a3, a6 -; RV32I-NEXT: slli s5, s5, 16 -; RV32I-NEXT: slli s6, s6, 24 -; RV32I-NEXT: or a3, s5, a3 -; RV32I-NEXT: or a3, s6, a3 -; RV32I-NEXT: lbu a6, 13(a0) -; RV32I-NEXT: lbu s5, 12(a0) -; RV32I-NEXT: lbu s6, 14(a0) +; RV32I-NEXT: or a3, a3, a5 +; RV32I-NEXT: slli s2, s2, 16 +; RV32I-NEXT: slli s4, s4, 24 +; RV32I-NEXT: or a3, s2, a3 +; RV32I-NEXT: or a3, s4, a3 +; RV32I-NEXT: lbu a5, 13(a0) +; RV32I-NEXT: lbu s2, 12(a0) +; RV32I-NEXT: lbu s4, 14(a0) ; RV32I-NEXT: lbu s8, 15(a0) -; RV32I-NEXT: slli a6, a6, 8 -; RV32I-NEXT: or a6, a6, s5 -; RV32I-NEXT: slli s6, s6, 16 +; RV32I-NEXT: slli a5, a5, 8 +; RV32I-NEXT: or a5, a5, s2 +; RV32I-NEXT: slli s4, s4, 16 ; RV32I-NEXT: slli s8, s8, 24 -; RV32I-NEXT: or a6, s6, a6 -; RV32I-NEXT: or a6, s8, a6 -; RV32I-NEXT: sw a6, 88(sp) # 4-byte Folded Spill -; RV32I-NEXT: lbu a6, 1(a0) -; RV32I-NEXT: lbu s5, 0(a0) -; RV32I-NEXT: lbu s6, 2(a0) +; RV32I-NEXT: or a5, s4, a5 +; RV32I-NEXT: or a5, s8, a5 +; RV32I-NEXT: sw a5, 72(sp) # 4-byte Folded Spill +; RV32I-NEXT: lbu a5, 1(a0) +; RV32I-NEXT: lbu s2, 0(a0) +; RV32I-NEXT: lbu s4, 2(a0) ; RV32I-NEXT: lbu s8, 3(a0) -; RV32I-NEXT: slli a6, a6, 8 -; RV32I-NEXT: or a6, a6, s5 -; RV32I-NEXT: slli s6, s6, 16 +; RV32I-NEXT: slli a5, a5, 8 +; RV32I-NEXT: or a5, a5, s2 +; RV32I-NEXT: slli s4, s4, 16 ; RV32I-NEXT: slli s8, s8, 24 -; RV32I-NEXT: or a6, s6, a6 -; RV32I-NEXT: or s6, s8, a6 -; RV32I-NEXT: lbu a6, 5(a0) -; RV32I-NEXT: lbu s5, 4(a0) +; RV32I-NEXT: or a5, s4, a5 +; RV32I-NEXT: or s4, s8, a5 +; RV32I-NEXT: lbu a5, 5(a0) +; RV32I-NEXT: lbu s2, 4(a0) ; RV32I-NEXT: lbu s8, 6(a0) ; RV32I-NEXT: lbu a0, 7(a0) -; RV32I-NEXT: slli a6, a6, 8 -; RV32I-NEXT: or a6, a6, s5 +; RV32I-NEXT: slli a5, a5, 8 +; RV32I-NEXT: or a5, a5, s2 ; RV32I-NEXT: slli s8, s8, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a6, s8, a6 -; RV32I-NEXT: or s10, a0, a6 +; RV32I-NEXT: or a5, s8, a5 +; RV32I-NEXT: or s8, a0, a5 ; RV32I-NEXT: lbu a0, 1(a1) -; RV32I-NEXT: lbu a6, 0(a1) -; RV32I-NEXT: lbu s5, 2(a1) +; RV32I-NEXT: lbu a5, 0(a1) +; RV32I-NEXT: lbu s2, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a0, a0, 8 -; RV32I-NEXT: or a0, a0, a6 -; RV32I-NEXT: slli s5, s5, 16 +; RV32I-NEXT: or a0, a0, a5 +; RV32I-NEXT: slli s2, s2, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a0, s5, a0 +; RV32I-NEXT: or a0, s2, a0 ; RV32I-NEXT: or a0, a1, a0 -; RV32I-NEXT: slli a6, a0, 3 -; RV32I-NEXT: sll s5, s10, a6 -; RV32I-NEXT: srli s8, s6, 1 -; RV32I-NEXT: addi a0, a6, -224 -; RV32I-NEXT: sw s6, 80(sp) # 4-byte Folded Spill -; RV32I-NEXT: sll a1, s6, a6 -; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a1, 76(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s5, 72(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s8, 68(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgez a0, .LBB10_2 +; RV32I-NEXT: slli a5, a0, 3 +; RV32I-NEXT: sll a1, s8, a5 +; RV32I-NEXT: srli s2, s4, 1 +; RV32I-NEXT: not a0, a5 +; RV32I-NEXT: srl s2, s2, a0 +; RV32I-NEXT: or s10, a1, s2 +; RV32I-NEXT: addi s2, a5, -224 +; RV32I-NEXT: sw s4, 56(sp) # 4-byte Folded Spill +; RV32I-NEXT: sll a1, s4, a5 +; RV32I-NEXT: sw s10, 64(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz s2, .LBB10_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: addi a0, a6, -192 -; RV32I-NEXT: xori a0, a0, 31 -; RV32I-NEXT: srl a0, s8, a0 -; RV32I-NEXT: or a1, s5, a0 +; RV32I-NEXT: mv s10, a1 ; RV32I-NEXT: .LBB10_2: -; RV32I-NEXT: slli s5, t2, 8 -; RV32I-NEXT: slli s8, t4, 16 -; RV32I-NEXT: slli s9, s2, 24 -; RV32I-NEXT: slli s11, s3, 8 -; RV32I-NEXT: slli s4, s4, 16 -; RV32I-NEXT: slli ra, s7, 24 -; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll s3, a0, a6 -; RV32I-NEXT: srli a0, a3, 1 -; RV32I-NEXT: addi s2, a6, -128 -; RV32I-NEXT: xori t2, s2, 31 -; RV32I-NEXT: addi t4, a6, -160 -; RV32I-NEXT: sll s7, a3, a6 -; RV32I-NEXT: sw s7, 60(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a0, 56(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgez t4, .LBB10_4 +; RV32I-NEXT: sw a1, 52(sp) # 4-byte Folded Spill +; RV32I-NEXT: slli s2, t0, 8 +; RV32I-NEXT: slli s11, s1, 16 +; RV32I-NEXT: slli s3, s3, 24 +; RV32I-NEXT: slli ra, s5, 8 +; RV32I-NEXT: slli s6, s6, 16 +; RV32I-NEXT: slli s7, s7, 24 +; RV32I-NEXT: lw a1, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: sll a1, a1, a5 +; RV32I-NEXT: srli t0, a3, 1 +; RV32I-NEXT: srl s1, t0, a0 +; RV32I-NEXT: or s5, a1, s1 +; RV32I-NEXT: addi s9, a5, -160 +; RV32I-NEXT: sll a1, a3, a5 +; RV32I-NEXT: sw s5, 44(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz s9, .LBB10_4 ; RV32I-NEXT: # %bb.3: -; RV32I-NEXT: srl a0, a0, t2 -; RV32I-NEXT: or s7, s3, a0 +; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: .LBB10_4: -; RV32I-NEXT: slli a0, t3, 8 -; RV32I-NEXT: slli t6, t6, 16 -; RV32I-NEXT: slli s0, s0, 24 -; RV32I-NEXT: or s1, s5, s1 -; RV32I-NEXT: or s3, s9, s8 -; RV32I-NEXT: or a4, s11, a4 -; RV32I-NEXT: or s4, ra, s4 -; RV32I-NEXT: neg s11, a6 -; RV32I-NEXT: srl s8, s10, s11 -; RV32I-NEXT: li s5, 160 -; RV32I-NEXT: li s6, 64 -; RV32I-NEXT: sub s5, s5, a6 -; RV32I-NEXT: sw s5, 40(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgeu s2, s6, .LBB10_6 +; RV32I-NEXT: sw a1, 48(sp) # 4-byte Folded Spill +; RV32I-NEXT: slli a4, a4, 8 +; RV32I-NEXT: slli a1, t2, 16 +; RV32I-NEXT: slli t5, t5, 24 +; RV32I-NEXT: or s1, s2, t6 +; RV32I-NEXT: or s2, s3, s11 +; RV32I-NEXT: or s0, ra, s0 +; RV32I-NEXT: or s3, s7, s6 +; RV32I-NEXT: neg s6, a5 +; RV32I-NEXT: srl ra, s8, s6 +; RV32I-NEXT: li s7, 160 +; RV32I-NEXT: addi t6, a5, -128 +; RV32I-NEXT: li t2, 64 +; RV32I-NEXT: sub s7, s7, a5 +; RV32I-NEXT: sw s7, 36(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgeu t6, t2, .LBB10_6 ; RV32I-NEXT: # %bb.5: -; RV32I-NEXT: slti a1, s5, 0 -; RV32I-NEXT: neg a1, a1 -; RV32I-NEXT: and a1, a1, s8 -; RV32I-NEXT: or a1, s7, a1 +; RV32I-NEXT: slti s7, s7, 0 +; RV32I-NEXT: neg s7, s7 +; RV32I-NEXT: and s7, s7, ra +; RV32I-NEXT: or s10, s5, s7 ; RV32I-NEXT: .LBB10_6: -; RV32I-NEXT: slli t0, t0, 8 -; RV32I-NEXT: slli t1, t1, 16 -; RV32I-NEXT: slli s5, t5, 24 -; RV32I-NEXT: or t5, a0, a5 -; RV32I-NEXT: or t6, s0, t6 -; RV32I-NEXT: or a5, s3, s1 -; RV32I-NEXT: or s7, s4, a4 -; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: beqz s2, .LBB10_8 +; RV32I-NEXT: slli t1, t1, 8 +; RV32I-NEXT: slli t3, t3, 16 +; RV32I-NEXT: slli t4, t4, 24 +; RV32I-NEXT: or a4, a4, a7 +; RV32I-NEXT: or s5, t5, a1 +; RV32I-NEXT: or t5, s2, s1 +; RV32I-NEXT: or s3, s3, s0 +; RV32I-NEXT: lw s2, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: mv a1, s2 +; RV32I-NEXT: beqz t6, .LBB10_8 ; RV32I-NEXT: # %bb.7: -; RV32I-NEXT: mv a0, a1 +; RV32I-NEXT: mv a1, s10 ; RV32I-NEXT: .LBB10_8: -; RV32I-NEXT: or a1, t0, a7 -; RV32I-NEXT: or t0, s5, t1 -; RV32I-NEXT: or a7, t6, t5 -; RV32I-NEXT: sll t5, s7, a6 -; RV32I-NEXT: srli s1, a5, 1 -; RV32I-NEXT: addi a4, a6, -64 -; RV32I-NEXT: xori a4, a4, 31 -; RV32I-NEXT: addi t1, a6, -96 -; RV32I-NEXT: sll t6, a5, a6 -; RV32I-NEXT: sw t1, 48(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a4, 20(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz t1, .LBB10_10 +; RV32I-NEXT: or a7, t1, a6 +; RV32I-NEXT: or t3, t4, t3 +; RV32I-NEXT: or a6, s5, a4 +; RV32I-NEXT: sll a4, s3, a5 +; RV32I-NEXT: srli t1, t5, 1 +; RV32I-NEXT: srl t1, t1, a0 +; RV32I-NEXT: or t1, a4, t1 +; RV32I-NEXT: addi t4, a5, -96 +; RV32I-NEXT: sll a4, t5, a5 +; RV32I-NEXT: sw a4, 60(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv a4, t1 +; RV32I-NEXT: sw t4, 40(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz t4, .LBB10_10 ; RV32I-NEXT: # %bb.9: -; RV32I-NEXT: mv a4, t6 -; RV32I-NEXT: j .LBB10_11 +; RV32I-NEXT: lw a4, 60(sp) # 4-byte Folded Reload ; RV32I-NEXT: .LBB10_10: -; RV32I-NEXT: srl a4, s1, a4 -; RV32I-NEXT: or a4, t5, a4 -; RV32I-NEXT: .LBB10_11: -; RV32I-NEXT: or t1, t0, a1 -; RV32I-NEXT: xori ra, a6, 31 -; RV32I-NEXT: addi s0, a6, -32 -; RV32I-NEXT: sll t0, a7, a6 -; RV32I-NEXT: sw t6, 64(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw t0, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgez s0, .LBB10_13 -; RV32I-NEXT: # %bb.12: -; RV32I-NEXT: sll a1, t1, a6 -; RV32I-NEXT: srli t0, a7, 1 -; RV32I-NEXT: srl t0, t0, ra -; RV32I-NEXT: or t0, a1, t0 -; RV32I-NEXT: .LBB10_13: -; RV32I-NEXT: srl s4, s7, s11 -; RV32I-NEXT: li a1, 32 -; RV32I-NEXT: sub s3, a1, a6 -; RV32I-NEXT: slti t6, s3, 0 -; RV32I-NEXT: neg t6, t6 -; RV32I-NEXT: bgeu a6, s6, .LBB10_15 -; RV32I-NEXT: # %bb.14: -; RV32I-NEXT: and a4, t6, s4 -; RV32I-NEXT: or a4, t0, a4 -; RV32I-NEXT: .LBB10_15: -; RV32I-NEXT: sw s4, 36(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw t6, 44(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s8, 84(sp) # 4-byte Folded Spill -; RV32I-NEXT: mv t0, t1 -; RV32I-NEXT: beqz a6, .LBB10_17 -; RV32I-NEXT: # %bb.16: -; RV32I-NEXT: mv t0, a4 -; RV32I-NEXT: .LBB10_17: -; RV32I-NEXT: lw a4, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl t3, a4, s11 +; RV32I-NEXT: or a7, t3, a7 +; RV32I-NEXT: addi s4, a5, -32 +; RV32I-NEXT: sll t3, a6, a5 +; RV32I-NEXT: sw t3, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgez s4, .LBB10_12 +; RV32I-NEXT: # %bb.11: +; RV32I-NEXT: sll t3, a7, a5 +; RV32I-NEXT: srli s0, a6, 1 +; RV32I-NEXT: srl a0, s0, a0 +; RV32I-NEXT: or t3, t3, a0 +; RV32I-NEXT: .LBB10_12: +; RV32I-NEXT: srl s5, s3, s6 +; RV32I-NEXT: li a0, 32 +; RV32I-NEXT: sub s0, a0, a5 +; RV32I-NEXT: sw s0, 68(sp) # 4-byte Folded Spill +; RV32I-NEXT: slti s1, s0, 0 +; RV32I-NEXT: neg s7, s1 +; RV32I-NEXT: bgeu a5, t2, .LBB10_14 +; RV32I-NEXT: # %bb.13: +; RV32I-NEXT: and a4, s7, s5 +; RV32I-NEXT: or a4, t3, a4 +; RV32I-NEXT: .LBB10_14: +; RV32I-NEXT: sw s5, 28(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv t3, a7 +; RV32I-NEXT: beqz a5, .LBB10_16 +; RV32I-NEXT: # %bb.15: +; RV32I-NEXT: mv t3, a4 +; RV32I-NEXT: .LBB10_16: +; RV32I-NEXT: srl s10, s2, s6 ; RV32I-NEXT: li a4, 96 -; RV32I-NEXT: sub s8, a4, a6 -; RV32I-NEXT: slti a4, s8, 0 +; RV32I-NEXT: sub s5, a4, a5 +; RV32I-NEXT: slti a4, s5, 0 ; RV32I-NEXT: neg a4, a4 -; RV32I-NEXT: li s9, 128 -; RV32I-NEXT: sub t6, s9, a6 -; RV32I-NEXT: sltiu s5, t6, 64 -; RV32I-NEXT: neg s5, s5 -; RV32I-NEXT: bgeu a6, s9, .LBB10_19 -; RV32I-NEXT: # %bb.18: -; RV32I-NEXT: and a0, a4, t3 -; RV32I-NEXT: and a0, s5, a0 -; RV32I-NEXT: or a0, t0, a0 -; RV32I-NEXT: .LBB10_19: -; RV32I-NEXT: beqz a6, .LBB10_21 -; RV32I-NEXT: # %bb.20: -; RV32I-NEXT: mv t1, a0 -; RV32I-NEXT: .LBB10_21: -; RV32I-NEXT: neg t0, t6 -; RV32I-NEXT: sub s9, a1, t6 -; RV32I-NEXT: sll a0, a3, t0 -; RV32I-NEXT: sw s5, 16(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz s9, .LBB10_24 -; RV32I-NEXT: # %bb.22: -; RV32I-NEXT: mv a1, a0 -; RV32I-NEXT: bgeu t6, s6, .LBB10_25 +; RV32I-NEXT: li t2, 128 +; RV32I-NEXT: sub s11, t2, a5 +; RV32I-NEXT: sltiu s1, s11, 64 +; RV32I-NEXT: neg s1, s1 +; RV32I-NEXT: bgeu a5, t2, .LBB10_18 +; RV32I-NEXT: # %bb.17: +; RV32I-NEXT: and a1, a4, s10 +; RV32I-NEXT: and a1, s1, a1 +; RV32I-NEXT: or a1, t3, a1 +; RV32I-NEXT: .LBB10_18: +; RV32I-NEXT: li t2, 64 +; RV32I-NEXT: sw s1, 32(sp) # 4-byte Folded Spill +; RV32I-NEXT: beqz a5, .LBB10_20 +; RV32I-NEXT: # %bb.19: +; RV32I-NEXT: mv a7, a1 +; RV32I-NEXT: .LBB10_20: +; RV32I-NEXT: neg s1, s11 +; RV32I-NEXT: sub t3, a0, s11 +; RV32I-NEXT: sll a1, a3, s1 +; RV32I-NEXT: bltz t3, .LBB10_23 +; RV32I-NEXT: # %bb.21: +; RV32I-NEXT: mv a0, a1 +; RV32I-NEXT: bgeu s11, t2, .LBB10_24 +; RV32I-NEXT: .LBB10_22: +; RV32I-NEXT: and a4, a4, ra +; RV32I-NEXT: or a4, a4, a0 +; RV32I-NEXT: mv a0, s8 +; RV32I-NEXT: bnez s11, .LBB10_25 +; RV32I-NEXT: j .LBB10_26 ; RV32I-NEXT: .LBB10_23: -; RV32I-NEXT: lw t0, 84(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a4, t0 -; RV32I-NEXT: or a4, a4, a1 -; RV32I-NEXT: mv a1, s10 -; RV32I-NEXT: bnez t6, .LBB10_26 -; RV32I-NEXT: j .LBB10_27 +; RV32I-NEXT: sll a0, s2, s1 +; RV32I-NEXT: sub s1, t2, s11 +; RV32I-NEXT: not s1, s1 +; RV32I-NEXT: srl t0, t0, s1 +; RV32I-NEXT: or a0, a0, t0 +; RV32I-NEXT: bltu s11, t2, .LBB10_22 ; RV32I-NEXT: .LBB10_24: -; RV32I-NEXT: lw a1, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a1, a1, t0 -; RV32I-NEXT: sub t0, s6, t6 -; RV32I-NEXT: xori t0, t0, 31 -; RV32I-NEXT: lw s5, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl t0, s5, t0 -; RV32I-NEXT: or a1, a1, t0 -; RV32I-NEXT: bltu t6, s6, .LBB10_23 +; RV32I-NEXT: and a4, s7, s10 +; RV32I-NEXT: mv a0, s8 +; RV32I-NEXT: beqz s11, .LBB10_26 ; RV32I-NEXT: .LBB10_25: -; RV32I-NEXT: lw a1, 44(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a1, t3 -; RV32I-NEXT: mv a1, s10 -; RV32I-NEXT: beqz t6, .LBB10_27 +; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: .LBB10_26: -; RV32I-NEXT: mv a1, a4 -; RV32I-NEXT: .LBB10_27: -; RV32I-NEXT: bltz s0, .LBB10_29 -; RV32I-NEXT: # %bb.28: +; RV32I-NEXT: bltz s4, .LBB10_28 +; RV32I-NEXT: # %bb.27: +; RV32I-NEXT: lw t1, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: .LBB10_28: +; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sltiu t0, a5, 64 ; RV32I-NEXT: lw a4, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: j .LBB10_30 -; RV32I-NEXT: .LBB10_29: -; RV32I-NEXT: srl a4, s1, ra -; RV32I-NEXT: or a4, t5, a4 +; RV32I-NEXT: mv s0, s9 +; RV32I-NEXT: bltz s9, .LBB10_30 +; RV32I-NEXT: # %bb.29: +; RV32I-NEXT: lw a4, 52(sp) # 4-byte Folded Reload ; RV32I-NEXT: .LBB10_30: -; RV32I-NEXT: sltiu t0, a6, 64 -; RV32I-NEXT: sw ra, 52(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz t4, .LBB10_32 +; RV32I-NEXT: neg s9, t0 +; RV32I-NEXT: sltiu t0, t6, 64 +; RV32I-NEXT: neg s1, t0 +; RV32I-NEXT: li t0, 128 +; RV32I-NEXT: bltu a5, t0, .LBB10_32 ; RV32I-NEXT: # %bb.31: -; RV32I-NEXT: lw t2, 76(sp) # 4-byte Folded Reload -; RV32I-NEXT: j .LBB10_33 +; RV32I-NEXT: and a4, s1, a4 +; RV32I-NEXT: mv t0, s3 +; RV32I-NEXT: bnez a5, .LBB10_33 +; RV32I-NEXT: j .LBB10_34 ; RV32I-NEXT: .LBB10_32: -; RV32I-NEXT: lw t5, 68(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl t2, t5, t2 -; RV32I-NEXT: lw t5, 72(sp) # 4-byte Folded Reload -; RV32I-NEXT: or t2, t5, t2 +; RV32I-NEXT: and a4, s9, t1 +; RV32I-NEXT: or a4, a4, a0 +; RV32I-NEXT: mv t0, s3 +; RV32I-NEXT: beqz a5, .LBB10_34 ; RV32I-NEXT: .LBB10_33: -; RV32I-NEXT: neg ra, t0 -; RV32I-NEXT: sltiu t0, s2, 64 -; RV32I-NEXT: neg t0, t0 -; RV32I-NEXT: li t5, 128 -; RV32I-NEXT: bltu a6, t5, .LBB10_35 -; RV32I-NEXT: # %bb.34: -; RV32I-NEXT: and a1, t0, t2 -; RV32I-NEXT: mv s1, s7 -; RV32I-NEXT: bnez a6, .LBB10_36 +; RV32I-NEXT: mv t0, a4 +; RV32I-NEXT: .LBB10_34: +; RV32I-NEXT: srl t1, a3, s6 +; RV32I-NEXT: slli a4, s2, 1 +; RV32I-NEXT: sub a0, t2, a5 +; RV32I-NEXT: not a0, a0 +; RV32I-NEXT: lw s2, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s10, 20(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz s2, .LBB10_36 +; RV32I-NEXT: # %bb.35: +; RV32I-NEXT: mv s2, s10 ; RV32I-NEXT: j .LBB10_37 -; RV32I-NEXT: .LBB10_35: -; RV32I-NEXT: and a4, ra, a4 -; RV32I-NEXT: or a1, a4, a1 -; RV32I-NEXT: mv s1, s7 -; RV32I-NEXT: beqz a6, .LBB10_37 ; RV32I-NEXT: .LBB10_36: -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: sll a0, a4, a0 +; RV32I-NEXT: or s2, t1, a0 ; RV32I-NEXT: .LBB10_37: -; RV32I-NEXT: srl a1, a3, s11 -; RV32I-NEXT: lw a4, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: slli a4, a4, 1 -; RV32I-NEXT: sub t2, s6, a6 -; RV32I-NEXT: xori t2, t2, 31 -; RV32I-NEXT: sw t2, 32(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a1, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz s3, .LBB10_39 +; RV32I-NEXT: lw a0, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: srl s10, a0, s6 +; RV32I-NEXT: slli s8, s8, 1 +; RV32I-NEXT: not a0, s11 +; RV32I-NEXT: bltz s5, .LBB10_39 ; RV32I-NEXT: # %bb.38: -; RV32I-NEXT: mv s4, t3 -; RV32I-NEXT: mv s5, t3 -; RV32I-NEXT: j .LBB10_40 +; RV32I-NEXT: mv t4, s8 +; RV32I-NEXT: mv s7, s10 +; RV32I-NEXT: mv s8, ra +; RV32I-NEXT: bltu s11, t2, .LBB10_40 +; RV32I-NEXT: j .LBB10_41 ; RV32I-NEXT: .LBB10_39: -; RV32I-NEXT: mv s4, t3 -; RV32I-NEXT: sll t2, a4, t2 -; RV32I-NEXT: or s5, a1, t2 +; RV32I-NEXT: mv t4, s8 +; RV32I-NEXT: sll s8, s8, a0 +; RV32I-NEXT: mv s7, s10 +; RV32I-NEXT: or s8, s10, s8 +; RV32I-NEXT: bgeu s11, t2, .LBB10_41 ; RV32I-NEXT: .LBB10_40: -; RV32I-NEXT: li s6, 64 -; RV32I-NEXT: lw t2, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl t2, t2, s11 -; RV32I-NEXT: slli s10, s10, 1 -; RV32I-NEXT: xori t5, t6, 31 -; RV32I-NEXT: bltz s8, .LBB10_42 -; RV32I-NEXT: # %bb.41: -; RV32I-NEXT: mv a1, s10 -; RV32I-NEXT: mv t3, t2 -; RV32I-NEXT: lw s10, 84(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltu t6, s6, .LBB10_43 -; RV32I-NEXT: j .LBB10_44 -; RV32I-NEXT: .LBB10_42: -; RV32I-NEXT: mv a1, s10 -; RV32I-NEXT: sll s10, s10, t5 -; RV32I-NEXT: mv t3, t2 -; RV32I-NEXT: or s10, t2, s10 -; RV32I-NEXT: bgeu t6, s6, .LBB10_44 +; RV32I-NEXT: slti t3, t3, 0 +; RV32I-NEXT: neg t3, t3 +; RV32I-NEXT: and a1, t3, a1 +; RV32I-NEXT: or s2, s8, a1 +; RV32I-NEXT: .LBB10_41: +; RV32I-NEXT: beqz s11, .LBB10_43 +; RV32I-NEXT: # %bb.42: +; RV32I-NEXT: sw s2, 56(sp) # 4-byte Folded Spill ; RV32I-NEXT: .LBB10_43: -; RV32I-NEXT: slti s5, s9, 0 -; RV32I-NEXT: neg s5, s5 -; RV32I-NEXT: and a0, s5, a0 -; RV32I-NEXT: or s5, s10, a0 -; RV32I-NEXT: .LBB10_44: -; RV32I-NEXT: lw s9, 76(sp) # 4-byte Folded Reload -; RV32I-NEXT: beqz t6, .LBB10_46 -; RV32I-NEXT: # %bb.45: -; RV32I-NEXT: sw s5, 80(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv s11, s4 +; RV32I-NEXT: slti a1, s4, 0 +; RV32I-NEXT: neg s8, a1 +; RV32I-NEXT: slti a1, s0, 0 +; RV32I-NEXT: neg a1, a1 +; RV32I-NEXT: li t3, 128 +; RV32I-NEXT: bltu a5, t3, .LBB10_45 +; RV32I-NEXT: # %bb.44: +; RV32I-NEXT: lw s4, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: and t3, a1, s4 +; RV32I-NEXT: and t3, s1, t3 +; RV32I-NEXT: mv s2, t5 +; RV32I-NEXT: bnez a5, .LBB10_46 +; RV32I-NEXT: j .LBB10_47 +; RV32I-NEXT: .LBB10_45: +; RV32I-NEXT: lw t3, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: and t3, s8, t3 +; RV32I-NEXT: and t3, s9, t3 +; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: or t3, t3, s0 +; RV32I-NEXT: lw s4, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: mv s2, t5 +; RV32I-NEXT: beqz a5, .LBB10_47 ; RV32I-NEXT: .LBB10_46: -; RV32I-NEXT: slti a0, s0, 0 -; RV32I-NEXT: neg s10, a0 -; RV32I-NEXT: slti a0, t4, 0 -; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: li t4, 128 -; RV32I-NEXT: bltu a6, t4, .LBB10_48 -; RV32I-NEXT: # %bb.47: -; RV32I-NEXT: and t4, a0, s9 -; RV32I-NEXT: and t0, t0, t4 -; RV32I-NEXT: lw s6, 48(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw t6, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: mv t4, a5 -; RV32I-NEXT: bnez a6, .LBB10_49 -; RV32I-NEXT: j .LBB10_50 -; RV32I-NEXT: .LBB10_48: -; RV32I-NEXT: lw t6, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: and t0, s10, t6 -; RV32I-NEXT: and t0, ra, t0 -; RV32I-NEXT: lw t2, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: or t0, t0, t2 -; RV32I-NEXT: lw s6, 48(sp) # 4-byte Folded Reload -; RV32I-NEXT: mv t4, a5 -; RV32I-NEXT: beqz a6, .LBB10_50 +; RV32I-NEXT: mv s2, t3 +; RV32I-NEXT: .LBB10_47: +; RV32I-NEXT: lw t3, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgez t3, .LBB10_49 +; RV32I-NEXT: # %bb.48: +; RV32I-NEXT: srl t3, t5, s6 +; RV32I-NEXT: slli s3, s3, 1 +; RV32I-NEXT: lw t5, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: sll t5, s3, t5 +; RV32I-NEXT: or t3, t3, t5 +; RV32I-NEXT: sw t3, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: .LBB10_49: -; RV32I-NEXT: mv t4, t0 -; RV32I-NEXT: .LBB10_50: -; RV32I-NEXT: bgez s3, .LBB10_52 -; RV32I-NEXT: # %bb.51: -; RV32I-NEXT: srl a5, a5, s11 -; RV32I-NEXT: slli s7, s7, 1 -; RV32I-NEXT: lw t0, 32(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll t0, s7, t0 -; RV32I-NEXT: or a5, a5, t0 -; RV32I-NEXT: sw a5, 36(sp) # 4-byte Folded Spill +; RV32I-NEXT: lw s3, 40(sp) # 4-byte Folded Reload +; RV32I-NEXT: slti t3, s3, 0 +; RV32I-NEXT: neg t5, t3 +; RV32I-NEXT: bltu a5, t2, .LBB10_51 +; RV32I-NEXT: # %bb.50: +; RV32I-NEXT: lw t3, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: and s1, t5, t3 +; RV32I-NEXT: mv t3, a6 +; RV32I-NEXT: bnez a5, .LBB10_52 +; RV32I-NEXT: j .LBB10_53 +; RV32I-NEXT: .LBB10_51: +; RV32I-NEXT: lw t3, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: and t3, s8, t3 +; RV32I-NEXT: lw s1, 28(sp) # 4-byte Folded Reload +; RV32I-NEXT: or s1, t3, s1 +; RV32I-NEXT: mv t3, a6 +; RV32I-NEXT: beqz a5, .LBB10_53 ; RV32I-NEXT: .LBB10_52: -; RV32I-NEXT: lw s5, 60(sp) # 4-byte Folded Reload -; RV32I-NEXT: mv s7, t3 -; RV32I-NEXT: slti a5, s6, 0 -; RV32I-NEXT: neg a5, a5 -; RV32I-NEXT: li t2, 64 -; RV32I-NEXT: mv t3, a1 -; RV32I-NEXT: bltu a6, t2, .LBB10_54 -; RV32I-NEXT: # %bb.53: -; RV32I-NEXT: and t6, a5, t6 -; RV32I-NEXT: mv t0, a7 -; RV32I-NEXT: bnez a6, .LBB10_55 -; RV32I-NEXT: j .LBB10_56 -; RV32I-NEXT: .LBB10_54: -; RV32I-NEXT: lw t0, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: and t0, s10, t0 -; RV32I-NEXT: lw t6, 36(sp) # 4-byte Folded Reload -; RV32I-NEXT: or t6, t0, t6 -; RV32I-NEXT: mv t0, a7 -; RV32I-NEXT: beqz a6, .LBB10_56 +; RV32I-NEXT: mv t3, s1 +; RV32I-NEXT: .LBB10_53: +; RV32I-NEXT: bgez s5, .LBB10_55 +; RV32I-NEXT: # %bb.54: +; RV32I-NEXT: sll a0, a4, a0 +; RV32I-NEXT: or a0, t1, a0 +; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: .LBB10_55: -; RV32I-NEXT: mv t0, t6 -; RV32I-NEXT: .LBB10_56: -; RV32I-NEXT: bgez s8, .LBB10_58 -; RV32I-NEXT: # %bb.57: -; RV32I-NEXT: sll a4, a4, t5 -; RV32I-NEXT: lw a1, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: or s4, a1, a4 -; RV32I-NEXT: .LBB10_58: -; RV32I-NEXT: lw t5, 72(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw t6, 68(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw a4, 84(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw a1, 40(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz a1, .LBB10_61 -; RV32I-NEXT: # %bb.59: -; RV32I-NEXT: mv a1, a4 -; RV32I-NEXT: bgeu s2, t2, .LBB10_62 -; RV32I-NEXT: .LBB10_60: -; RV32I-NEXT: and a0, a0, s5 -; RV32I-NEXT: or a1, a0, a1 +; RV32I-NEXT: lw a4, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t1, 32(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a0, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a0, .LBB10_58 +; RV32I-NEXT: # %bb.56: +; RV32I-NEXT: mv a0, ra +; RV32I-NEXT: bgeu t6, t2, .LBB10_59 +; RV32I-NEXT: .LBB10_57: +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: or a1, a1, a0 ; RV32I-NEXT: mv a0, a3 -; RV32I-NEXT: bnez s2, .LBB10_63 -; RV32I-NEXT: j .LBB10_64 -; RV32I-NEXT: .LBB10_61: -; RV32I-NEXT: li a1, 192 -; RV32I-NEXT: sub a1, a1, a6 -; RV32I-NEXT: xori a1, a1, 31 -; RV32I-NEXT: sll a1, t3, a1 -; RV32I-NEXT: or a1, s7, a1 -; RV32I-NEXT: bltu s2, t2, .LBB10_60 -; RV32I-NEXT: .LBB10_62: -; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: bnez t6, .LBB10_60 +; RV32I-NEXT: j .LBB10_61 +; RV32I-NEXT: .LBB10_58: +; RV32I-NEXT: li a0, 192 +; RV32I-NEXT: sub a0, a0, a5 +; RV32I-NEXT: not a0, a0 +; RV32I-NEXT: sll a0, t4, a0 +; RV32I-NEXT: or a0, s7, a0 +; RV32I-NEXT: bltu t6, t2, .LBB10_57 +; RV32I-NEXT: .LBB10_59: +; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: and a1, a0, s9 +; RV32I-NEXT: and a1, a0, s4 ; RV32I-NEXT: mv a0, a3 -; RV32I-NEXT: beqz s2, .LBB10_64 -; RV32I-NEXT: .LBB10_63: +; RV32I-NEXT: beqz t6, .LBB10_61 +; RV32I-NEXT: .LBB10_60: ; RV32I-NEXT: mv a0, a1 -; RV32I-NEXT: .LBB10_64: +; RV32I-NEXT: .LBB10_61: ; RV32I-NEXT: li a1, 128 -; RV32I-NEXT: bltu a6, a1, .LBB10_69 -; RV32I-NEXT: # %bb.65: -; RV32I-NEXT: bnez a6, .LBB10_70 +; RV32I-NEXT: bltu a5, a1, .LBB10_70 +; RV32I-NEXT: # %bb.62: +; RV32I-NEXT: lw t3, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: bnez a5, .LBB10_71 +; RV32I-NEXT: .LBB10_63: +; RV32I-NEXT: mv a0, t3 +; RV32I-NEXT: bgez s3, .LBB10_72 +; RV32I-NEXT: .LBB10_64: +; RV32I-NEXT: bgez s11, .LBB10_73 +; RV32I-NEXT: .LBB10_65: +; RV32I-NEXT: bltu a5, t2, .LBB10_74 ; RV32I-NEXT: .LBB10_66: -; RV32I-NEXT: bltz s6, .LBB10_71 +; RV32I-NEXT: bnez a5, .LBB10_75 ; RV32I-NEXT: .LBB10_67: -; RV32I-NEXT: mv a0, s9 -; RV32I-NEXT: bgez s0, .LBB10_72 +; RV32I-NEXT: lw a0, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a0, .LBB10_76 ; RV32I-NEXT: .LBB10_68: -; RV32I-NEXT: lw a1, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw t0, 52(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl a1, a1, t0 -; RV32I-NEXT: lw t0, 28(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a1, t0, a1 -; RV32I-NEXT: bltu a6, t2, .LBB10_73 -; RV32I-NEXT: j .LBB10_74 +; RV32I-NEXT: sltiu a0, a5, 128 +; RV32I-NEXT: bltu a5, t2, .LBB10_77 ; RV32I-NEXT: .LBB10_69: -; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a0, s4 -; RV32I-NEXT: or a0, t0, a0 -; RV32I-NEXT: beqz a6, .LBB10_66 +; RV32I-NEXT: and a1, t5, s4 +; RV32I-NEXT: neg a4, a0 +; RV32I-NEXT: bnez a5, .LBB10_78 +; RV32I-NEXT: j .LBB10_79 ; RV32I-NEXT: .LBB10_70: -; RV32I-NEXT: mv a7, a0 -; RV32I-NEXT: bgez s6, .LBB10_67 -; RV32I-NEXT: .LBB10_71: ; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl a0, t6, a0 -; RV32I-NEXT: or a0, t5, a0 -; RV32I-NEXT: bltz s0, .LBB10_68 +; RV32I-NEXT: and a0, t1, a0 +; RV32I-NEXT: or a0, t3, a0 +; RV32I-NEXT: lw t3, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: beqz a5, .LBB10_63 +; RV32I-NEXT: .LBB10_71: +; RV32I-NEXT: mv a6, a0 +; RV32I-NEXT: mv a0, t3 +; RV32I-NEXT: bltz s3, .LBB10_64 ; RV32I-NEXT: .LBB10_72: -; RV32I-NEXT: mv a1, s5 -; RV32I-NEXT: bgeu a6, t2, .LBB10_74 +; RV32I-NEXT: mv a0, s4 +; RV32I-NEXT: bltz s11, .LBB10_65 ; RV32I-NEXT: .LBB10_73: -; RV32I-NEXT: lw a0, 44(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a0, a4 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: sw a4, 44(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgeu a5, t2, .LBB10_66 ; RV32I-NEXT: .LBB10_74: -; RV32I-NEXT: bnez a6, .LBB10_78 -; RV32I-NEXT: # %bb.75: -; RV32I-NEXT: bltz s3, .LBB10_79 +; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a0, a0, ra +; RV32I-NEXT: lw a1, 44(sp) # 4-byte Folded Reload +; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: beqz a5, .LBB10_67 +; RV32I-NEXT: .LBB10_75: +; RV32I-NEXT: sw a0, 72(sp) # 4-byte Folded Spill +; RV32I-NEXT: lw a0, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgez a0, .LBB10_68 ; RV32I-NEXT: .LBB10_76: -; RV32I-NEXT: sltiu a0, a6, 128 -; RV32I-NEXT: bltu a6, t2, .LBB10_80 +; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: sll a0, t4, a0 +; RV32I-NEXT: or ra, s7, a0 +; RV32I-NEXT: sltiu a0, a5, 128 +; RV32I-NEXT: bgeu a5, t2, .LBB10_69 ; RV32I-NEXT: .LBB10_77: -; RV32I-NEXT: and a1, a5, s9 +; RV32I-NEXT: and a1, s8, a4 +; RV32I-NEXT: or a1, a1, ra ; RV32I-NEXT: neg a4, a0 -; RV32I-NEXT: bnez a6, .LBB10_81 -; RV32I-NEXT: j .LBB10_82 +; RV32I-NEXT: beqz a5, .LBB10_79 ; RV32I-NEXT: .LBB10_78: -; RV32I-NEXT: sw a0, 88(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgez s3, .LBB10_76 -; RV32I-NEXT: .LBB10_79: -; RV32I-NEXT: lw a0, 32(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a0, t3, a0 -; RV32I-NEXT: or a4, s7, a0 -; RV32I-NEXT: sltiu a0, a6, 128 -; RV32I-NEXT: bgeu a6, t2, .LBB10_77 -; RV32I-NEXT: .LBB10_80: -; RV32I-NEXT: and a1, s10, s5 -; RV32I-NEXT: or a1, a1, a4 -; RV32I-NEXT: neg a4, a0 -; RV32I-NEXT: beqz a6, .LBB10_82 -; RV32I-NEXT: .LBB10_81: ; RV32I-NEXT: mv a3, a1 -; RV32I-NEXT: .LBB10_82: -; RV32I-NEXT: lw a1, 88(sp) # 4-byte Folded Reload +; RV32I-NEXT: .LBB10_79: +; RV32I-NEXT: lw a1, 72(sp) # 4-byte Folded Reload ; RV32I-NEXT: and a1, a4, a1 ; RV32I-NEXT: and a0, a4, a3 -; RV32I-NEXT: bltz s0, .LBB10_84 -; RV32I-NEXT: # %bb.83: -; RV32I-NEXT: mv a3, s9 -; RV32I-NEXT: j .LBB10_85 -; RV32I-NEXT: .LBB10_84: -; RV32I-NEXT: lw a3, 52(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl a3, t6, a3 -; RV32I-NEXT: or a3, t5, a3 -; RV32I-NEXT: .LBB10_85: -; RV32I-NEXT: and a3, ra, a3 +; RV32I-NEXT: bltz s11, .LBB10_81 +; RV32I-NEXT: # %bb.80: +; RV32I-NEXT: mv t3, s4 +; RV32I-NEXT: .LBB10_81: +; RV32I-NEXT: and a3, s9, t3 ; RV32I-NEXT: and a3, a4, a3 -; RV32I-NEXT: and a5, s10, s9 -; RV32I-NEXT: and a5, ra, a5 +; RV32I-NEXT: and a5, s8, s4 +; RV32I-NEXT: and a5, s9, a5 ; RV32I-NEXT: and a4, a4, a5 ; RV32I-NEXT: sb a4, 0(a2) ; RV32I-NEXT: sb a3, 4(a2) @@ -3194,54 +3088,54 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sb a3, 14(a2) ; RV32I-NEXT: srli a1, a1, 8 ; RV32I-NEXT: sb a1, 13(a2) -; RV32I-NEXT: sb t1, 28(a2) +; RV32I-NEXT: sb a7, 28(a2) ; RV32I-NEXT: srli a1, a0, 24 ; RV32I-NEXT: sb a1, 11(a2) ; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: sb a1, 10(a2) ; RV32I-NEXT: srli a0, a0, 8 ; RV32I-NEXT: sb a0, 9(a2) -; RV32I-NEXT: sb a7, 24(a2) -; RV32I-NEXT: srli a0, t1, 24 +; RV32I-NEXT: sb a6, 24(a2) +; RV32I-NEXT: srli a0, a7, 24 ; RV32I-NEXT: sb a0, 31(a2) -; RV32I-NEXT: srli a0, t1, 16 +; RV32I-NEXT: srli a0, a7, 16 ; RV32I-NEXT: sb a0, 30(a2) -; RV32I-NEXT: srli a0, t1, 8 +; RV32I-NEXT: srli a0, a7, 8 ; RV32I-NEXT: sb a0, 29(a2) -; RV32I-NEXT: sb t4, 16(a2) -; RV32I-NEXT: srli a0, a7, 24 +; RV32I-NEXT: sb s2, 16(a2) +; RV32I-NEXT: srli a0, a6, 24 ; RV32I-NEXT: sb a0, 27(a2) -; RV32I-NEXT: srli a0, a7, 16 +; RV32I-NEXT: srli a0, a6, 16 ; RV32I-NEXT: sb a0, 26(a2) -; RV32I-NEXT: srli a0, a7, 8 +; RV32I-NEXT: srli a0, a6, 8 ; RV32I-NEXT: sb a0, 25(a2) -; RV32I-NEXT: srli a0, t4, 24 +; RV32I-NEXT: srli a0, s2, 24 ; RV32I-NEXT: sb a0, 19(a2) -; RV32I-NEXT: srli a0, t4, 16 +; RV32I-NEXT: srli a0, s2, 16 ; RV32I-NEXT: sb a0, 18(a2) -; RV32I-NEXT: srli a0, t4, 8 +; RV32I-NEXT: srli a0, s2, 8 ; RV32I-NEXT: sb a0, 17(a2) -; RV32I-NEXT: sb s1, 20(a2) -; RV32I-NEXT: srli a0, s1, 24 +; RV32I-NEXT: sb t0, 20(a2) +; RV32I-NEXT: srli a0, t0, 24 ; RV32I-NEXT: sb a0, 23(a2) -; RV32I-NEXT: srli a0, s1, 16 +; RV32I-NEXT: srli a0, t0, 16 ; RV32I-NEXT: sb a0, 22(a2) -; RV32I-NEXT: srli s1, s1, 8 -; RV32I-NEXT: sb s1, 21(a2) -; RV32I-NEXT: lw ra, 140(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 136(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 132(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 128(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s3, 124(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s4, 120(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s5, 116(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s6, 112(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s7, 108(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s8, 104(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s9, 100(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s10, 96(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s11, 92(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 144 +; RV32I-NEXT: srli a0, t0, 8 +; RV32I-NEXT: sb a0, 21(a2) +; RV32I-NEXT: lw ra, 124(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 120(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 116(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 112(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s3, 108(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s4, 104(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s5, 100(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s6, 96(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s7, 92(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s8, 88(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s9, 84(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s10, 80(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s11, 76(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 128 ; RV32I-NEXT: ret %src = load i256, ptr %src.ptr, align 1 %byteOff = load i256, ptr %byteOff.ptr, align 1 @@ -3253,12 +3147,10 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-LABEL: ashr_32bytes: ; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -48 -; RV64I-NEXT: sd s0, 40(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s1, 32(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s2, 24(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s3, 16(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s4, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: addi sp, sp, -32 +; RV64I-NEXT: sd s0, 24(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s1, 16(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s2, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lbu a3, 9(a0) ; RV64I-NEXT: lbu a4, 8(a0) ; RV64I-NEXT: lbu a5, 10(a0) @@ -3290,7 +3182,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a6, a6, 16 ; RV64I-NEXT: slli a7, a7, 24 ; RV64I-NEXT: or a4, a6, a4 -; RV64I-NEXT: or t1, a7, a4 +; RV64I-NEXT: or t0, a7, a4 ; RV64I-NEXT: lbu a4, 5(a0) ; RV64I-NEXT: lbu a5, 4(a0) ; RV64I-NEXT: lbu a6, 6(a0) @@ -3300,199 +3192,166 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a6, a6, 16 ; RV64I-NEXT: slli a7, a7, 24 ; RV64I-NEXT: or a4, a6, a4 -; RV64I-NEXT: or a5, a7, a4 +; RV64I-NEXT: or t1, a7, a4 +; RV64I-NEXT: slli t1, t1, 32 ; RV64I-NEXT: lbu a4, 25(a0) -; RV64I-NEXT: lbu a6, 24(a0) -; RV64I-NEXT: lbu a7, 26(a0) -; RV64I-NEXT: lbu t0, 27(a0) +; RV64I-NEXT: lbu a5, 24(a0) +; RV64I-NEXT: lbu a6, 26(a0) +; RV64I-NEXT: lbu a7, 27(a0) ; RV64I-NEXT: slli a4, a4, 8 -; RV64I-NEXT: or a4, a4, a6 -; RV64I-NEXT: slli a7, a7, 16 -; RV64I-NEXT: slli t0, t0, 24 -; RV64I-NEXT: or a6, a7, a4 -; RV64I-NEXT: lbu a4, 29(a0) -; RV64I-NEXT: lbu a7, 28(a0) +; RV64I-NEXT: or a4, a4, a5 +; RV64I-NEXT: slli a6, a6, 16 +; RV64I-NEXT: slli a7, a7, 24 +; RV64I-NEXT: or a4, a6, a4 +; RV64I-NEXT: lbu a5, 29(a0) +; RV64I-NEXT: lbu a6, 28(a0) ; RV64I-NEXT: lbu t2, 30(a0) ; RV64I-NEXT: lbu t3, 31(a0) +; RV64I-NEXT: slli a5, a5, 8 +; RV64I-NEXT: or a5, a5, a6 +; RV64I-NEXT: slli t2, t2, 16 +; RV64I-NEXT: slli t3, t3, 24 +; RV64I-NEXT: or a5, t2, a5 +; RV64I-NEXT: or a5, t3, a5 +; RV64I-NEXT: slli a6, a5, 32 +; RV64I-NEXT: or a4, a6, a4 +; RV64I-NEXT: or a7, a4, a7 +; RV64I-NEXT: lbu a4, 17(a0) +; RV64I-NEXT: lbu a6, 16(a0) +; RV64I-NEXT: lbu t2, 18(a0) +; RV64I-NEXT: lbu t3, 19(a0) ; RV64I-NEXT: slli a4, a4, 8 -; RV64I-NEXT: or a4, a4, a7 +; RV64I-NEXT: or a4, a4, a6 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli t3, t3, 24 ; RV64I-NEXT: or a4, t2, a4 -; RV64I-NEXT: or a4, t3, a4 -; RV64I-NEXT: slli a7, a4, 32 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: lbu a7, 17(a0) -; RV64I-NEXT: lbu t2, 16(a0) -; RV64I-NEXT: lbu t3, 18(a0) -; RV64I-NEXT: or a6, a6, t0 -; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a7, a7, t2 -; RV64I-NEXT: slli t3, t3, 16 -; RV64I-NEXT: lbu t0, 21(a0) +; RV64I-NEXT: lbu a6, 21(a0) ; RV64I-NEXT: lbu t2, 20(a0) -; RV64I-NEXT: or a7, t3, a7 -; RV64I-NEXT: lbu t3, 19(a0) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t2 -; RV64I-NEXT: lbu t2, 22(a0) -; RV64I-NEXT: lbu t4, 23(a0) -; RV64I-NEXT: slli a0, a5, 32 -; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: slli t2, t2, 16 -; RV64I-NEXT: slli t4, t4, 24 -; RV64I-NEXT: or a5, t2, t0 -; RV64I-NEXT: or a5, t4, a5 -; RV64I-NEXT: slli a5, a5, 32 -; RV64I-NEXT: or a5, a5, a7 -; RV64I-NEXT: or t2, a5, t3 -; RV64I-NEXT: lbu a5, 5(a1) -; RV64I-NEXT: lbu a7, 4(a1) -; RV64I-NEXT: lbu t0, 6(a1) +; RV64I-NEXT: lbu t4, 22(a0) +; RV64I-NEXT: lbu a0, 23(a0) +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: or a6, a6, t2 +; RV64I-NEXT: slli t4, t4, 16 +; RV64I-NEXT: slli a0, a0, 24 +; RV64I-NEXT: or a6, t4, a6 +; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: or a0, a0, a4 +; RV64I-NEXT: or t2, a0, t3 +; RV64I-NEXT: lbu a0, 5(a1) +; RV64I-NEXT: lbu a4, 4(a1) +; RV64I-NEXT: lbu a6, 6(a1) ; RV64I-NEXT: lbu t3, 7(a1) -; RV64I-NEXT: slli a5, a5, 8 -; RV64I-NEXT: or a5, a5, a7 -; RV64I-NEXT: slli t0, t0, 16 +; RV64I-NEXT: slli a0, a0, 8 +; RV64I-NEXT: or a0, a0, a4 +; RV64I-NEXT: slli a6, a6, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or a5, t0, a5 -; RV64I-NEXT: or a5, t3, a5 -; RV64I-NEXT: lbu a7, 1(a1) -; RV64I-NEXT: lbu t0, 0(a1) +; RV64I-NEXT: or a0, a6, a0 +; RV64I-NEXT: or a0, t3, a0 +; RV64I-NEXT: lbu a4, 1(a1) +; RV64I-NEXT: lbu a6, 0(a1) ; RV64I-NEXT: lbu t3, 2(a1) ; RV64I-NEXT: lbu a1, 3(a1) -; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a7, a7, t0 +; RV64I-NEXT: slli a4, a4, 8 +; RV64I-NEXT: or a4, a4, a6 ; RV64I-NEXT: slli t3, t3, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a7, t3, a7 -; RV64I-NEXT: or a1, a1, a7 +; RV64I-NEXT: or a4, t3, a4 +; RV64I-NEXT: or a1, a1, a4 ; RV64I-NEXT: slli a1, a1, 3 -; RV64I-NEXT: slli a5, a5, 35 -; RV64I-NEXT: or a5, a5, a1 -; RV64I-NEXT: srl a7, t2, a5 -; RV64I-NEXT: slli t0, a6, 1 -; RV64I-NEXT: addi t5, a5, -192 -; RV64I-NEXT: sra a1, a6, a5 -; RV64I-NEXT: bltz t5, .LBB11_2 +; RV64I-NEXT: slli a0, a0, 35 +; RV64I-NEXT: or a6, a0, a1 +; RV64I-NEXT: srl a0, t2, a6 +; RV64I-NEXT: not t5, a6 +; RV64I-NEXT: slli a1, a7, 1 +; RV64I-NEXT: sll a1, a1, t5 +; RV64I-NEXT: or a1, a0, a1 +; RV64I-NEXT: addi t3, a6, -192 +; RV64I-NEXT: sra a4, a7, a6 +; RV64I-NEXT: mv t6, a1 +; RV64I-NEXT: bltz t3, .LBB11_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv s1, a1 -; RV64I-NEXT: j .LBB11_3 +; RV64I-NEXT: mv t6, a4 ; RV64I-NEXT: .LBB11_2: -; RV64I-NEXT: addiw t3, a5, -128 -; RV64I-NEXT: xori t3, t3, 63 -; RV64I-NEXT: sll t3, t0, t3 -; RV64I-NEXT: or s1, a7, t3 -; RV64I-NEXT: .LBB11_3: -; RV64I-NEXT: or a0, a0, t1 -; RV64I-NEXT: xori t4, a5, 63 -; RV64I-NEXT: addi t1, a5, -64 -; RV64I-NEXT: srl t6, a3, a5 -; RV64I-NEXT: bltz t1, .LBB11_5 -; RV64I-NEXT: # %bb.4: -; RV64I-NEXT: mv s4, t6 -; RV64I-NEXT: j .LBB11_6 -; RV64I-NEXT: .LBB11_5: -; RV64I-NEXT: srl t3, a0, a5 +; RV64I-NEXT: or a0, t1, t0 +; RV64I-NEXT: addi t0, a6, -64 +; RV64I-NEXT: srl t4, a3, a6 +; RV64I-NEXT: bltz t0, .LBB11_4 +; RV64I-NEXT: # %bb.3: +; RV64I-NEXT: mv s2, t4 +; RV64I-NEXT: j .LBB11_5 +; RV64I-NEXT: .LBB11_4: +; RV64I-NEXT: srl t1, a0, a6 ; RV64I-NEXT: slli s0, a3, 1 -; RV64I-NEXT: sll s0, s0, t4 -; RV64I-NEXT: or s4, t3, s0 -; RV64I-NEXT: .LBB11_6: -; RV64I-NEXT: negw s2, a5 -; RV64I-NEXT: sll s0, t2, s2 -; RV64I-NEXT: li s3, 64 -; RV64I-NEXT: li t3, 128 -; RV64I-NEXT: sub s3, s3, a5 -; RV64I-NEXT: bltu a5, t3, .LBB11_15 -; RV64I-NEXT: # %bb.7: -; RV64I-NEXT: bnez a5, .LBB11_16 +; RV64I-NEXT: sll t5, s0, t5 +; RV64I-NEXT: or s2, t1, t5 +; RV64I-NEXT: .LBB11_5: +; RV64I-NEXT: negw s0, a6 +; RV64I-NEXT: sll t5, t2, s0 +; RV64I-NEXT: li s1, 64 +; RV64I-NEXT: li t1, 128 +; RV64I-NEXT: sub s1, s1, a6 +; RV64I-NEXT: bltu a6, t1, .LBB11_18 +; RV64I-NEXT: # %bb.6: +; RV64I-NEXT: bnez a6, .LBB11_19 +; RV64I-NEXT: .LBB11_7: +; RV64I-NEXT: bgez s1, .LBB11_9 ; RV64I-NEXT: .LBB11_8: -; RV64I-NEXT: bgez s3, .LBB11_10 -; RV64I-NEXT: .LBB11_9: -; RV64I-NEXT: sll a6, a6, s2 +; RV64I-NEXT: sll a7, a7, s0 ; RV64I-NEXT: srli t2, t2, 1 -; RV64I-NEXT: subw s0, t3, a5 -; RV64I-NEXT: xori s0, s0, 63 -; RV64I-NEXT: srl t2, t2, s0 -; RV64I-NEXT: or s0, a6, t2 -; RV64I-NEXT: .LBB11_10: -; RV64I-NEXT: sraiw a6, a4, 31 -; RV64I-NEXT: mv a4, a1 -; RV64I-NEXT: bgez t5, .LBB11_17 -; RV64I-NEXT: # %bb.11: -; RV64I-NEXT: bltu a5, t3, .LBB11_18 +; RV64I-NEXT: subw t5, t1, a6 +; RV64I-NEXT: not t5, t5 +; RV64I-NEXT: srl t2, t2, t5 +; RV64I-NEXT: or t5, a7, t2 +; RV64I-NEXT: .LBB11_9: +; RV64I-NEXT: sraiw a5, a5, 31 +; RV64I-NEXT: mv a7, a4 +; RV64I-NEXT: bgez t3, .LBB11_20 +; RV64I-NEXT: # %bb.10: +; RV64I-NEXT: bltu a6, t1, .LBB11_21 +; RV64I-NEXT: .LBB11_11: +; RV64I-NEXT: bnez a6, .LBB11_22 ; RV64I-NEXT: .LBB11_12: -; RV64I-NEXT: bnez a5, .LBB11_19 +; RV64I-NEXT: bgez t0, .LBB11_23 ; RV64I-NEXT: .LBB11_13: -; RV64I-NEXT: bltz t1, .LBB11_20 +; RV64I-NEXT: bgeu a6, t1, .LBB11_24 ; RV64I-NEXT: .LBB11_14: -; RV64I-NEXT: mv a4, a1 -; RV64I-NEXT: bgeu a5, t3, .LBB11_21 -; RV64I-NEXT: j .LBB11_22 +; RV64I-NEXT: bgez t0, .LBB11_25 ; RV64I-NEXT: .LBB11_15: -; RV64I-NEXT: slti s1, s3, 0 -; RV64I-NEXT: neg s1, s1 -; RV64I-NEXT: and s1, s1, s0 -; RV64I-NEXT: or s1, s4, s1 -; RV64I-NEXT: beqz a5, .LBB11_8 +; RV64I-NEXT: bltu a6, t1, .LBB11_17 ; RV64I-NEXT: .LBB11_16: -; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: bltz s3, .LBB11_9 -; RV64I-NEXT: j .LBB11_10 +; RV64I-NEXT: mv a4, a5 ; RV64I-NEXT: .LBB11_17: -; RV64I-NEXT: mv a4, a6 -; RV64I-NEXT: bgeu a5, t3, .LBB11_12 -; RV64I-NEXT: .LBB11_18: -; RV64I-NEXT: slti a4, t1, 0 -; RV64I-NEXT: neg a4, a4 -; RV64I-NEXT: and a4, a4, t6 -; RV64I-NEXT: or a4, a4, s0 -; RV64I-NEXT: beqz a5, .LBB11_13 -; RV64I-NEXT: .LBB11_19: -; RV64I-NEXT: mv a3, a4 -; RV64I-NEXT: bgez t1, .LBB11_14 -; RV64I-NEXT: .LBB11_20: -; RV64I-NEXT: sll a4, t0, t4 -; RV64I-NEXT: or a4, a7, a4 -; RV64I-NEXT: bltu a5, t3, .LBB11_22 -; RV64I-NEXT: .LBB11_21: -; RV64I-NEXT: mv a4, a6 -; RV64I-NEXT: .LBB11_22: -; RV64I-NEXT: bgez t1, .LBB11_26 -; RV64I-NEXT: # %bb.23: -; RV64I-NEXT: bltu a5, t3, .LBB11_25 -; RV64I-NEXT: .LBB11_24: -; RV64I-NEXT: mv a1, a6 -; RV64I-NEXT: .LBB11_25: -; RV64I-NEXT: sb a1, 24(a2) -; RV64I-NEXT: srli a5, a1, 56 +; RV64I-NEXT: sb a4, 24(a2) +; RV64I-NEXT: srli a5, a4, 56 ; RV64I-NEXT: sb a5, 31(a2) -; RV64I-NEXT: srli a5, a1, 48 +; RV64I-NEXT: srli a5, a4, 48 ; RV64I-NEXT: sb a5, 30(a2) -; RV64I-NEXT: srli a5, a1, 40 +; RV64I-NEXT: srli a5, a4, 40 ; RV64I-NEXT: sb a5, 29(a2) -; RV64I-NEXT: srli a5, a1, 32 +; RV64I-NEXT: srli a5, a4, 32 ; RV64I-NEXT: sb a5, 28(a2) -; RV64I-NEXT: srli a5, a1, 24 +; RV64I-NEXT: srli a5, a4, 24 ; RV64I-NEXT: sb a5, 27(a2) -; RV64I-NEXT: srli a5, a1, 16 +; RV64I-NEXT: srli a5, a4, 16 ; RV64I-NEXT: sb a5, 26(a2) -; RV64I-NEXT: srli a1, a1, 8 -; RV64I-NEXT: sb a1, 25(a2) -; RV64I-NEXT: sb a4, 16(a2) -; RV64I-NEXT: srli a1, a4, 56 -; RV64I-NEXT: sb a1, 23(a2) -; RV64I-NEXT: srli a1, a4, 48 -; RV64I-NEXT: sb a1, 22(a2) -; RV64I-NEXT: srli a1, a4, 40 -; RV64I-NEXT: sb a1, 21(a2) -; RV64I-NEXT: srli a1, a4, 32 -; RV64I-NEXT: sb a1, 20(a2) -; RV64I-NEXT: srli a1, a4, 24 -; RV64I-NEXT: sb a1, 19(a2) -; RV64I-NEXT: srli a1, a4, 16 -; RV64I-NEXT: sb a1, 18(a2) ; RV64I-NEXT: srli a4, a4, 8 -; RV64I-NEXT: sb a4, 17(a2) +; RV64I-NEXT: sb a4, 25(a2) +; RV64I-NEXT: sb a1, 16(a2) +; RV64I-NEXT: srli a4, a1, 56 +; RV64I-NEXT: sb a4, 23(a2) +; RV64I-NEXT: srli a4, a1, 48 +; RV64I-NEXT: sb a4, 22(a2) +; RV64I-NEXT: srli a4, a1, 40 +; RV64I-NEXT: sb a4, 21(a2) +; RV64I-NEXT: srli a4, a1, 32 +; RV64I-NEXT: sb a4, 20(a2) +; RV64I-NEXT: srli a4, a1, 24 +; RV64I-NEXT: sb a4, 19(a2) +; RV64I-NEXT: srli a4, a1, 16 +; RV64I-NEXT: sb a4, 18(a2) +; RV64I-NEXT: srli a1, a1, 8 +; RV64I-NEXT: sb a1, 17(a2) ; RV64I-NEXT: sb a0, 0(a2) ; RV64I-NEXT: srli a1, a0, 56 ; RV64I-NEXT: sb a1, 7(a2) @@ -3523,590 +3382,539 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: sb a0, 10(a2) ; RV64I-NEXT: srli a3, a3, 8 ; RV64I-NEXT: sb a3, 9(a2) -; RV64I-NEXT: ld s0, 40(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s1, 32(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s2, 24(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s3, 16(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s4, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 48 +; RV64I-NEXT: ld s0, 24(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s1, 16(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s2, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB11_26: -; RV64I-NEXT: mv a1, a6 -; RV64I-NEXT: bgeu a5, t3, .LBB11_24 -; RV64I-NEXT: j .LBB11_25 +; RV64I-NEXT: .LBB11_18: +; RV64I-NEXT: slti t6, s1, 0 +; RV64I-NEXT: neg t6, t6 +; RV64I-NEXT: and t6, t6, t5 +; RV64I-NEXT: or t6, s2, t6 +; RV64I-NEXT: beqz a6, .LBB11_7 +; RV64I-NEXT: .LBB11_19: +; RV64I-NEXT: mv a0, t6 +; RV64I-NEXT: bltz s1, .LBB11_8 +; RV64I-NEXT: j .LBB11_9 +; RV64I-NEXT: .LBB11_20: +; RV64I-NEXT: mv a7, a5 +; RV64I-NEXT: bgeu a6, t1, .LBB11_11 +; RV64I-NEXT: .LBB11_21: +; RV64I-NEXT: slti a7, t0, 0 +; RV64I-NEXT: neg a7, a7 +; RV64I-NEXT: and a7, a7, t4 +; RV64I-NEXT: or a7, a7, t5 +; RV64I-NEXT: beqz a6, .LBB11_12 +; RV64I-NEXT: .LBB11_22: +; RV64I-NEXT: mv a3, a7 +; RV64I-NEXT: bltz t0, .LBB11_13 +; RV64I-NEXT: .LBB11_23: +; RV64I-NEXT: mv a1, a4 +; RV64I-NEXT: bltu a6, t1, .LBB11_14 +; RV64I-NEXT: .LBB11_24: +; RV64I-NEXT: mv a1, a5 +; RV64I-NEXT: bltz t0, .LBB11_15 +; RV64I-NEXT: .LBB11_25: +; RV64I-NEXT: mv a4, a5 +; RV64I-NEXT: bgeu a6, t1, .LBB11_16 +; RV64I-NEXT: j .LBB11_17 ; ; RV32I-LABEL: ashr_32bytes: ; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -144 -; RV32I-NEXT: sw ra, 140(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 136(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 132(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 128(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 124(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s4, 120(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s5, 116(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s6, 112(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s7, 108(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s8, 104(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s9, 100(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s10, 96(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s11, 92(sp) # 4-byte Folded Spill +; RV32I-NEXT: addi sp, sp, -128 +; RV32I-NEXT: sw ra, 124(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 120(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 116(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 112(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s3, 108(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s4, 104(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s5, 100(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s6, 96(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s7, 92(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s8, 88(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s9, 84(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s10, 80(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s11, 76(sp) # 4-byte Folded Spill ; RV32I-NEXT: lbu a6, 4(a0) -; RV32I-NEXT: lbu a7, 5(a0) -; RV32I-NEXT: lbu t1, 6(a0) -; RV32I-NEXT: lbu t5, 7(a0) +; RV32I-NEXT: lbu t1, 5(a0) +; RV32I-NEXT: lbu t5, 6(a0) +; RV32I-NEXT: lbu t6, 7(a0) ; RV32I-NEXT: lbu a3, 0(a0) -; RV32I-NEXT: sw a3, 88(sp) # 4-byte Folded Spill -; RV32I-NEXT: lbu t2, 1(a0) -; RV32I-NEXT: lbu t3, 2(a0) -; RV32I-NEXT: lbu t4, 3(a0) -; RV32I-NEXT: lbu t6, 12(a0) -; RV32I-NEXT: lbu s3, 13(a0) -; RV32I-NEXT: lbu s4, 14(a0) -; RV32I-NEXT: lbu s5, 15(a0) +; RV32I-NEXT: sw a3, 72(sp) # 4-byte Folded Spill +; RV32I-NEXT: lbu a5, 1(a0) +; RV32I-NEXT: lbu t2, 2(a0) +; RV32I-NEXT: lbu t3, 3(a0) +; RV32I-NEXT: lbu s0, 12(a0) +; RV32I-NEXT: lbu a4, 13(a0) +; RV32I-NEXT: lbu s3, 14(a0) +; RV32I-NEXT: lbu s4, 15(a0) ; RV32I-NEXT: lbu s2, 8(a0) -; RV32I-NEXT: lbu s6, 9(a0) +; RV32I-NEXT: lbu s1, 9(a0) ; RV32I-NEXT: lbu s7, 10(a0) ; RV32I-NEXT: lbu s8, 11(a0) ; RV32I-NEXT: lbu a3, 21(a0) -; RV32I-NEXT: lbu a4, 20(a0) -; RV32I-NEXT: lbu a5, 22(a0) -; RV32I-NEXT: lbu t0, 23(a0) +; RV32I-NEXT: lbu t0, 20(a0) +; RV32I-NEXT: lbu t4, 22(a0) +; RV32I-NEXT: lbu s5, 23(a0) ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a3, a4 -; RV32I-NEXT: slli a5, a5, 16 -; RV32I-NEXT: slli t0, t0, 24 -; RV32I-NEXT: or a3, a5, a3 -; RV32I-NEXT: or a3, t0, a3 -; RV32I-NEXT: lbu a4, 17(a0) -; RV32I-NEXT: lbu a5, 16(a0) -; RV32I-NEXT: lbu t0, 18(a0) -; RV32I-NEXT: lbu s0, 19(a0) -; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a4, a4, a5 -; RV32I-NEXT: slli t0, t0, 16 -; RV32I-NEXT: slli s0, s0, 24 -; RV32I-NEXT: or a4, t0, a4 -; RV32I-NEXT: or t0, s0, a4 -; RV32I-NEXT: lbu a4, 29(a0) -; RV32I-NEXT: lbu a5, 28(a0) -; RV32I-NEXT: lbu s0, 30(a0) -; RV32I-NEXT: lbu s1, 31(a0) -; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a4, a4, a5 -; RV32I-NEXT: slli s0, s0, 16 -; RV32I-NEXT: slli s1, s1, 24 -; RV32I-NEXT: or a4, s0, a4 -; RV32I-NEXT: sw s1, 32(sp) # 4-byte Folded Spill -; RV32I-NEXT: or s9, s1, a4 -; RV32I-NEXT: lbu a4, 25(a0) -; RV32I-NEXT: lbu a5, 24(a0) -; RV32I-NEXT: lbu s0, 26(a0) +; RV32I-NEXT: or a3, a3, t0 +; RV32I-NEXT: slli t4, t4, 16 +; RV32I-NEXT: slli s5, s5, 24 +; RV32I-NEXT: or a3, t4, a3 +; RV32I-NEXT: or a3, s5, a3 +; RV32I-NEXT: lbu t0, 17(a0) +; RV32I-NEXT: lbu t4, 16(a0) +; RV32I-NEXT: lbu s5, 18(a0) +; RV32I-NEXT: lbu s6, 19(a0) +; RV32I-NEXT: slli t0, t0, 8 +; RV32I-NEXT: or t0, t0, t4 +; RV32I-NEXT: slli s5, s5, 16 +; RV32I-NEXT: slli s6, s6, 24 +; RV32I-NEXT: or t0, s5, t0 +; RV32I-NEXT: or t4, s6, t0 +; RV32I-NEXT: lbu t0, 29(a0) +; RV32I-NEXT: lbu s5, 28(a0) +; RV32I-NEXT: lbu s6, 30(a0) +; RV32I-NEXT: lbu s9, 31(a0) +; RV32I-NEXT: slli t0, t0, 8 +; RV32I-NEXT: or t0, t0, s5 +; RV32I-NEXT: slli s6, s6, 16 +; RV32I-NEXT: slli s9, s9, 24 +; RV32I-NEXT: or t0, s6, t0 +; RV32I-NEXT: sw s9, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: or s10, s9, t0 +; RV32I-NEXT: lbu t0, 25(a0) +; RV32I-NEXT: lbu s5, 24(a0) +; RV32I-NEXT: lbu s6, 26(a0) ; RV32I-NEXT: lbu a0, 27(a0) -; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a4, a4, a5 -; RV32I-NEXT: slli s0, s0, 16 +; RV32I-NEXT: slli t0, t0, 8 +; RV32I-NEXT: or t0, t0, s5 +; RV32I-NEXT: slli s6, s6, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a4, s0, a4 -; RV32I-NEXT: or s0, a0, a4 +; RV32I-NEXT: or t0, s6, t0 +; RV32I-NEXT: or s9, a0, t0 ; RV32I-NEXT: lbu a0, 1(a1) -; RV32I-NEXT: lbu a4, 0(a1) -; RV32I-NEXT: lbu a5, 2(a1) +; RV32I-NEXT: lbu t0, 0(a1) +; RV32I-NEXT: lbu s5, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a0, a0, 8 -; RV32I-NEXT: or a0, a0, a4 -; RV32I-NEXT: slli a5, a5, 16 +; RV32I-NEXT: or a0, a0, t0 +; RV32I-NEXT: slli s5, s5, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a0, a5, a0 +; RV32I-NEXT: or a0, s5, a0 ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: slli a1, a0, 3 -; RV32I-NEXT: srl a4, s0, a1 -; RV32I-NEXT: slli s1, s9, 1 +; RV32I-NEXT: srl a0, s9, a1 +; RV32I-NEXT: slli t0, s10, 1 +; RV32I-NEXT: not s5, a1 +; RV32I-NEXT: sll t0, t0, s5 +; RV32I-NEXT: or t0, a0, t0 ; RV32I-NEXT: addi a0, a1, -224 -; RV32I-NEXT: sw s9, 76(sp) # 4-byte Folded Spill -; RV32I-NEXT: sra a5, s9, a1 -; RV32I-NEXT: sw a0, 40(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a4, 72(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 68(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s10, 60(sp) # 4-byte Folded Spill +; RV32I-NEXT: sra s6, s10, a1 +; RV32I-NEXT: mv s10, t0 +; RV32I-NEXT: sw a0, 32(sp) # 4-byte Folded Spill ; RV32I-NEXT: bltz a0, .LBB11_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: mv a4, a5 -; RV32I-NEXT: j .LBB11_3 +; RV32I-NEXT: mv s10, s6 ; RV32I-NEXT: .LBB11_2: -; RV32I-NEXT: addi a0, a1, -192 -; RV32I-NEXT: xori a0, a0, 31 -; RV32I-NEXT: sll a0, s1, a0 -; RV32I-NEXT: or a4, a4, a0 -; RV32I-NEXT: .LBB11_3: -; RV32I-NEXT: slli s9, s3, 8 -; RV32I-NEXT: slli s10, s4, 16 -; RV32I-NEXT: slli s11, s5, 24 -; RV32I-NEXT: slli ra, s6, 8 +; RV32I-NEXT: slli ra, a4, 8 +; RV32I-NEXT: slli s3, s3, 16 +; RV32I-NEXT: slli s4, s4, 24 +; RV32I-NEXT: slli s1, s1, 8 ; RV32I-NEXT: slli s7, s7, 16 ; RV32I-NEXT: slli s8, s8, 24 -; RV32I-NEXT: srl s3, t0, a1 +; RV32I-NEXT: srl a4, t4, a1 ; RV32I-NEXT: slli a0, a3, 1 -; RV32I-NEXT: addi s5, a1, -128 -; RV32I-NEXT: xori s6, s5, 31 -; RV32I-NEXT: addi s4, a1, -160 -; RV32I-NEXT: srl s1, a3, a1 -; RV32I-NEXT: sw s4, 84(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 64(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a0, 52(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s6, 20(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgez s4, .LBB11_5 -; RV32I-NEXT: # %bb.4: -; RV32I-NEXT: sll a0, a0, s6 -; RV32I-NEXT: or s1, s3, a0 -; RV32I-NEXT: .LBB11_5: -; RV32I-NEXT: slli s3, a7, 8 -; RV32I-NEXT: slli s4, t1, 16 -; RV32I-NEXT: slli t5, t5, 24 -; RV32I-NEXT: or t6, s9, t6 -; RV32I-NEXT: or s6, s11, s10 -; RV32I-NEXT: or s2, ra, s2 -; RV32I-NEXT: or s7, s8, s7 -; RV32I-NEXT: neg a7, a1 -; RV32I-NEXT: sll s8, s0, a7 -; RV32I-NEXT: li a0, 160 +; RV32I-NEXT: sll s11, a0, s5 +; RV32I-NEXT: or s11, a4, s11 +; RV32I-NEXT: addi a7, a1, -160 +; RV32I-NEXT: srl a4, a3, a1 +; RV32I-NEXT: sw a4, 64(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s11, 40(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a7, 68(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz a7, .LBB11_4 +; RV32I-NEXT: # %bb.3: +; RV32I-NEXT: lw s11, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: .LBB11_4: +; RV32I-NEXT: slli a4, t1, 8 +; RV32I-NEXT: slli t5, t5, 16 +; RV32I-NEXT: slli t6, t6, 24 +; RV32I-NEXT: or s0, ra, s0 +; RV32I-NEXT: or s3, s4, s3 +; RV32I-NEXT: or s1, s1, s2 +; RV32I-NEXT: or s8, s8, s7 +; RV32I-NEXT: neg ra, a1 +; RV32I-NEXT: sll s7, s9, ra +; RV32I-NEXT: li s2, 160 +; RV32I-NEXT: addi s4, a1, -128 ; RV32I-NEXT: li t1, 64 -; RV32I-NEXT: sub a0, a0, a1 -; RV32I-NEXT: sw a0, 36(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgeu s5, t1, .LBB11_7 -; RV32I-NEXT: # %bb.6: -; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: and a4, a0, s8 -; RV32I-NEXT: or a4, s1, a4 -; RV32I-NEXT: .LBB11_7: -; RV32I-NEXT: slli t2, t2, 8 -; RV32I-NEXT: slli t3, t3, 16 -; RV32I-NEXT: slli t4, t4, 24 -; RV32I-NEXT: or a0, s3, a6 -; RV32I-NEXT: or a6, t5, s4 -; RV32I-NEXT: or s3, s6, t6 -; RV32I-NEXT: or s7, s7, s2 -; RV32I-NEXT: mv s9, t0 -; RV32I-NEXT: beqz s5, .LBB11_9 -; RV32I-NEXT: # %bb.8: -; RV32I-NEXT: mv s9, a4 -; RV32I-NEXT: .LBB11_9: -; RV32I-NEXT: lw a4, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a4, t2, a4 -; RV32I-NEXT: or t2, t4, t3 -; RV32I-NEXT: or s4, a6, a0 -; RV32I-NEXT: srl ra, s7, a1 -; RV32I-NEXT: slli s11, s3, 1 -; RV32I-NEXT: addi a0, a1, -64 -; RV32I-NEXT: xori a6, a0, 31 -; RV32I-NEXT: addi a0, a1, -96 -; RV32I-NEXT: srl t3, s3, a1 -; RV32I-NEXT: sw a0, 60(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a6, 24(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz a0, .LBB11_11 -; RV32I-NEXT: # %bb.10: -; RV32I-NEXT: mv a6, t3 -; RV32I-NEXT: j .LBB11_12 -; RV32I-NEXT: .LBB11_11: -; RV32I-NEXT: sll a0, s11, a6 -; RV32I-NEXT: or a6, ra, a0 +; RV32I-NEXT: sub a7, s2, a1 +; RV32I-NEXT: sw s7, 52(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgeu s4, t1, .LBB11_6 +; RV32I-NEXT: # %bb.5: +; RV32I-NEXT: slti s2, a7, 0 +; RV32I-NEXT: neg s2, s2 +; RV32I-NEXT: and s2, s2, s7 +; RV32I-NEXT: or s10, s11, s2 +; RV32I-NEXT: .LBB11_6: +; RV32I-NEXT: sw a7, 28(sp) # 4-byte Folded Spill +; RV32I-NEXT: slli a5, a5, 8 +; RV32I-NEXT: slli t2, t2, 16 +; RV32I-NEXT: slli t3, t3, 24 +; RV32I-NEXT: or s2, a4, a6 +; RV32I-NEXT: or t5, t6, t5 +; RV32I-NEXT: or a6, s3, s0 +; RV32I-NEXT: or s8, s8, s1 +; RV32I-NEXT: mv a4, t4 +; RV32I-NEXT: beqz s4, .LBB11_8 +; RV32I-NEXT: # %bb.7: +; RV32I-NEXT: mv a4, s10 +; RV32I-NEXT: .LBB11_8: +; RV32I-NEXT: lw a7, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: or a5, a5, a7 +; RV32I-NEXT: or t3, t3, t2 +; RV32I-NEXT: or t1, t5, s2 +; RV32I-NEXT: srl t2, s8, a1 +; RV32I-NEXT: slli t5, a6, 1 +; RV32I-NEXT: sll t5, t5, s5 +; RV32I-NEXT: or t6, t2, t5 +; RV32I-NEXT: addi s0, a1, -96 +; RV32I-NEXT: srl t2, a6, a1 +; RV32I-NEXT: sw t2, 56(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv t2, t6 +; RV32I-NEXT: li a7, 64 +; RV32I-NEXT: bltz s0, .LBB11_10 +; RV32I-NEXT: # %bb.9: +; RV32I-NEXT: lw t2, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: .LBB11_10: +; RV32I-NEXT: or s3, t3, a5 +; RV32I-NEXT: addi t5, a1, -32 +; RV32I-NEXT: srl a5, t1, a1 +; RV32I-NEXT: sw s0, 48(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a5, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgez t5, .LBB11_12 +; RV32I-NEXT: # %bb.11: +; RV32I-NEXT: srl a5, s3, a1 +; RV32I-NEXT: slli t3, t1, 1 +; RV32I-NEXT: sll t3, t3, s5 +; RV32I-NEXT: or a5, a5, t3 ; RV32I-NEXT: .LBB11_12: -; RV32I-NEXT: or t2, t2, a4 -; RV32I-NEXT: xori s1, a1, 31 -; RV32I-NEXT: addi t6, a1, -32 -; RV32I-NEXT: srl a0, s4, a1 -; RV32I-NEXT: sw s8, 80(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw t3, 56(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgez t6, .LBB11_14 +; RV32I-NEXT: sll s10, s8, ra +; RV32I-NEXT: li t3, 32 +; RV32I-NEXT: sub s0, t3, a1 +; RV32I-NEXT: sw s0, 72(sp) # 4-byte Folded Spill +; RV32I-NEXT: slti s0, s0, 0 +; RV32I-NEXT: neg s0, s0 +; RV32I-NEXT: bgeu a1, a7, .LBB11_14 ; RV32I-NEXT: # %bb.13: -; RV32I-NEXT: srl a0, t2, a1 -; RV32I-NEXT: slli a4, s4, 1 -; RV32I-NEXT: sll a4, a4, s1 -; RV32I-NEXT: or a0, a0, a4 +; RV32I-NEXT: and t2, s0, s10 +; RV32I-NEXT: or t2, a5, t2 ; RV32I-NEXT: .LBB11_14: -; RV32I-NEXT: sll s10, s7, a7 -; RV32I-NEXT: li a4, 32 -; RV32I-NEXT: sub t3, a4, a1 -; RV32I-NEXT: sw t3, 88(sp) # 4-byte Folded Spill -; RV32I-NEXT: slti t3, t3, 0 -; RV32I-NEXT: neg t3, t3 -; RV32I-NEXT: bgeu a1, t1, .LBB11_16 +; RV32I-NEXT: sw a6, 44(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 36(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv s2, s3 +; RV32I-NEXT: beqz a1, .LBB11_16 ; RV32I-NEXT: # %bb.15: -; RV32I-NEXT: and a6, t3, s10 -; RV32I-NEXT: or a6, a0, a6 +; RV32I-NEXT: mv s2, t2 ; RV32I-NEXT: .LBB11_16: -; RV32I-NEXT: sw t3, 44(sp) # 4-byte Folded Spill -; RV32I-NEXT: mv t5, t2 -; RV32I-NEXT: beqz a1, .LBB11_18 +; RV32I-NEXT: sll a6, t4, ra +; RV32I-NEXT: li a5, 96 +; RV32I-NEXT: sub s7, a5, a1 +; RV32I-NEXT: slti a5, s7, 0 +; RV32I-NEXT: neg s11, a5 +; RV32I-NEXT: li t2, 128 +; RV32I-NEXT: sub s0, t2, a1 +; RV32I-NEXT: sltiu a5, s0, 64 +; RV32I-NEXT: neg a5, a5 +; RV32I-NEXT: bgeu a1, t2, .LBB11_18 ; RV32I-NEXT: # %bb.17: -; RV32I-NEXT: mv t5, a6 +; RV32I-NEXT: and a4, s11, a6 +; RV32I-NEXT: and a4, a5, a4 +; RV32I-NEXT: or a4, s2, a4 ; RV32I-NEXT: .LBB11_18: -; RV32I-NEXT: sll s6, t0, a7 -; RV32I-NEXT: li a0, 96 -; RV32I-NEXT: sub s2, a0, a1 -; RV32I-NEXT: slti a0, s2, 0 -; RV32I-NEXT: neg a6, a0 -; RV32I-NEXT: li t4, 128 -; RV32I-NEXT: sub t3, t4, a1 -; RV32I-NEXT: sltiu a0, t3, 64 -; RV32I-NEXT: neg s8, a0 -; RV32I-NEXT: bgeu a1, t4, .LBB11_20 +; RV32I-NEXT: lw s2, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a5, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: beqz a1, .LBB11_20 ; RV32I-NEXT: # %bb.19: -; RV32I-NEXT: and a0, a6, s6 -; RV32I-NEXT: and a0, s8, a0 -; RV32I-NEXT: or s9, t5, a0 +; RV32I-NEXT: mv s3, a4 ; RV32I-NEXT: .LBB11_20: -; RV32I-NEXT: sw s8, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: beqz a1, .LBB11_22 +; RV32I-NEXT: neg a4, s0 +; RV32I-NEXT: sub a5, t3, s0 +; RV32I-NEXT: srl t3, a3, a4 +; RV32I-NEXT: sw a5, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz a5, .LBB11_23 ; RV32I-NEXT: # %bb.21: -; RV32I-NEXT: mv t2, s9 +; RV32I-NEXT: mv a0, t3 +; RV32I-NEXT: bgeu s0, a7, .LBB11_24 ; RV32I-NEXT: .LBB11_22: -; RV32I-NEXT: neg a0, t3 -; RV32I-NEXT: sub a4, a4, t3 -; RV32I-NEXT: srl s8, a3, a0 -; RV32I-NEXT: sw a4, 16(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz a4, .LBB11_25 -; RV32I-NEXT: # %bb.23: -; RV32I-NEXT: mv a0, s8 -; RV32I-NEXT: bgeu t3, t1, .LBB11_26 -; RV32I-NEXT: .LBB11_24: -; RV32I-NEXT: lw a4, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a6, a4 +; RV32I-NEXT: and a4, s11, s2 ; RV32I-NEXT: or a0, a4, a0 -; RV32I-NEXT: mv a4, s0 -; RV32I-NEXT: bnez t3, .LBB11_27 -; RV32I-NEXT: j .LBB11_28 +; RV32I-NEXT: mv a4, s9 +; RV32I-NEXT: bnez s0, .LBB11_25 +; RV32I-NEXT: j .LBB11_26 +; RV32I-NEXT: .LBB11_23: +; RV32I-NEXT: srl a4, t4, a4 +; RV32I-NEXT: sub a5, a7, s0 +; RV32I-NEXT: not a5, a5 +; RV32I-NEXT: sll a0, a0, a5 +; RV32I-NEXT: or a0, a4, a0 +; RV32I-NEXT: bltu s0, a7, .LBB11_22 +; RV32I-NEXT: .LBB11_24: +; RV32I-NEXT: lw a0, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a0, a0, a6 +; RV32I-NEXT: mv a4, s9 +; RV32I-NEXT: beqz s0, .LBB11_26 ; RV32I-NEXT: .LBB11_25: -; RV32I-NEXT: srl a0, t0, a0 -; RV32I-NEXT: sub a4, t1, t3 -; RV32I-NEXT: xori a4, a4, 31 -; RV32I-NEXT: lw t5, 52(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a4, t5, a4 -; RV32I-NEXT: or a0, a0, a4 -; RV32I-NEXT: bltu t3, t1, .LBB11_24 -; RV32I-NEXT: .LBB11_26: -; RV32I-NEXT: lw a0, 44(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a0, s6 -; RV32I-NEXT: mv a4, s0 -; RV32I-NEXT: beqz t3, .LBB11_28 -; RV32I-NEXT: .LBB11_27: ; RV32I-NEXT: mv a4, a0 +; RV32I-NEXT: .LBB11_26: +; RV32I-NEXT: sw t3, 20(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz t5, .LBB11_28 +; RV32I-NEXT: # %bb.27: +; RV32I-NEXT: lw t6, 56(sp) # 4-byte Folded Reload ; RV32I-NEXT: .LBB11_28: -; RV32I-NEXT: bltz t6, .LBB11_30 +; RV32I-NEXT: mv t3, t0 +; RV32I-NEXT: lw a0, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a0, .LBB11_30 ; RV32I-NEXT: # %bb.29: -; RV32I-NEXT: lw a6, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: j .LBB11_31 +; RV32I-NEXT: mv t3, s6 ; RV32I-NEXT: .LBB11_30: -; RV32I-NEXT: sll a0, s11, s1 -; RV32I-NEXT: or a6, ra, a0 -; RV32I-NEXT: .LBB11_31: -; RV32I-NEXT: li ra, 128 -; RV32I-NEXT: lw a0, 84(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz a0, .LBB11_33 -; RV32I-NEXT: # %bb.32: -; RV32I-NEXT: mv t5, a5 -; RV32I-NEXT: j .LBB11_34 -; RV32I-NEXT: .LBB11_33: -; RV32I-NEXT: lw a0, 68(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw t4, 20(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a0, a0, t4 -; RV32I-NEXT: lw t5, 72(sp) # 4-byte Folded Reload -; RV32I-NEXT: or t5, t5, a0 +; RV32I-NEXT: sltiu a5, a1, 64 +; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: srai a0, a0, 31 +; RV32I-NEXT: bltu s4, a7, .LBB11_32 +; RV32I-NEXT: # %bb.31: +; RV32I-NEXT: mv t3, a0 +; RV32I-NEXT: .LBB11_32: +; RV32I-NEXT: neg s1, a5 +; RV32I-NEXT: li a5, 128 +; RV32I-NEXT: bgeu a1, a5, .LBB11_34 +; RV32I-NEXT: # %bb.33: +; RV32I-NEXT: and a5, s1, t6 +; RV32I-NEXT: or t3, a5, a4 ; RV32I-NEXT: .LBB11_34: -; RV32I-NEXT: sltiu a0, a1, 64 -; RV32I-NEXT: lw t4, 32(sp) # 4-byte Folded Reload -; RV32I-NEXT: srai s11, t4, 31 -; RV32I-NEXT: bltu s5, t1, .LBB11_36 +; RV32I-NEXT: mv a4, s8 +; RV32I-NEXT: beqz a1, .LBB11_36 ; RV32I-NEXT: # %bb.35: -; RV32I-NEXT: mv t5, s11 +; RV32I-NEXT: mv a4, t3 ; RV32I-NEXT: .LBB11_36: -; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: sw s1, 48(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgeu a1, ra, .LBB11_38 +; RV32I-NEXT: sw a4, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: sub a4, a7, a1 +; RV32I-NEXT: not t3, a4 +; RV32I-NEXT: lw a4, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgez a4, .LBB11_38 ; RV32I-NEXT: # %bb.37: -; RV32I-NEXT: and a0, a0, a6 -; RV32I-NEXT: or t5, a0, a4 +; RV32I-NEXT: lw a4, 44(sp) # 4-byte Folded Reload +; RV32I-NEXT: sll a4, a4, ra +; RV32I-NEXT: srli a5, s8, 1 +; RV32I-NEXT: srl a5, a5, t3 +; RV32I-NEXT: or s10, a4, a5 ; RV32I-NEXT: .LBB11_38: -; RV32I-NEXT: sw s8, 20(sp) # 4-byte Folded Spill -; RV32I-NEXT: mv s1, s7 -; RV32I-NEXT: beqz a1, .LBB11_40 +; RV32I-NEXT: slti a4, t5, 0 +; RV32I-NEXT: neg s5, a4 +; RV32I-NEXT: li t2, 64 +; RV32I-NEXT: bltu a1, a7, .LBB11_40 ; RV32I-NEXT: # %bb.39: -; RV32I-NEXT: mv s1, t5 +; RV32I-NEXT: lw a4, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: slti a4, a4, 0 +; RV32I-NEXT: neg a4, a4 +; RV32I-NEXT: lw a5, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a4, a4, a5 +; RV32I-NEXT: j .LBB11_41 ; RV32I-NEXT: .LBB11_40: -; RV32I-NEXT: sub a0, t1, a1 -; RV32I-NEXT: xori s9, a0, 31 -; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgez a0, .LBB11_42 -; RV32I-NEXT: # %bb.41: -; RV32I-NEXT: sll a0, s3, a7 -; RV32I-NEXT: srli a4, s7, 1 -; RV32I-NEXT: srl a4, a4, s9 -; RV32I-NEXT: or s10, a0, a4 -; RV32I-NEXT: .LBB11_42: -; RV32I-NEXT: slti a0, t6, 0 -; RV32I-NEXT: neg s8, a0 -; RV32I-NEXT: bltu a1, t1, .LBB11_44 -; RV32I-NEXT: # %bb.43: -; RV32I-NEXT: lw a0, 60(sp) # 4-byte Folded Reload -; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: lw a4, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a0, a4 -; RV32I-NEXT: mv a6, s4 -; RV32I-NEXT: bnez a1, .LBB11_45 +; RV32I-NEXT: lw a4, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a4, s5, a4 +; RV32I-NEXT: or a4, a4, s10 +; RV32I-NEXT: .LBB11_41: +; RV32I-NEXT: sw t0, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv a7, t1 +; RV32I-NEXT: beqz a1, .LBB11_43 +; RV32I-NEXT: # %bb.42: +; RV32I-NEXT: mv a7, a4 +; RV32I-NEXT: .LBB11_43: +; RV32I-NEXT: mv s10, t3 +; RV32I-NEXT: sll a4, a3, ra +; RV32I-NEXT: srli s8, t4, 1 +; RV32I-NEXT: not t3, s0 +; RV32I-NEXT: mv t0, s7 +; RV32I-NEXT: bltz s7, .LBB11_45 +; RV32I-NEXT: # %bb.44: +; RV32I-NEXT: mv s7, t5 +; RV32I-NEXT: mv s11, a6 ; RV32I-NEXT: j .LBB11_46 -; RV32I-NEXT: .LBB11_44: -; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, s8, a0 -; RV32I-NEXT: or a0, a0, s10 -; RV32I-NEXT: mv a6, s4 -; RV32I-NEXT: beqz a1, .LBB11_46 ; RV32I-NEXT: .LBB11_45: -; RV32I-NEXT: mv a6, a0 +; RV32I-NEXT: mv s7, t5 +; RV32I-NEXT: srl a5, s8, t3 +; RV32I-NEXT: or s11, a4, a5 ; RV32I-NEXT: .LBB11_46: -; RV32I-NEXT: sll s10, a3, a7 -; RV32I-NEXT: srli a4, t0, 1 -; RV32I-NEXT: xori t4, t3, 31 -; RV32I-NEXT: bltz s2, .LBB11_48 +; RV32I-NEXT: mv t5, t1 +; RV32I-NEXT: mv t6, s3 +; RV32I-NEXT: lw a5, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: sll s3, a5, ra +; RV32I-NEXT: srli s9, s9, 1 +; RV32I-NEXT: lw a5, 28(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a5, .LBB11_48 ; RV32I-NEXT: # %bb.47: -; RV32I-NEXT: mv t5, s6 +; RV32I-NEXT: mv t1, s9 +; RV32I-NEXT: mv s9, s3 +; RV32I-NEXT: mv s3, s2 ; RV32I-NEXT: j .LBB11_49 ; RV32I-NEXT: .LBB11_48: -; RV32I-NEXT: srl a0, a4, t4 -; RV32I-NEXT: or t5, s10, a0 +; RV32I-NEXT: li a5, 192 +; RV32I-NEXT: sub a5, a5, a1 +; RV32I-NEXT: not a5, a5 +; RV32I-NEXT: mv t1, s9 +; RV32I-NEXT: srl a5, s9, a5 +; RV32I-NEXT: mv s9, s3 +; RV32I-NEXT: or s3, s3, a5 ; RV32I-NEXT: .LBB11_49: -; RV32I-NEXT: lw a0, 76(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll s7, a0, a7 -; RV32I-NEXT: srli s0, s0, 1 -; RV32I-NEXT: lw a0, 36(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw s7, 32(sp) # 4-byte Folded Spill -; RV32I-NEXT: mv a7, s9 -; RV32I-NEXT: bltz a0, .LBB11_51 +; RV32I-NEXT: mv a5, s6 +; RV32I-NEXT: lw ra, 32(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz ra, .LBB11_51 ; RV32I-NEXT: # %bb.50: -; RV32I-NEXT: lw s7, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: j .LBB11_52 +; RV32I-NEXT: mv a5, a0 ; RV32I-NEXT: .LBB11_51: -; RV32I-NEXT: li a0, 192 -; RV32I-NEXT: sub a0, a0, a1 -; RV32I-NEXT: xori a0, a0, 31 -; RV32I-NEXT: srl a0, s0, a0 -; RV32I-NEXT: or s7, s7, a0 -; RV32I-NEXT: .LBB11_52: -; RV32I-NEXT: mv a0, a5 -; RV32I-NEXT: lw s9, 40(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgez s9, .LBB11_60 -; RV32I-NEXT: # %bb.53: -; RV32I-NEXT: bltu s5, t1, .LBB11_61 +; RV32I-NEXT: bltu s4, t2, .LBB11_53 +; RV32I-NEXT: # %bb.52: +; RV32I-NEXT: mv t2, s2 +; RV32I-NEXT: j .LBB11_54 +; RV32I-NEXT: .LBB11_53: +; RV32I-NEXT: lw a5, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: slti a5, a5, 0 +; RV32I-NEXT: neg a5, a5 +; RV32I-NEXT: lw t2, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a5, a5, t2 +; RV32I-NEXT: lw t2, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: or a5, a5, s3 ; RV32I-NEXT: .LBB11_54: -; RV32I-NEXT: mv s7, a3 -; RV32I-NEXT: bnez s5, .LBB11_62 -; RV32I-NEXT: .LBB11_55: -; RV32I-NEXT: bltu a1, ra, .LBB11_63 +; RV32I-NEXT: mv s2, s1 +; RV32I-NEXT: mv ra, s9 +; RV32I-NEXT: mv s3, a3 +; RV32I-NEXT: mv s9, t1 +; RV32I-NEXT: beqz s4, .LBB11_56 +; RV32I-NEXT: # %bb.55: +; RV32I-NEXT: mv s3, a5 ; RV32I-NEXT: .LBB11_56: -; RV32I-NEXT: bnez a1, .LBB11_64 -; RV32I-NEXT: .LBB11_57: -; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz a0, .LBB11_65 +; RV32I-NEXT: li a5, 128 +; RV32I-NEXT: mv t1, t5 +; RV32I-NEXT: bltu a1, a5, .LBB11_61 +; RV32I-NEXT: # %bb.57: +; RV32I-NEXT: li a7, 64 +; RV32I-NEXT: bnez a1, .LBB11_62 ; RV32I-NEXT: .LBB11_58: -; RV32I-NEXT: lw t5, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz s2, .LBB11_66 +; RV32I-NEXT: lw a5, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a5, .LBB11_63 ; RV32I-NEXT: .LBB11_59: -; RV32I-NEXT: mv a0, t5 -; RV32I-NEXT: bltu t3, t1, .LBB11_67 -; RV32I-NEXT: j .LBB11_68 +; RV32I-NEXT: bltz t0, .LBB11_64 ; RV32I-NEXT: .LBB11_60: -; RV32I-NEXT: mv a0, s11 -; RV32I-NEXT: bgeu s5, t1, .LBB11_54 +; RV32I-NEXT: mv a4, t2 +; RV32I-NEXT: j .LBB11_65 ; RV32I-NEXT: .LBB11_61: -; RV32I-NEXT: lw a0, 84(sp) # 4-byte Folded Reload -; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: lw ra, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a0, ra -; RV32I-NEXT: li ra, 128 -; RV32I-NEXT: or a0, a0, s7 -; RV32I-NEXT: mv s7, a3 -; RV32I-NEXT: beqz s5, .LBB11_55 +; RV32I-NEXT: lw a5, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a5, a5, s11 +; RV32I-NEXT: or s3, a7, a5 +; RV32I-NEXT: li a7, 64 +; RV32I-NEXT: beqz a1, .LBB11_58 ; RV32I-NEXT: .LBB11_62: -; RV32I-NEXT: mv s7, a0 -; RV32I-NEXT: bgeu a1, ra, .LBB11_56 +; RV32I-NEXT: mv t1, s3 +; RV32I-NEXT: lw a5, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgez a5, .LBB11_59 ; RV32I-NEXT: .LBB11_63: -; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a0, t5 -; RV32I-NEXT: or s7, a6, a0 -; RV32I-NEXT: beqz a1, .LBB11_57 +; RV32I-NEXT: srl s1, s8, s10 +; RV32I-NEXT: or a6, a4, s1 +; RV32I-NEXT: bgez t0, .LBB11_60 ; RV32I-NEXT: .LBB11_64: -; RV32I-NEXT: mv s4, s7 -; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgez a0, .LBB11_58 +; RV32I-NEXT: srl a4, s9, t3 +; RV32I-NEXT: or a4, ra, a4 ; RV32I-NEXT: .LBB11_65: -; RV32I-NEXT: srl a0, a4, a7 -; RV32I-NEXT: or s6, s10, a0 -; RV32I-NEXT: lw t5, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgez s2, .LBB11_59 -; RV32I-NEXT: .LBB11_66: -; RV32I-NEXT: srl a0, s0, t4 -; RV32I-NEXT: lw a4, 32(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a0, a4, a0 -; RV32I-NEXT: bgeu t3, t1, .LBB11_68 +; RV32I-NEXT: lw t3, 20(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t0, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgeu s0, a7, .LBB11_67 +; RV32I-NEXT: # %bb.66: +; RV32I-NEXT: lw a5, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: slti a5, a5, 0 +; RV32I-NEXT: neg a5, a5 +; RV32I-NEXT: and s1, a5, t3 +; RV32I-NEXT: or a6, a4, s1 ; RV32I-NEXT: .LBB11_67: -; RV32I-NEXT: lw a4, 16(sp) # 4-byte Folded Reload -; RV32I-NEXT: slti a4, a4, 0 -; RV32I-NEXT: neg a4, a4 -; RV32I-NEXT: lw a6, 20(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a4, a6 -; RV32I-NEXT: or s6, a0, a4 -; RV32I-NEXT: .LBB11_68: -; RV32I-NEXT: lw a6, 72(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw t4, 68(sp) # 4-byte Folded Reload -; RV32I-NEXT: beqz t3, .LBB11_70 -; RV32I-NEXT: # %bb.69: -; RV32I-NEXT: sw s6, 76(sp) # 4-byte Folded Spill -; RV32I-NEXT: .LBB11_70: -; RV32I-NEXT: mv a4, a5 -; RV32I-NEXT: lw a0, 84(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgez a0, .LBB11_77 -; RV32I-NEXT: # %bb.71: -; RV32I-NEXT: lw t3, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgeu s5, t1, .LBB11_78 -; RV32I-NEXT: .LBB11_72: -; RV32I-NEXT: bltu a1, ra, .LBB11_79 +; RV32I-NEXT: beqz s0, .LBB11_69 +; RV32I-NEXT: # %bb.68: +; RV32I-NEXT: sw a6, 60(sp) # 4-byte Folded Spill +; RV32I-NEXT: .LBB11_69: +; RV32I-NEXT: mv a4, s6 +; RV32I-NEXT: lw a5, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a5, .LBB11_71 +; RV32I-NEXT: # %bb.70: +; RV32I-NEXT: mv a4, a0 +; RV32I-NEXT: .LBB11_71: +; RV32I-NEXT: li t3, 128 +; RV32I-NEXT: lw s0, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a6, 44(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgeu s4, a7, .LBB11_92 +; RV32I-NEXT: # %bb.72: +; RV32I-NEXT: bltu a1, t3, .LBB11_93 ; RV32I-NEXT: .LBB11_73: -; RV32I-NEXT: lw s5, 60(sp) # 4-byte Folded Reload -; RV32I-NEXT: bnez a1, .LBB11_80 +; RV32I-NEXT: bnez a1, .LBB11_94 ; RV32I-NEXT: .LBB11_74: -; RV32I-NEXT: bltz s5, .LBB11_81 +; RV32I-NEXT: mv a4, t0 +; RV32I-NEXT: bgez s0, .LBB11_95 ; RV32I-NEXT: .LBB11_75: -; RV32I-NEXT: mv a4, a5 -; RV32I-NEXT: bgez t6, .LBB11_82 +; RV32I-NEXT: bgez s7, .LBB11_96 ; RV32I-NEXT: .LBB11_76: -; RV32I-NEXT: lw a0, 52(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 48(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a0, a0, s2 -; RV32I-NEXT: lw s2, 28(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a0, s2, a0 -; RV32I-NEXT: bltu a1, t1, .LBB11_83 -; RV32I-NEXT: j .LBB11_84 +; RV32I-NEXT: bltu a1, a7, .LBB11_97 ; RV32I-NEXT: .LBB11_77: -; RV32I-NEXT: mv a4, s11 -; RV32I-NEXT: lw t3, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltu s5, t1, .LBB11_72 +; RV32I-NEXT: bnez a1, .LBB11_98 ; RV32I-NEXT: .LBB11_78: -; RV32I-NEXT: mv a4, s11 -; RV32I-NEXT: bgeu a1, ra, .LBB11_73 +; RV32I-NEXT: bgeu a1, t3, .LBB11_99 ; RV32I-NEXT: .LBB11_79: -; RV32I-NEXT: lw a0, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, s8, a0 -; RV32I-NEXT: lw a4, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a4, a0 -; RV32I-NEXT: lw a4, 76(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a4, a0, a4 -; RV32I-NEXT: lw s5, 60(sp) # 4-byte Folded Reload -; RV32I-NEXT: beqz a1, .LBB11_74 +; RV32I-NEXT: lw a4, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a4, .LBB11_100 ; RV32I-NEXT: .LBB11_80: -; RV32I-NEXT: mv s3, a4 -; RV32I-NEXT: bgez s5, .LBB11_75 +; RV32I-NEXT: mv a4, s6 +; RV32I-NEXT: bgez s0, .LBB11_101 ; RV32I-NEXT: .LBB11_81: -; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a0, t4, a0 -; RV32I-NEXT: or a4, a6, a0 -; RV32I-NEXT: bltz t6, .LBB11_76 +; RV32I-NEXT: bltu a1, a7, .LBB11_102 ; RV32I-NEXT: .LBB11_82: -; RV32I-NEXT: mv a0, t3 -; RV32I-NEXT: bgeu a1, t1, .LBB11_84 +; RV32I-NEXT: bnez a1, .LBB11_103 ; RV32I-NEXT: .LBB11_83: -; RV32I-NEXT: lw a4, 44(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a4, t5 -; RV32I-NEXT: or a4, a0, a4 +; RV32I-NEXT: bgeu a1, t3, .LBB11_104 ; RV32I-NEXT: .LBB11_84: -; RV32I-NEXT: bnez a1, .LBB11_93 -; RV32I-NEXT: # %bb.85: -; RV32I-NEXT: bgeu a1, ra, .LBB11_94 +; RV32I-NEXT: lw a4, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgez s7, .LBB11_105 +; RV32I-NEXT: .LBB11_85: +; RV32I-NEXT: bgeu a1, a7, .LBB11_106 ; RV32I-NEXT: .LBB11_86: -; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz a0, .LBB11_95 +; RV32I-NEXT: bgeu a1, t3, .LBB11_107 ; RV32I-NEXT: .LBB11_87: -; RV32I-NEXT: mv a0, a5 -; RV32I-NEXT: bgez s5, .LBB11_96 +; RV32I-NEXT: bgez s7, .LBB11_108 ; RV32I-NEXT: .LBB11_88: -; RV32I-NEXT: bltu a1, t1, .LBB11_97 +; RV32I-NEXT: bgeu a1, a7, .LBB11_109 ; RV32I-NEXT: .LBB11_89: -; RV32I-NEXT: bnez a1, .LBB11_98 +; RV32I-NEXT: bltu a1, t3, .LBB11_91 ; RV32I-NEXT: .LBB11_90: -; RV32I-NEXT: bgeu a1, ra, .LBB11_99 +; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: .LBB11_91: -; RV32I-NEXT: bltz t6, .LBB11_100 -; RV32I-NEXT: .LBB11_92: -; RV32I-NEXT: mv a4, a5 -; RV32I-NEXT: bgeu a1, t1, .LBB11_101 -; RV32I-NEXT: j .LBB11_102 -; RV32I-NEXT: .LBB11_93: -; RV32I-NEXT: mv t0, a4 -; RV32I-NEXT: bltu a1, ra, .LBB11_86 -; RV32I-NEXT: .LBB11_94: -; RV32I-NEXT: mv t0, s11 -; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgez a0, .LBB11_87 -; RV32I-NEXT: .LBB11_95: -; RV32I-NEXT: srl a0, s0, a7 -; RV32I-NEXT: lw a4, 32(sp) # 4-byte Folded Reload -; RV32I-NEXT: or t5, a4, a0 -; RV32I-NEXT: mv a0, a5 -; RV32I-NEXT: bltz s5, .LBB11_88 -; RV32I-NEXT: .LBB11_96: -; RV32I-NEXT: mv a0, s11 -; RV32I-NEXT: bgeu a1, t1, .LBB11_89 -; RV32I-NEXT: .LBB11_97: -; RV32I-NEXT: and a0, s8, t3 -; RV32I-NEXT: or a0, a0, t5 -; RV32I-NEXT: beqz a1, .LBB11_90 -; RV32I-NEXT: .LBB11_98: -; RV32I-NEXT: mv a3, a0 -; RV32I-NEXT: bltu a1, ra, .LBB11_91 -; RV32I-NEXT: .LBB11_99: -; RV32I-NEXT: mv a3, s11 -; RV32I-NEXT: bgez t6, .LBB11_92 -; RV32I-NEXT: .LBB11_100: -; RV32I-NEXT: lw a0, 48(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a0, t4, a0 -; RV32I-NEXT: or a4, a6, a0 -; RV32I-NEXT: bltu a1, t1, .LBB11_102 -; RV32I-NEXT: .LBB11_101: -; RV32I-NEXT: mv a4, s11 -; RV32I-NEXT: .LBB11_102: -; RV32I-NEXT: bgeu a1, ra, .LBB11_108 -; RV32I-NEXT: # %bb.103: -; RV32I-NEXT: bgez t6, .LBB11_109 -; RV32I-NEXT: .LBB11_104: -; RV32I-NEXT: bgeu a1, t1, .LBB11_110 -; RV32I-NEXT: .LBB11_105: -; RV32I-NEXT: bltu a1, ra, .LBB11_107 -; RV32I-NEXT: .LBB11_106: -; RV32I-NEXT: mv a5, s11 -; RV32I-NEXT: .LBB11_107: -; RV32I-NEXT: sb a5, 28(a2) -; RV32I-NEXT: srli a0, a5, 24 +; RV32I-NEXT: sb s6, 28(a2) +; RV32I-NEXT: srli a0, s6, 24 ; RV32I-NEXT: sb a0, 31(a2) -; RV32I-NEXT: srli a0, a5, 16 +; RV32I-NEXT: srli a0, s6, 16 ; RV32I-NEXT: sb a0, 30(a2) -; RV32I-NEXT: srli a5, a5, 8 -; RV32I-NEXT: sb a5, 29(a2) -; RV32I-NEXT: sb a4, 24(a2) -; RV32I-NEXT: srli a0, a4, 24 +; RV32I-NEXT: srli a0, s6, 8 +; RV32I-NEXT: sb a0, 29(a2) +; RV32I-NEXT: sb t0, 24(a2) +; RV32I-NEXT: srli a0, t0, 24 ; RV32I-NEXT: sb a0, 27(a2) -; RV32I-NEXT: srli a0, a4, 16 +; RV32I-NEXT: srli a0, t0, 16 ; RV32I-NEXT: sb a0, 26(a2) -; RV32I-NEXT: srli a4, a4, 8 -; RV32I-NEXT: sb a4, 25(a2) -; RV32I-NEXT: sb t0, 16(a2) -; RV32I-NEXT: srli a0, t0, 24 +; RV32I-NEXT: srli a0, t0, 8 +; RV32I-NEXT: sb a0, 25(a2) +; RV32I-NEXT: sb t4, 16(a2) +; RV32I-NEXT: srli a0, t4, 24 ; RV32I-NEXT: sb a0, 19(a2) -; RV32I-NEXT: srli a0, t0, 16 +; RV32I-NEXT: srli a0, t4, 16 ; RV32I-NEXT: sb a0, 18(a2) -; RV32I-NEXT: srli a0, t0, 8 +; RV32I-NEXT: srli a0, t4, 8 ; RV32I-NEXT: sb a0, 17(a2) ; RV32I-NEXT: sb a3, 20(a2) ; RV32I-NEXT: srli a0, a3, 24 @@ -4115,59 +3923,119 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sb a0, 22(a2) ; RV32I-NEXT: srli a3, a3, 8 ; RV32I-NEXT: sb a3, 21(a2) -; RV32I-NEXT: sb t2, 0(a2) -; RV32I-NEXT: sb s3, 12(a2) -; RV32I-NEXT: srli a0, t2, 24 +; RV32I-NEXT: sb t6, 0(a2) +; RV32I-NEXT: sb a6, 12(a2) +; RV32I-NEXT: srli a0, t6, 24 ; RV32I-NEXT: sb a0, 3(a2) -; RV32I-NEXT: srli a0, t2, 16 +; RV32I-NEXT: srli a0, t6, 16 ; RV32I-NEXT: sb a0, 2(a2) -; RV32I-NEXT: srli a0, t2, 8 +; RV32I-NEXT: srli a0, t6, 8 ; RV32I-NEXT: sb a0, 1(a2) -; RV32I-NEXT: sb s4, 4(a2) -; RV32I-NEXT: sb s1, 8(a2) -; RV32I-NEXT: srli a0, s3, 24 +; RV32I-NEXT: sb t1, 4(a2) +; RV32I-NEXT: sb a4, 8(a2) +; RV32I-NEXT: srli a0, a6, 24 ; RV32I-NEXT: sb a0, 15(a2) -; RV32I-NEXT: srli a0, s3, 16 +; RV32I-NEXT: srli a0, a6, 16 ; RV32I-NEXT: sb a0, 14(a2) -; RV32I-NEXT: srli a0, s3, 8 +; RV32I-NEXT: srli a0, a6, 8 ; RV32I-NEXT: sb a0, 13(a2) -; RV32I-NEXT: srli a0, s4, 24 +; RV32I-NEXT: srli a0, t1, 24 ; RV32I-NEXT: sb a0, 7(a2) -; RV32I-NEXT: srli a0, s4, 16 +; RV32I-NEXT: srli a0, t1, 16 ; RV32I-NEXT: sb a0, 6(a2) -; RV32I-NEXT: srli a0, s4, 8 +; RV32I-NEXT: srli a0, t1, 8 ; RV32I-NEXT: sb a0, 5(a2) -; RV32I-NEXT: srli a0, s1, 24 +; RV32I-NEXT: srli a0, a4, 24 ; RV32I-NEXT: sb a0, 11(a2) -; RV32I-NEXT: srli a0, s1, 16 +; RV32I-NEXT: srli a0, a4, 16 ; RV32I-NEXT: sb a0, 10(a2) -; RV32I-NEXT: srli s1, s1, 8 -; RV32I-NEXT: sb s1, 9(a2) -; RV32I-NEXT: lw ra, 140(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 136(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 132(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 128(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s3, 124(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s4, 120(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s5, 116(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s6, 112(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s7, 108(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s8, 104(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s9, 100(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s10, 96(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s11, 92(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 144 +; RV32I-NEXT: srli a0, a4, 8 +; RV32I-NEXT: sb a0, 9(a2) +; RV32I-NEXT: lw ra, 124(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 120(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 116(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 112(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s3, 108(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s4, 104(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s5, 100(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s6, 96(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s7, 92(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s8, 88(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s9, 84(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s10, 80(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s11, 76(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 128 ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB11_92: +; RV32I-NEXT: mv a4, a0 +; RV32I-NEXT: bgeu a1, t3, .LBB11_73 +; RV32I-NEXT: .LBB11_93: +; RV32I-NEXT: lw a4, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a4, s5, a4 +; RV32I-NEXT: and a4, s2, a4 +; RV32I-NEXT: lw a5, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: or a4, a4, a5 +; RV32I-NEXT: beqz a1, .LBB11_74 +; RV32I-NEXT: .LBB11_94: +; RV32I-NEXT: mv a6, a4 +; RV32I-NEXT: mv a4, t0 +; RV32I-NEXT: bltz s0, .LBB11_75 +; RV32I-NEXT: .LBB11_95: +; RV32I-NEXT: mv a4, s6 +; RV32I-NEXT: bltz s7, .LBB11_76 +; RV32I-NEXT: .LBB11_96: +; RV32I-NEXT: lw a5, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a5, 40(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgeu a1, a7, .LBB11_77 +; RV32I-NEXT: .LBB11_97: +; RV32I-NEXT: lw a4, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a4, a4, t2 +; RV32I-NEXT: lw a5, 40(sp) # 4-byte Folded Reload +; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: beqz a1, .LBB11_78 +; RV32I-NEXT: .LBB11_98: +; RV32I-NEXT: mv t4, a4 +; RV32I-NEXT: bltu a1, t3, .LBB11_79 +; RV32I-NEXT: .LBB11_99: +; RV32I-NEXT: mv t4, a0 +; RV32I-NEXT: lw a4, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgez a4, .LBB11_80 +; RV32I-NEXT: .LBB11_100: +; RV32I-NEXT: srl a4, s9, s10 +; RV32I-NEXT: or t2, ra, a4 +; RV32I-NEXT: mv a4, s6 +; RV32I-NEXT: bltz s0, .LBB11_81 +; RV32I-NEXT: .LBB11_101: +; RV32I-NEXT: mv a4, a0 +; RV32I-NEXT: bgeu a1, a7, .LBB11_82 +; RV32I-NEXT: .LBB11_102: +; RV32I-NEXT: lw a4, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a4, s5, a4 +; RV32I-NEXT: or a4, a4, t2 +; RV32I-NEXT: beqz a1, .LBB11_83 +; RV32I-NEXT: .LBB11_103: +; RV32I-NEXT: mv a3, a4 +; RV32I-NEXT: bltu a1, t3, .LBB11_84 +; RV32I-NEXT: .LBB11_104: +; RV32I-NEXT: mv a3, a0 +; RV32I-NEXT: lw a4, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz s7, .LBB11_85 +; RV32I-NEXT: .LBB11_105: +; RV32I-NEXT: mv t0, s6 +; RV32I-NEXT: bltu a1, a7, .LBB11_86 +; RV32I-NEXT: .LBB11_106: +; RV32I-NEXT: mv t0, a0 +; RV32I-NEXT: bltu a1, t3, .LBB11_87 +; RV32I-NEXT: .LBB11_107: +; RV32I-NEXT: mv t0, a0 +; RV32I-NEXT: bltz s7, .LBB11_88 ; RV32I-NEXT: .LBB11_108: -; RV32I-NEXT: mv a4, s11 -; RV32I-NEXT: bltz t6, .LBB11_104 +; RV32I-NEXT: mv s6, a0 +; RV32I-NEXT: bltu a1, a7, .LBB11_89 ; RV32I-NEXT: .LBB11_109: -; RV32I-NEXT: mv a5, s11 -; RV32I-NEXT: bltu a1, t1, .LBB11_105 -; RV32I-NEXT: .LBB11_110: -; RV32I-NEXT: mv a5, s11 -; RV32I-NEXT: bgeu a1, ra, .LBB11_106 -; RV32I-NEXT: j .LBB11_107 +; RV32I-NEXT: mv s6, a0 +; RV32I-NEXT: bgeu a1, t3, .LBB11_90 +; RV32I-NEXT: j .LBB11_91 %src = load i256, ptr %src.ptr, align 1 %byteOff = load i256, ptr %byteOff.ptr, align 1 %bitOff = shl i256 %byteOff, 3 diff --git a/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll b/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll index 9aa6fc47783dc2..a178d87cd75f21 100644 --- a/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll +++ b/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll @@ -291,7 +291,7 @@ define void @lshr_8bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: or a6, t0, a6 ; RV32I-NEXT: or a0, a0, a6 ; RV32I-NEXT: srl a0, a0, a5 -; RV32I-NEXT: xori a5, a5, 31 +; RV32I-NEXT: not a5, a5 ; RV32I-NEXT: slli a3, a3, 1 ; RV32I-NEXT: sll a3, a3, a5 ; RV32I-NEXT: or a0, a0, a3 @@ -425,7 +425,7 @@ define void @shl_8bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: or a6, t0, a6 ; RV32I-NEXT: or a0, a0, a6 ; RV32I-NEXT: sll a0, a0, a5 -; RV32I-NEXT: xori a5, a5, 31 +; RV32I-NEXT: not a5, a5 ; RV32I-NEXT: srli a3, a3, 1 ; RV32I-NEXT: srl a3, a3, a5 ; RV32I-NEXT: or a0, a0, a3 @@ -561,7 +561,7 @@ define void @ashr_8bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: or a5, a7, a5 ; RV32I-NEXT: or a0, a0, a5 ; RV32I-NEXT: srl a0, a0, a4 -; RV32I-NEXT: xori a4, a4, 31 +; RV32I-NEXT: not a4, a4 ; RV32I-NEXT: slli a3, a3, 1 ; RV32I-NEXT: sll a3, a3, a4 ; RV32I-NEXT: or a0, a0, a3 @@ -665,7 +665,7 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: or a0, a0, a6 ; RV64I-NEXT: or a0, a0, t1 ; RV64I-NEXT: srl a0, a0, a5 -; RV64I-NEXT: xori a5, a5, 63 +; RV64I-NEXT: not a5, a5 ; RV64I-NEXT: slli a3, a3, 1 ; RV64I-NEXT: sll a3, a3, a5 ; RV64I-NEXT: or a0, a0, a3 @@ -710,8 +710,6 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: lbu a3, 5(a0) ; RV32I-NEXT: lbu a4, 4(a0) ; RV32I-NEXT: lbu a5, 6(a0) @@ -725,32 +723,32 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: lbu a4, 1(a0) ; RV32I-NEXT: lbu a5, 0(a0) ; RV32I-NEXT: lbu a6, 2(a0) -; RV32I-NEXT: lbu a7, 3(a0) +; RV32I-NEXT: lbu t0, 3(a0) ; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or t0, a4, a5 +; RV32I-NEXT: or a7, a4, a5 ; RV32I-NEXT: slli a6, a6, 16 -; RV32I-NEXT: slli a7, a7, 24 -; RV32I-NEXT: or t1, a7, a6 +; RV32I-NEXT: slli t0, t0, 24 +; RV32I-NEXT: or t2, t0, a6 ; RV32I-NEXT: lbu a4, 13(a0) ; RV32I-NEXT: lbu a5, 12(a0) ; RV32I-NEXT: lbu a6, 14(a0) -; RV32I-NEXT: lbu a7, 15(a0) +; RV32I-NEXT: lbu t0, 15(a0) ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: or a4, a4, a5 ; RV32I-NEXT: slli a6, a6, 16 -; RV32I-NEXT: slli a7, a7, 24 +; RV32I-NEXT: slli t0, t0, 24 ; RV32I-NEXT: or a4, a6, a4 -; RV32I-NEXT: or a7, a7, a4 +; RV32I-NEXT: or a6, t0, a4 ; RV32I-NEXT: lbu a4, 9(a0) ; RV32I-NEXT: lbu a5, 8(a0) -; RV32I-NEXT: lbu a6, 10(a0) +; RV32I-NEXT: lbu t0, 10(a0) ; RV32I-NEXT: lbu a0, 11(a0) ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: or a4, a4, a5 -; RV32I-NEXT: slli a6, a6, 16 +; RV32I-NEXT: slli t0, t0, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a4, a6, a4 -; RV32I-NEXT: or t3, a0, a4 +; RV32I-NEXT: or a4, t0, a4 +; RV32I-NEXT: or t0, a0, a4 ; RV32I-NEXT: lbu a0, 1(a1) ; RV32I-NEXT: lbu a4, 0(a1) ; RV32I-NEXT: lbu a5, 2(a1) @@ -761,99 +759,92 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a1, a1, a0 -; RV32I-NEXT: srl a5, t3, a1 -; RV32I-NEXT: slli a6, a7, 1 -; RV32I-NEXT: addi t2, a1, -96 -; RV32I-NEXT: srl a4, a7, a1 -; RV32I-NEXT: bltz t2, .LBB6_2 +; RV32I-NEXT: srl a0, t0, a1 +; RV32I-NEXT: not t4, a1 +; RV32I-NEXT: slli a4, a6, 1 +; RV32I-NEXT: sll a4, a4, t4 +; RV32I-NEXT: or a4, a0, a4 +; RV32I-NEXT: addi t1, a1, -96 +; RV32I-NEXT: srl a5, a6, a1 +; RV32I-NEXT: mv t3, a4 +; RV32I-NEXT: bltz t1, .LBB6_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: mv t5, a4 -; RV32I-NEXT: j .LBB6_3 +; RV32I-NEXT: mv t3, a5 ; RV32I-NEXT: .LBB6_2: -; RV32I-NEXT: addi a0, a1, -64 -; RV32I-NEXT: xori a0, a0, 31 -; RV32I-NEXT: sll a0, a6, a0 -; RV32I-NEXT: or t5, a5, a0 -; RV32I-NEXT: .LBB6_3: -; RV32I-NEXT: or a0, t1, t0 -; RV32I-NEXT: xori t0, a1, 31 -; RV32I-NEXT: addi t1, a1, -32 -; RV32I-NEXT: srl t4, a3, a1 -; RV32I-NEXT: bltz t1, .LBB6_5 -; RV32I-NEXT: # %bb.4: -; RV32I-NEXT: mv s3, t4 -; RV32I-NEXT: j .LBB6_6 +; RV32I-NEXT: or a0, t2, a7 +; RV32I-NEXT: addi a7, a1, -32 +; RV32I-NEXT: srl t2, a3, a1 +; RV32I-NEXT: bltz a7, .LBB6_4 +; RV32I-NEXT: # %bb.3: +; RV32I-NEXT: mv s1, t2 +; RV32I-NEXT: j .LBB6_5 +; RV32I-NEXT: .LBB6_4: +; RV32I-NEXT: srl t5, a0, a1 +; RV32I-NEXT: slli t6, a3, 1 +; RV32I-NEXT: sll t4, t6, t4 +; RV32I-NEXT: or s1, t5, t4 ; RV32I-NEXT: .LBB6_5: -; RV32I-NEXT: srl t6, a0, a1 -; RV32I-NEXT: slli s0, a3, 1 -; RV32I-NEXT: sll s0, s0, t0 -; RV32I-NEXT: or s3, t6, s0 -; RV32I-NEXT: .LBB6_6: -; RV32I-NEXT: neg s1, a1 -; RV32I-NEXT: sll t6, t3, s1 -; RV32I-NEXT: li s2, 32 -; RV32I-NEXT: li s0, 64 -; RV32I-NEXT: sub s2, s2, a1 -; RV32I-NEXT: bltu a1, s0, .LBB6_12 -; RV32I-NEXT: # %bb.7: -; RV32I-NEXT: bnez a1, .LBB6_13 +; RV32I-NEXT: neg t6, a1 +; RV32I-NEXT: sll t4, t0, t6 +; RV32I-NEXT: li s0, 32 +; RV32I-NEXT: li t5, 64 +; RV32I-NEXT: sub s0, s0, a1 +; RV32I-NEXT: bltu a1, t5, .LBB6_11 +; RV32I-NEXT: # %bb.6: +; RV32I-NEXT: bnez a1, .LBB6_12 +; RV32I-NEXT: .LBB6_7: +; RV32I-NEXT: bgez s0, .LBB6_9 ; RV32I-NEXT: .LBB6_8: -; RV32I-NEXT: bgez s2, .LBB6_10 +; RV32I-NEXT: sll a6, a6, t6 +; RV32I-NEXT: srli t0, t0, 1 +; RV32I-NEXT: sub t3, t5, a1 +; RV32I-NEXT: not t3, t3 +; RV32I-NEXT: srl t0, t0, t3 +; RV32I-NEXT: or t4, a6, t0 ; RV32I-NEXT: .LBB6_9: -; RV32I-NEXT: sll a7, a7, s1 -; RV32I-NEXT: srli t3, t3, 1 -; RV32I-NEXT: sub t5, s0, a1 -; RV32I-NEXT: xori t5, t5, 31 -; RV32I-NEXT: srl t3, t3, t5 -; RV32I-NEXT: or t6, a7, t3 -; RV32I-NEXT: .LBB6_10: -; RV32I-NEXT: slti a7, t1, 0 -; RV32I-NEXT: neg a7, a7 -; RV32I-NEXT: bltu a1, s0, .LBB6_14 -; RV32I-NEXT: # %bb.11: -; RV32I-NEXT: slti t2, t2, 0 -; RV32I-NEXT: neg t2, t2 -; RV32I-NEXT: and t2, t2, a4 -; RV32I-NEXT: bnez a1, .LBB6_15 -; RV32I-NEXT: j .LBB6_16 +; RV32I-NEXT: slti a6, a7, 0 +; RV32I-NEXT: neg a6, a6 +; RV32I-NEXT: bltu a1, t5, .LBB6_13 +; RV32I-NEXT: # %bb.10: +; RV32I-NEXT: slti t0, t1, 0 +; RV32I-NEXT: neg t0, t0 +; RV32I-NEXT: and t0, t0, a5 +; RV32I-NEXT: bnez a1, .LBB6_14 +; RV32I-NEXT: j .LBB6_15 +; RV32I-NEXT: .LBB6_11: +; RV32I-NEXT: slti t3, s0, 0 +; RV32I-NEXT: neg t3, t3 +; RV32I-NEXT: and t3, t3, t4 +; RV32I-NEXT: or t3, s1, t3 +; RV32I-NEXT: beqz a1, .LBB6_7 ; RV32I-NEXT: .LBB6_12: -; RV32I-NEXT: slti t5, s2, 0 -; RV32I-NEXT: neg t5, t5 -; RV32I-NEXT: and t5, t5, t6 -; RV32I-NEXT: or t5, s3, t5 -; RV32I-NEXT: beqz a1, .LBB6_8 +; RV32I-NEXT: mv a0, t3 +; RV32I-NEXT: bltz s0, .LBB6_8 +; RV32I-NEXT: j .LBB6_9 ; RV32I-NEXT: .LBB6_13: -; RV32I-NEXT: mv a0, t5 -; RV32I-NEXT: bltz s2, .LBB6_9 -; RV32I-NEXT: j .LBB6_10 +; RV32I-NEXT: and t0, a6, t2 +; RV32I-NEXT: or t0, t0, t4 +; RV32I-NEXT: beqz a1, .LBB6_15 ; RV32I-NEXT: .LBB6_14: -; RV32I-NEXT: and t2, a7, t4 -; RV32I-NEXT: or t2, t2, t6 -; RV32I-NEXT: beqz a1, .LBB6_16 +; RV32I-NEXT: mv a3, t0 ; RV32I-NEXT: .LBB6_15: -; RV32I-NEXT: mv a3, t2 -; RV32I-NEXT: .LBB6_16: -; RV32I-NEXT: bltz t1, .LBB6_18 -; RV32I-NEXT: # %bb.17: -; RV32I-NEXT: mv a5, a4 -; RV32I-NEXT: j .LBB6_19 -; RV32I-NEXT: .LBB6_18: -; RV32I-NEXT: sll a6, a6, t0 -; RV32I-NEXT: or a5, a5, a6 -; RV32I-NEXT: .LBB6_19: +; RV32I-NEXT: bltz a7, .LBB6_17 +; RV32I-NEXT: # %bb.16: +; RV32I-NEXT: mv a4, a5 +; RV32I-NEXT: .LBB6_17: ; RV32I-NEXT: sltiu a1, a1, 64 ; RV32I-NEXT: neg a1, a1 -; RV32I-NEXT: and a5, a1, a5 -; RV32I-NEXT: and a4, a7, a4 -; RV32I-NEXT: and a1, a1, a4 -; RV32I-NEXT: sb a5, 8(a2) +; RV32I-NEXT: and a4, a1, a4 +; RV32I-NEXT: and a5, a6, a5 +; RV32I-NEXT: and a1, a1, a5 +; RV32I-NEXT: sb a4, 8(a2) ; RV32I-NEXT: sb a1, 12(a2) -; RV32I-NEXT: srli a4, a5, 16 -; RV32I-NEXT: sb a4, 10(a2) -; RV32I-NEXT: srli a4, a5, 24 -; RV32I-NEXT: sb a4, 11(a2) -; RV32I-NEXT: srli a5, a5, 8 -; RV32I-NEXT: sb a5, 9(a2) +; RV32I-NEXT: srli a5, a4, 16 +; RV32I-NEXT: sb a5, 10(a2) +; RV32I-NEXT: srli a5, a4, 24 +; RV32I-NEXT: sb a5, 11(a2) +; RV32I-NEXT: srli a4, a4, 8 +; RV32I-NEXT: sb a4, 9(a2) ; RV32I-NEXT: srli a4, a1, 16 ; RV32I-NEXT: sb a4, 14(a2) ; RV32I-NEXT: srli a4, a1, 24 @@ -876,8 +867,6 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sb a3, 5(a2) ; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s3, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret %src = load i128, ptr %src.ptr, align 1 @@ -963,7 +952,7 @@ define void @shl_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: or a0, a0, a6 ; RV64I-NEXT: or a0, a0, t1 ; RV64I-NEXT: sll a0, a0, a5 -; RV64I-NEXT: xori a5, a5, 63 +; RV64I-NEXT: not a5, a5 ; RV64I-NEXT: srli a3, a3, 1 ; RV64I-NEXT: srl a3, a3, a5 ; RV64I-NEXT: or a0, a0, a3 @@ -1008,8 +997,6 @@ define void @shl_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: lbu a3, 9(a0) ; RV32I-NEXT: lbu a4, 8(a0) ; RV32I-NEXT: lbu a5, 10(a0) @@ -1023,32 +1010,32 @@ define void @shl_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: lbu a4, 13(a0) ; RV32I-NEXT: lbu a5, 12(a0) ; RV32I-NEXT: lbu a6, 14(a0) -; RV32I-NEXT: lbu a7, 15(a0) +; RV32I-NEXT: lbu t0, 15(a0) ; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or t0, a4, a5 +; RV32I-NEXT: or a7, a4, a5 ; RV32I-NEXT: slli a6, a6, 16 -; RV32I-NEXT: slli a7, a7, 24 -; RV32I-NEXT: or t1, a7, a6 +; RV32I-NEXT: slli t0, t0, 24 +; RV32I-NEXT: or t2, t0, a6 ; RV32I-NEXT: lbu a4, 1(a0) ; RV32I-NEXT: lbu a5, 0(a0) ; RV32I-NEXT: lbu a6, 2(a0) -; RV32I-NEXT: lbu a7, 3(a0) +; RV32I-NEXT: lbu t0, 3(a0) ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: or a4, a4, a5 ; RV32I-NEXT: slli a6, a6, 16 -; RV32I-NEXT: slli a7, a7, 24 +; RV32I-NEXT: slli t0, t0, 24 ; RV32I-NEXT: or a4, a6, a4 -; RV32I-NEXT: or a7, a7, a4 +; RV32I-NEXT: or a6, t0, a4 ; RV32I-NEXT: lbu a4, 5(a0) ; RV32I-NEXT: lbu a5, 4(a0) -; RV32I-NEXT: lbu a6, 6(a0) +; RV32I-NEXT: lbu t0, 6(a0) ; RV32I-NEXT: lbu a0, 7(a0) ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: or a4, a4, a5 -; RV32I-NEXT: slli a6, a6, 16 +; RV32I-NEXT: slli t0, t0, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a4, a6, a4 -; RV32I-NEXT: or t3, a0, a4 +; RV32I-NEXT: or a4, t0, a4 +; RV32I-NEXT: or t0, a0, a4 ; RV32I-NEXT: lbu a0, 1(a1) ; RV32I-NEXT: lbu a4, 0(a1) ; RV32I-NEXT: lbu a5, 2(a1) @@ -1059,105 +1046,98 @@ define void @shl_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a1, a1, a0 -; RV32I-NEXT: sll a5, t3, a1 -; RV32I-NEXT: srli a6, a7, 1 -; RV32I-NEXT: addi t2, a1, -96 -; RV32I-NEXT: sll a4, a7, a1 -; RV32I-NEXT: bltz t2, .LBB7_2 +; RV32I-NEXT: sll a0, t0, a1 +; RV32I-NEXT: not t4, a1 +; RV32I-NEXT: srli a4, a6, 1 +; RV32I-NEXT: srl a4, a4, t4 +; RV32I-NEXT: or a4, a0, a4 +; RV32I-NEXT: addi t1, a1, -96 +; RV32I-NEXT: sll a5, a6, a1 +; RV32I-NEXT: mv t3, a4 +; RV32I-NEXT: bltz t1, .LBB7_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: mv t5, a4 -; RV32I-NEXT: j .LBB7_3 +; RV32I-NEXT: mv t3, a5 ; RV32I-NEXT: .LBB7_2: -; RV32I-NEXT: addi a0, a1, -64 -; RV32I-NEXT: xori a0, a0, 31 -; RV32I-NEXT: srl a0, a6, a0 -; RV32I-NEXT: or t5, a5, a0 -; RV32I-NEXT: .LBB7_3: -; RV32I-NEXT: or a0, t1, t0 -; RV32I-NEXT: xori t0, a1, 31 -; RV32I-NEXT: addi t1, a1, -32 -; RV32I-NEXT: sll t4, a3, a1 -; RV32I-NEXT: bltz t1, .LBB7_5 -; RV32I-NEXT: # %bb.4: -; RV32I-NEXT: mv s3, t4 -; RV32I-NEXT: j .LBB7_6 +; RV32I-NEXT: or a0, t2, a7 +; RV32I-NEXT: addi a7, a1, -32 +; RV32I-NEXT: sll t2, a3, a1 +; RV32I-NEXT: bltz a7, .LBB7_4 +; RV32I-NEXT: # %bb.3: +; RV32I-NEXT: mv s1, t2 +; RV32I-NEXT: j .LBB7_5 +; RV32I-NEXT: .LBB7_4: +; RV32I-NEXT: sll t5, a0, a1 +; RV32I-NEXT: srli t6, a3, 1 +; RV32I-NEXT: srl t4, t6, t4 +; RV32I-NEXT: or s1, t5, t4 ; RV32I-NEXT: .LBB7_5: -; RV32I-NEXT: sll t6, a0, a1 -; RV32I-NEXT: srli s0, a3, 1 -; RV32I-NEXT: srl s0, s0, t0 -; RV32I-NEXT: or s3, t6, s0 -; RV32I-NEXT: .LBB7_6: -; RV32I-NEXT: neg s1, a1 -; RV32I-NEXT: srl t6, t3, s1 -; RV32I-NEXT: li s2, 32 -; RV32I-NEXT: li s0, 64 -; RV32I-NEXT: sub s2, s2, a1 -; RV32I-NEXT: bltu a1, s0, .LBB7_12 -; RV32I-NEXT: # %bb.7: -; RV32I-NEXT: bnez a1, .LBB7_13 +; RV32I-NEXT: neg t6, a1 +; RV32I-NEXT: srl t4, t0, t6 +; RV32I-NEXT: li s0, 32 +; RV32I-NEXT: li t5, 64 +; RV32I-NEXT: sub s0, s0, a1 +; RV32I-NEXT: bltu a1, t5, .LBB7_11 +; RV32I-NEXT: # %bb.6: +; RV32I-NEXT: bnez a1, .LBB7_12 +; RV32I-NEXT: .LBB7_7: +; RV32I-NEXT: bgez s0, .LBB7_9 ; RV32I-NEXT: .LBB7_8: -; RV32I-NEXT: bgez s2, .LBB7_10 +; RV32I-NEXT: srl a6, a6, t6 +; RV32I-NEXT: slli t0, t0, 1 +; RV32I-NEXT: sub t3, t5, a1 +; RV32I-NEXT: not t3, t3 +; RV32I-NEXT: sll t0, t0, t3 +; RV32I-NEXT: or t4, a6, t0 ; RV32I-NEXT: .LBB7_9: -; RV32I-NEXT: srl a7, a7, s1 -; RV32I-NEXT: slli t3, t3, 1 -; RV32I-NEXT: sub t5, s0, a1 -; RV32I-NEXT: xori t5, t5, 31 -; RV32I-NEXT: sll t3, t3, t5 -; RV32I-NEXT: or t6, a7, t3 -; RV32I-NEXT: .LBB7_10: -; RV32I-NEXT: slti a7, t1, 0 -; RV32I-NEXT: neg a7, a7 -; RV32I-NEXT: bltu a1, s0, .LBB7_14 -; RV32I-NEXT: # %bb.11: -; RV32I-NEXT: slti t2, t2, 0 -; RV32I-NEXT: neg t2, t2 -; RV32I-NEXT: and t2, t2, a4 -; RV32I-NEXT: bnez a1, .LBB7_15 -; RV32I-NEXT: j .LBB7_16 +; RV32I-NEXT: slti a6, a7, 0 +; RV32I-NEXT: neg a6, a6 +; RV32I-NEXT: bltu a1, t5, .LBB7_13 +; RV32I-NEXT: # %bb.10: +; RV32I-NEXT: slti t0, t1, 0 +; RV32I-NEXT: neg t0, t0 +; RV32I-NEXT: and t0, t0, a5 +; RV32I-NEXT: bnez a1, .LBB7_14 +; RV32I-NEXT: j .LBB7_15 +; RV32I-NEXT: .LBB7_11: +; RV32I-NEXT: slti t3, s0, 0 +; RV32I-NEXT: neg t3, t3 +; RV32I-NEXT: and t3, t3, t4 +; RV32I-NEXT: or t3, s1, t3 +; RV32I-NEXT: beqz a1, .LBB7_7 ; RV32I-NEXT: .LBB7_12: -; RV32I-NEXT: slti t5, s2, 0 -; RV32I-NEXT: neg t5, t5 -; RV32I-NEXT: and t5, t5, t6 -; RV32I-NEXT: or t5, s3, t5 -; RV32I-NEXT: beqz a1, .LBB7_8 +; RV32I-NEXT: mv a0, t3 +; RV32I-NEXT: bltz s0, .LBB7_8 +; RV32I-NEXT: j .LBB7_9 ; RV32I-NEXT: .LBB7_13: -; RV32I-NEXT: mv a0, t5 -; RV32I-NEXT: bltz s2, .LBB7_9 -; RV32I-NEXT: j .LBB7_10 +; RV32I-NEXT: and t0, a6, t2 +; RV32I-NEXT: or t0, t0, t4 +; RV32I-NEXT: beqz a1, .LBB7_15 ; RV32I-NEXT: .LBB7_14: -; RV32I-NEXT: and t2, a7, t4 -; RV32I-NEXT: or t2, t2, t6 -; RV32I-NEXT: beqz a1, .LBB7_16 +; RV32I-NEXT: mv a3, t0 ; RV32I-NEXT: .LBB7_15: -; RV32I-NEXT: mv a3, t2 -; RV32I-NEXT: .LBB7_16: -; RV32I-NEXT: bltz t1, .LBB7_18 -; RV32I-NEXT: # %bb.17: -; RV32I-NEXT: mv a5, a4 -; RV32I-NEXT: j .LBB7_19 -; RV32I-NEXT: .LBB7_18: -; RV32I-NEXT: srl a6, a6, t0 -; RV32I-NEXT: or a5, a5, a6 -; RV32I-NEXT: .LBB7_19: +; RV32I-NEXT: bltz a7, .LBB7_17 +; RV32I-NEXT: # %bb.16: +; RV32I-NEXT: mv a4, a5 +; RV32I-NEXT: .LBB7_17: ; RV32I-NEXT: sltiu a1, a1, 64 ; RV32I-NEXT: neg a1, a1 -; RV32I-NEXT: and a5, a1, a5 -; RV32I-NEXT: and a4, a7, a4 -; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: and a4, a1, a4 +; RV32I-NEXT: and a5, a6, a5 +; RV32I-NEXT: and a1, a1, a5 ; RV32I-NEXT: sb a1, 0(a2) -; RV32I-NEXT: sb a5, 4(a2) -; RV32I-NEXT: srli a4, a1, 16 -; RV32I-NEXT: sb a4, 2(a2) -; RV32I-NEXT: srli a4, a1, 24 -; RV32I-NEXT: sb a4, 3(a2) +; RV32I-NEXT: sb a4, 4(a2) +; RV32I-NEXT: srli a5, a1, 16 +; RV32I-NEXT: sb a5, 2(a2) +; RV32I-NEXT: srli a5, a1, 24 +; RV32I-NEXT: sb a5, 3(a2) ; RV32I-NEXT: srli a1, a1, 8 ; RV32I-NEXT: sb a1, 1(a2) -; RV32I-NEXT: srli a1, a5, 16 +; RV32I-NEXT: srli a1, a4, 16 ; RV32I-NEXT: sb a1, 6(a2) -; RV32I-NEXT: srli a1, a5, 24 +; RV32I-NEXT: srli a1, a4, 24 ; RV32I-NEXT: sb a1, 7(a2) -; RV32I-NEXT: srli a5, a5, 8 -; RV32I-NEXT: sb a5, 5(a2) +; RV32I-NEXT: srli a4, a4, 8 +; RV32I-NEXT: sb a4, 5(a2) ; RV32I-NEXT: sb a0, 12(a2) ; RV32I-NEXT: sb a3, 8(a2) ; RV32I-NEXT: srli a1, a0, 16 @@ -1174,8 +1154,6 @@ define void @shl_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sb a3, 9(a2) ; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s3, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret %src = load i128, ptr %src.ptr, align 1 @@ -1263,7 +1241,7 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: or a0, a0, a4 ; RV64I-NEXT: or a0, a0, t0 ; RV64I-NEXT: srl a0, a0, a5 -; RV64I-NEXT: xori a4, a5, 63 +; RV64I-NEXT: not a4, a5 ; RV64I-NEXT: slli a3, a3, 1 ; RV64I-NEXT: sll a3, a3, a4 ; RV64I-NEXT: or a0, a0, a3 @@ -1302,12 +1280,10 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; ; RV32I-LABEL: ashr_16bytes: ; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -32 -; RV32I-NEXT: sw s0, 28(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 24(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 20(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 16(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s4, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: lbu a3, 5(a0) ; RV32I-NEXT: lbu a4, 4(a0) ; RV32I-NEXT: lbu a5, 6(a0) @@ -1320,33 +1296,33 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: or a3, a6, a3 ; RV32I-NEXT: lbu a4, 1(a0) ; RV32I-NEXT: lbu a5, 0(a0) -; RV32I-NEXT: lbu a6, 2(a0) +; RV32I-NEXT: lbu a7, 2(a0) ; RV32I-NEXT: lbu t0, 3(a0) ; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a7, a4, a5 -; RV32I-NEXT: slli a6, a6, 16 +; RV32I-NEXT: or a6, a4, a5 +; RV32I-NEXT: slli a7, a7, 16 ; RV32I-NEXT: slli t0, t0, 24 -; RV32I-NEXT: or t1, t0, a6 +; RV32I-NEXT: or t0, t0, a7 ; RV32I-NEXT: lbu a4, 13(a0) ; RV32I-NEXT: lbu a5, 12(a0) -; RV32I-NEXT: lbu a6, 14(a0) -; RV32I-NEXT: lbu t0, 15(a0) +; RV32I-NEXT: lbu a7, 14(a0) +; RV32I-NEXT: lbu t1, 15(a0) ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: or a4, a4, a5 -; RV32I-NEXT: slli a6, a6, 16 -; RV32I-NEXT: slli t0, t0, 24 -; RV32I-NEXT: or a4, a6, a4 -; RV32I-NEXT: or t3, t0, a4 +; RV32I-NEXT: slli a5, a7, 16 +; RV32I-NEXT: slli a7, t1, 24 +; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: or t1, a7, a4 ; RV32I-NEXT: lbu a4, 9(a0) ; RV32I-NEXT: lbu a5, 8(a0) -; RV32I-NEXT: lbu a6, 10(a0) +; RV32I-NEXT: lbu t2, 10(a0) ; RV32I-NEXT: lbu a0, 11(a0) ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: or a4, a4, a5 -; RV32I-NEXT: slli a6, a6, 16 +; RV32I-NEXT: slli t2, t2, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a4, a6, a4 -; RV32I-NEXT: or t4, a0, a4 +; RV32I-NEXT: or a4, t2, a4 +; RV32I-NEXT: or t2, a0, a4 ; RV32I-NEXT: lbu a0, 1(a1) ; RV32I-NEXT: lbu a4, 0(a1) ; RV32I-NEXT: lbu a5, 2(a1) @@ -1356,122 +1332,89 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: or a0, a5, a0 -; RV32I-NEXT: or a4, a1, a0 -; RV32I-NEXT: srl a5, t4, a4 -; RV32I-NEXT: slli a6, t3, 1 -; RV32I-NEXT: addi t5, a4, -96 -; RV32I-NEXT: sra a1, t3, a4 -; RV32I-NEXT: bltz t5, .LBB8_2 +; RV32I-NEXT: or a5, a1, a0 +; RV32I-NEXT: srl a0, t2, a5 +; RV32I-NEXT: not t5, a5 +; RV32I-NEXT: slli a1, t1, 1 +; RV32I-NEXT: sll a1, a1, t5 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: addi t3, a5, -96 +; RV32I-NEXT: sra a4, t1, a5 +; RV32I-NEXT: mv t6, a0 +; RV32I-NEXT: bltz t3, .LBB8_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: mv s1, a1 -; RV32I-NEXT: j .LBB8_3 +; RV32I-NEXT: mv t6, a4 ; RV32I-NEXT: .LBB8_2: -; RV32I-NEXT: addi a0, a4, -64 -; RV32I-NEXT: xori a0, a0, 31 -; RV32I-NEXT: sll s1, a6, a0 -; RV32I-NEXT: or s1, a5, s1 -; RV32I-NEXT: .LBB8_3: -; RV32I-NEXT: or a0, t1, a7 -; RV32I-NEXT: xori t2, a4, 31 -; RV32I-NEXT: addi a7, a4, -32 -; RV32I-NEXT: srl t6, a3, a4 -; RV32I-NEXT: bltz a7, .LBB8_5 -; RV32I-NEXT: # %bb.4: -; RV32I-NEXT: mv s4, t6 -; RV32I-NEXT: j .LBB8_6 -; RV32I-NEXT: .LBB8_5: -; RV32I-NEXT: srl t1, a0, a4 +; RV32I-NEXT: or a1, t0, a6 +; RV32I-NEXT: addi a6, a5, -32 +; RV32I-NEXT: srl t4, a3, a5 +; RV32I-NEXT: bltz a6, .LBB8_4 +; RV32I-NEXT: # %bb.3: +; RV32I-NEXT: mv s2, t4 +; RV32I-NEXT: j .LBB8_5 +; RV32I-NEXT: .LBB8_4: +; RV32I-NEXT: srl t0, a1, a5 ; RV32I-NEXT: slli s0, a3, 1 -; RV32I-NEXT: sll s0, s0, t2 -; RV32I-NEXT: or s4, t1, s0 -; RV32I-NEXT: .LBB8_6: -; RV32I-NEXT: neg s2, a4 -; RV32I-NEXT: sll s0, t4, s2 -; RV32I-NEXT: li s3, 32 -; RV32I-NEXT: li t1, 64 -; RV32I-NEXT: sub s3, s3, a4 -; RV32I-NEXT: bltu a4, t1, .LBB8_15 -; RV32I-NEXT: # %bb.7: -; RV32I-NEXT: bnez a4, .LBB8_16 +; RV32I-NEXT: sll t5, s0, t5 +; RV32I-NEXT: or s2, t0, t5 +; RV32I-NEXT: .LBB8_5: +; RV32I-NEXT: neg s0, a5 +; RV32I-NEXT: sll t5, t2, s0 +; RV32I-NEXT: li s1, 32 +; RV32I-NEXT: li t0, 64 +; RV32I-NEXT: sub s1, s1, a5 +; RV32I-NEXT: bltu a5, t0, .LBB8_18 +; RV32I-NEXT: # %bb.6: +; RV32I-NEXT: bnez a5, .LBB8_19 +; RV32I-NEXT: .LBB8_7: +; RV32I-NEXT: bgez s1, .LBB8_9 ; RV32I-NEXT: .LBB8_8: -; RV32I-NEXT: bgez s3, .LBB8_10 +; RV32I-NEXT: sll t1, t1, s0 +; RV32I-NEXT: srli t2, t2, 1 +; RV32I-NEXT: sub t5, t0, a5 +; RV32I-NEXT: not t5, t5 +; RV32I-NEXT: srl t2, t2, t5 +; RV32I-NEXT: or t5, t1, t2 ; RV32I-NEXT: .LBB8_9: -; RV32I-NEXT: sll t3, t3, s2 -; RV32I-NEXT: srli t4, t4, 1 -; RV32I-NEXT: sub s0, t1, a4 -; RV32I-NEXT: xori s0, s0, 31 -; RV32I-NEXT: srl t4, t4, s0 -; RV32I-NEXT: or s0, t3, t4 -; RV32I-NEXT: .LBB8_10: -; RV32I-NEXT: srai t0, t0, 31 -; RV32I-NEXT: mv t3, a1 -; RV32I-NEXT: bgez t5, .LBB8_17 -; RV32I-NEXT: # %bb.11: -; RV32I-NEXT: bltu a4, t1, .LBB8_18 +; RV32I-NEXT: srai a7, a7, 31 +; RV32I-NEXT: mv t1, a4 +; RV32I-NEXT: bgez t3, .LBB8_20 +; RV32I-NEXT: # %bb.10: +; RV32I-NEXT: bltu a5, t0, .LBB8_21 +; RV32I-NEXT: .LBB8_11: +; RV32I-NEXT: bnez a5, .LBB8_22 ; RV32I-NEXT: .LBB8_12: -; RV32I-NEXT: bnez a4, .LBB8_19 +; RV32I-NEXT: bgez a6, .LBB8_23 ; RV32I-NEXT: .LBB8_13: -; RV32I-NEXT: bltz a7, .LBB8_20 +; RV32I-NEXT: bgeu a5, t0, .LBB8_24 ; RV32I-NEXT: .LBB8_14: -; RV32I-NEXT: mv a5, a1 -; RV32I-NEXT: bgeu a4, t1, .LBB8_21 -; RV32I-NEXT: j .LBB8_22 +; RV32I-NEXT: bgez a6, .LBB8_25 ; RV32I-NEXT: .LBB8_15: -; RV32I-NEXT: slti s1, s3, 0 -; RV32I-NEXT: neg s1, s1 -; RV32I-NEXT: and s1, s1, s0 -; RV32I-NEXT: or s1, s4, s1 -; RV32I-NEXT: beqz a4, .LBB8_8 +; RV32I-NEXT: bltu a5, t0, .LBB8_17 ; RV32I-NEXT: .LBB8_16: -; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: bltz s3, .LBB8_9 -; RV32I-NEXT: j .LBB8_10 +; RV32I-NEXT: mv a4, a7 ; RV32I-NEXT: .LBB8_17: -; RV32I-NEXT: mv t3, t0 -; RV32I-NEXT: bgeu a4, t1, .LBB8_12 -; RV32I-NEXT: .LBB8_18: -; RV32I-NEXT: slti t3, a7, 0 -; RV32I-NEXT: neg t3, t3 -; RV32I-NEXT: and t3, t3, t6 -; RV32I-NEXT: or t3, t3, s0 -; RV32I-NEXT: beqz a4, .LBB8_13 -; RV32I-NEXT: .LBB8_19: -; RV32I-NEXT: mv a3, t3 -; RV32I-NEXT: bgez a7, .LBB8_14 -; RV32I-NEXT: .LBB8_20: -; RV32I-NEXT: sll a6, a6, t2 -; RV32I-NEXT: or a5, a5, a6 -; RV32I-NEXT: bltu a4, t1, .LBB8_22 -; RV32I-NEXT: .LBB8_21: -; RV32I-NEXT: mv a5, t0 -; RV32I-NEXT: .LBB8_22: -; RV32I-NEXT: bgez a7, .LBB8_26 -; RV32I-NEXT: # %bb.23: -; RV32I-NEXT: bltu a4, t1, .LBB8_25 -; RV32I-NEXT: .LBB8_24: -; RV32I-NEXT: mv a1, t0 -; RV32I-NEXT: .LBB8_25: -; RV32I-NEXT: sb a1, 12(a2) -; RV32I-NEXT: srli a4, a1, 16 -; RV32I-NEXT: sb a4, 14(a2) -; RV32I-NEXT: srli a4, a1, 24 -; RV32I-NEXT: sb a4, 15(a2) -; RV32I-NEXT: srli a1, a1, 8 -; RV32I-NEXT: sb a1, 13(a2) -; RV32I-NEXT: sb a5, 8(a2) -; RV32I-NEXT: srli a1, a5, 16 -; RV32I-NEXT: sb a1, 10(a2) -; RV32I-NEXT: srli a1, a5, 24 -; RV32I-NEXT: sb a1, 11(a2) -; RV32I-NEXT: srli a5, a5, 8 -; RV32I-NEXT: sb a5, 9(a2) -; RV32I-NEXT: sb a0, 0(a2) -; RV32I-NEXT: srli a1, a0, 16 -; RV32I-NEXT: sb a1, 2(a2) -; RV32I-NEXT: srli a1, a0, 24 -; RV32I-NEXT: sb a1, 3(a2) +; RV32I-NEXT: sb a4, 12(a2) +; RV32I-NEXT: srli a5, a4, 16 +; RV32I-NEXT: sb a5, 14(a2) +; RV32I-NEXT: srli a5, a4, 24 +; RV32I-NEXT: sb a5, 15(a2) +; RV32I-NEXT: srli a4, a4, 8 +; RV32I-NEXT: sb a4, 13(a2) +; RV32I-NEXT: sb a0, 8(a2) +; RV32I-NEXT: srli a4, a0, 16 +; RV32I-NEXT: sb a4, 10(a2) +; RV32I-NEXT: srli a4, a0, 24 +; RV32I-NEXT: sb a4, 11(a2) ; RV32I-NEXT: srli a0, a0, 8 -; RV32I-NEXT: sb a0, 1(a2) +; RV32I-NEXT: sb a0, 9(a2) +; RV32I-NEXT: sb a1, 0(a2) +; RV32I-NEXT: srli a0, a1, 16 +; RV32I-NEXT: sb a0, 2(a2) +; RV32I-NEXT: srli a0, a1, 24 +; RV32I-NEXT: sb a0, 3(a2) +; RV32I-NEXT: srli a1, a1, 8 +; RV32I-NEXT: sb a1, 1(a2) ; RV32I-NEXT: sb a3, 4(a2) ; RV32I-NEXT: srli a0, a3, 16 ; RV32I-NEXT: sb a0, 6(a2) @@ -1479,17 +1422,43 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sb a0, 7(a2) ; RV32I-NEXT: srli a3, a3, 8 ; RV32I-NEXT: sb a3, 5(a2) -; RV32I-NEXT: lw s0, 28(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 24(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 20(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s3, 16(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s4, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 32 +; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB8_26: -; RV32I-NEXT: mv a1, t0 -; RV32I-NEXT: bgeu a4, t1, .LBB8_24 -; RV32I-NEXT: j .LBB8_25 +; RV32I-NEXT: .LBB8_18: +; RV32I-NEXT: slti t6, s1, 0 +; RV32I-NEXT: neg t6, t6 +; RV32I-NEXT: and t6, t6, t5 +; RV32I-NEXT: or t6, s2, t6 +; RV32I-NEXT: beqz a5, .LBB8_7 +; RV32I-NEXT: .LBB8_19: +; RV32I-NEXT: mv a1, t6 +; RV32I-NEXT: bltz s1, .LBB8_8 +; RV32I-NEXT: j .LBB8_9 +; RV32I-NEXT: .LBB8_20: +; RV32I-NEXT: mv t1, a7 +; RV32I-NEXT: bgeu a5, t0, .LBB8_11 +; RV32I-NEXT: .LBB8_21: +; RV32I-NEXT: slti t1, a6, 0 +; RV32I-NEXT: neg t1, t1 +; RV32I-NEXT: and t1, t1, t4 +; RV32I-NEXT: or t1, t1, t5 +; RV32I-NEXT: beqz a5, .LBB8_12 +; RV32I-NEXT: .LBB8_22: +; RV32I-NEXT: mv a3, t1 +; RV32I-NEXT: bltz a6, .LBB8_13 +; RV32I-NEXT: .LBB8_23: +; RV32I-NEXT: mv a0, a4 +; RV32I-NEXT: bltu a5, t0, .LBB8_14 +; RV32I-NEXT: .LBB8_24: +; RV32I-NEXT: mv a0, a7 +; RV32I-NEXT: bltz a6, .LBB8_15 +; RV32I-NEXT: .LBB8_25: +; RV32I-NEXT: mv a4, a7 +; RV32I-NEXT: bgeu a5, t0, .LBB8_16 +; RV32I-NEXT: j .LBB8_17 %src = load i128, ptr %src.ptr, align 1 %bitOff = load i128, ptr %bitOff.ptr, align 1 %res = ashr i128 %src, %bitOff @@ -1500,11 +1469,9 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-LABEL: lshr_32bytes: ; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -32 -; RV64I-NEXT: sd s0, 24(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s1, 16(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s2, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s3, 0(sp) # 8-byte Folded Spill +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd s0, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s1, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: lbu a3, 9(a0) ; RV64I-NEXT: lbu a4, 8(a0) ; RV64I-NEXT: lbu a5, 10(a0) @@ -1536,185 +1503,178 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a6, a6, 16 ; RV64I-NEXT: slli a7, a7, 24 ; RV64I-NEXT: or a4, a6, a4 -; RV64I-NEXT: or a6, a7, a4 +; RV64I-NEXT: or a5, a7, a4 ; RV64I-NEXT: lbu a4, 5(a0) -; RV64I-NEXT: lbu a5, 4(a0) +; RV64I-NEXT: lbu a6, 4(a0) ; RV64I-NEXT: lbu a7, 6(a0) ; RV64I-NEXT: lbu t0, 7(a0) ; RV64I-NEXT: slli a4, a4, 8 -; RV64I-NEXT: or a4, a4, a5 +; RV64I-NEXT: or a4, a4, a6 ; RV64I-NEXT: slli a7, a7, 16 ; RV64I-NEXT: slli t0, t0, 24 ; RV64I-NEXT: or a4, a7, a4 -; RV64I-NEXT: or a4, t0, a4 -; RV64I-NEXT: lbu a5, 25(a0) -; RV64I-NEXT: lbu a7, 24(a0) -; RV64I-NEXT: lbu t0, 26(a0) +; RV64I-NEXT: or t0, t0, a4 +; RV64I-NEXT: slli t0, t0, 32 +; RV64I-NEXT: lbu a4, 25(a0) +; RV64I-NEXT: lbu a6, 24(a0) +; RV64I-NEXT: lbu a7, 26(a0) ; RV64I-NEXT: lbu t1, 27(a0) -; RV64I-NEXT: slli a5, a5, 8 -; RV64I-NEXT: or a5, a5, a7 -; RV64I-NEXT: slli t0, t0, 16 +; RV64I-NEXT: slli a4, a4, 8 +; RV64I-NEXT: or a4, a4, a6 +; RV64I-NEXT: slli a7, a7, 16 ; RV64I-NEXT: slli t1, t1, 24 -; RV64I-NEXT: or a5, t0, a5 -; RV64I-NEXT: lbu a7, 29(a0) -; RV64I-NEXT: lbu t0, 28(a0) +; RV64I-NEXT: or a4, a7, a4 +; RV64I-NEXT: lbu a6, 29(a0) +; RV64I-NEXT: lbu a7, 28(a0) ; RV64I-NEXT: lbu t2, 30(a0) ; RV64I-NEXT: lbu t3, 31(a0) -; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a7, a7, t0 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: or a6, a6, a7 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or a7, t2, a7 -; RV64I-NEXT: or a7, t3, a7 -; RV64I-NEXT: slli a7, a7, 32 -; RV64I-NEXT: or a5, a7, a5 -; RV64I-NEXT: lbu a7, 17(a0) -; RV64I-NEXT: lbu t0, 16(a0) -; RV64I-NEXT: lbu t2, 18(a0) -; RV64I-NEXT: or a5, a5, t1 -; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a7, a7, t0 -; RV64I-NEXT: slli t2, t2, 16 -; RV64I-NEXT: lbu t0, 21(a0) -; RV64I-NEXT: lbu t1, 19(a0) -; RV64I-NEXT: or a7, t2, a7 -; RV64I-NEXT: lbu t2, 20(a0) -; RV64I-NEXT: slli t0, t0, 8 +; RV64I-NEXT: or a6, t2, a6 +; RV64I-NEXT: or a6, t3, a6 +; RV64I-NEXT: slli a6, a6, 32 +; RV64I-NEXT: or a4, a6, a4 +; RV64I-NEXT: or a4, a4, t1 +; RV64I-NEXT: lbu a6, 17(a0) +; RV64I-NEXT: lbu a7, 16(a0) +; RV64I-NEXT: lbu t1, 18(a0) +; RV64I-NEXT: lbu t2, 19(a0) +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: or a6, a6, a7 +; RV64I-NEXT: slli t1, t1, 16 +; RV64I-NEXT: slli t2, t2, 24 +; RV64I-NEXT: or a6, t1, a6 +; RV64I-NEXT: lbu a7, 21(a0) +; RV64I-NEXT: lbu t1, 20(a0) ; RV64I-NEXT: lbu t3, 22(a0) ; RV64I-NEXT: lbu a0, 23(a0) -; RV64I-NEXT: or t0, t0, t2 -; RV64I-NEXT: slli t1, t1, 24 +; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: or a7, a7, t1 ; RV64I-NEXT: slli t3, t3, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or t0, t3, t0 -; RV64I-NEXT: or a0, a0, t0 -; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: or a7, t3, a7 ; RV64I-NEXT: or a0, a0, a7 -; RV64I-NEXT: lbu a7, 1(a1) -; RV64I-NEXT: lbu t0, 0(a1) -; RV64I-NEXT: lbu t2, 2(a1) -; RV64I-NEXT: or t1, a0, t1 -; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a0, a7, t0 -; RV64I-NEXT: slli t2, t2, 16 -; RV64I-NEXT: lbu a7, 5(a1) -; RV64I-NEXT: lbu t0, 4(a1) -; RV64I-NEXT: or t2, t2, a0 -; RV64I-NEXT: lbu t3, 3(a1) -; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a7, a7, t0 -; RV64I-NEXT: lbu t0, 6(a1) +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: or t1, a0, t2 +; RV64I-NEXT: lbu a0, 1(a1) +; RV64I-NEXT: lbu a6, 0(a1) +; RV64I-NEXT: lbu a7, 2(a1) +; RV64I-NEXT: lbu t2, 3(a1) +; RV64I-NEXT: slli a0, a0, 8 +; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: slli a7, a7, 16 +; RV64I-NEXT: slli t2, t2, 24 +; RV64I-NEXT: or a0, a7, a0 +; RV64I-NEXT: lbu a6, 5(a1) +; RV64I-NEXT: lbu a7, 4(a1) +; RV64I-NEXT: lbu t3, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli a0, a4, 32 -; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: slli t0, t0, 16 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: or a6, a6, a7 +; RV64I-NEXT: slli t3, t3, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a4, t0, a7 -; RV64I-NEXT: or a1, a1, a4 +; RV64I-NEXT: or a6, t3, a6 +; RV64I-NEXT: or a1, a1, a6 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a1, a1, t2 -; RV64I-NEXT: or a1, a1, t3 -; RV64I-NEXT: srl a7, t1, a1 -; RV64I-NEXT: slli t0, a5, 1 -; RV64I-NEXT: addi t3, a1, -192 -; RV64I-NEXT: srl a4, a5, a1 -; RV64I-NEXT: bltz t3, .LBB9_2 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: or a1, a0, t2 +; RV64I-NEXT: srl a0, t1, a1 +; RV64I-NEXT: not t4, a1 +; RV64I-NEXT: slli a6, a4, 1 +; RV64I-NEXT: sll a6, a6, t4 +; RV64I-NEXT: or a6, a0, a6 +; RV64I-NEXT: addi t2, a1, -192 +; RV64I-NEXT: srl a7, a4, a1 +; RV64I-NEXT: mv t3, a6 +; RV64I-NEXT: bltz t2, .LBB9_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv t5, a4 -; RV64I-NEXT: j .LBB9_3 +; RV64I-NEXT: mv t3, a7 ; RV64I-NEXT: .LBB9_2: -; RV64I-NEXT: addiw t2, a1, -128 -; RV64I-NEXT: xori t2, t2, 63 -; RV64I-NEXT: sll t2, t0, t2 -; RV64I-NEXT: or t5, a7, t2 -; RV64I-NEXT: .LBB9_3: -; RV64I-NEXT: or a0, a0, a6 -; RV64I-NEXT: xori a6, a1, 63 -; RV64I-NEXT: addi t2, a1, -64 -; RV64I-NEXT: srl t4, a3, a1 -; RV64I-NEXT: bltz t2, .LBB9_5 -; RV64I-NEXT: # %bb.4: -; RV64I-NEXT: mv s3, t4 -; RV64I-NEXT: j .LBB9_6 +; RV64I-NEXT: or a0, t0, a5 +; RV64I-NEXT: addi a5, a1, -64 +; RV64I-NEXT: srl t0, a3, a1 +; RV64I-NEXT: bltz a5, .LBB9_4 +; RV64I-NEXT: # %bb.3: +; RV64I-NEXT: mv s1, t0 +; RV64I-NEXT: j .LBB9_5 +; RV64I-NEXT: .LBB9_4: +; RV64I-NEXT: srl t5, a0, a1 +; RV64I-NEXT: slli t6, a3, 1 +; RV64I-NEXT: sll t4, t6, t4 +; RV64I-NEXT: or s1, t5, t4 ; RV64I-NEXT: .LBB9_5: -; RV64I-NEXT: srl t6, a0, a1 -; RV64I-NEXT: slli s0, a3, 1 -; RV64I-NEXT: sll s0, s0, a6 -; RV64I-NEXT: or s3, t6, s0 -; RV64I-NEXT: .LBB9_6: -; RV64I-NEXT: negw s1, a1 -; RV64I-NEXT: sll t6, t1, s1 -; RV64I-NEXT: li s2, 64 -; RV64I-NEXT: li s0, 128 -; RV64I-NEXT: sub s2, s2, a1 -; RV64I-NEXT: bltu a1, s0, .LBB9_12 -; RV64I-NEXT: # %bb.7: -; RV64I-NEXT: bnez a1, .LBB9_13 +; RV64I-NEXT: negw t6, a1 +; RV64I-NEXT: sll t4, t1, t6 +; RV64I-NEXT: li s0, 64 +; RV64I-NEXT: li t5, 128 +; RV64I-NEXT: sub s0, s0, a1 +; RV64I-NEXT: bltu a1, t5, .LBB9_11 +; RV64I-NEXT: # %bb.6: +; RV64I-NEXT: bnez a1, .LBB9_12 +; RV64I-NEXT: .LBB9_7: +; RV64I-NEXT: bgez s0, .LBB9_9 ; RV64I-NEXT: .LBB9_8: -; RV64I-NEXT: bgez s2, .LBB9_10 -; RV64I-NEXT: .LBB9_9: -; RV64I-NEXT: sll a5, a5, s1 +; RV64I-NEXT: sll a4, a4, t6 ; RV64I-NEXT: srli t1, t1, 1 -; RV64I-NEXT: subw t5, s0, a1 -; RV64I-NEXT: xori t5, t5, 63 -; RV64I-NEXT: srl t1, t1, t5 -; RV64I-NEXT: or t6, a5, t1 -; RV64I-NEXT: .LBB9_10: -; RV64I-NEXT: slti a5, t2, 0 -; RV64I-NEXT: neg a5, a5 -; RV64I-NEXT: bltu a1, s0, .LBB9_14 -; RV64I-NEXT: # %bb.11: -; RV64I-NEXT: slti t1, t3, 0 -; RV64I-NEXT: neg t1, t1 -; RV64I-NEXT: and t1, t1, a4 -; RV64I-NEXT: bnez a1, .LBB9_15 -; RV64I-NEXT: j .LBB9_16 +; RV64I-NEXT: subw t3, t5, a1 +; RV64I-NEXT: not t3, t3 +; RV64I-NEXT: srl t1, t1, t3 +; RV64I-NEXT: or t4, a4, t1 +; RV64I-NEXT: .LBB9_9: +; RV64I-NEXT: slti a4, a5, 0 +; RV64I-NEXT: neg a4, a4 +; RV64I-NEXT: bltu a1, t5, .LBB9_13 +; RV64I-NEXT: # %bb.10: +; RV64I-NEXT: slti t0, t2, 0 +; RV64I-NEXT: neg t0, t0 +; RV64I-NEXT: and t0, t0, a7 +; RV64I-NEXT: bnez a1, .LBB9_14 +; RV64I-NEXT: j .LBB9_15 +; RV64I-NEXT: .LBB9_11: +; RV64I-NEXT: slti t3, s0, 0 +; RV64I-NEXT: neg t3, t3 +; RV64I-NEXT: and t3, t3, t4 +; RV64I-NEXT: or t3, s1, t3 +; RV64I-NEXT: beqz a1, .LBB9_7 ; RV64I-NEXT: .LBB9_12: -; RV64I-NEXT: slti t5, s2, 0 -; RV64I-NEXT: neg t5, t5 -; RV64I-NEXT: and t5, t5, t6 -; RV64I-NEXT: or t5, s3, t5 -; RV64I-NEXT: beqz a1, .LBB9_8 +; RV64I-NEXT: mv a0, t3 +; RV64I-NEXT: bltz s0, .LBB9_8 +; RV64I-NEXT: j .LBB9_9 ; RV64I-NEXT: .LBB9_13: -; RV64I-NEXT: mv a0, t5 -; RV64I-NEXT: bltz s2, .LBB9_9 -; RV64I-NEXT: j .LBB9_10 +; RV64I-NEXT: and t0, a4, t0 +; RV64I-NEXT: or t0, t0, t4 +; RV64I-NEXT: beqz a1, .LBB9_15 ; RV64I-NEXT: .LBB9_14: -; RV64I-NEXT: and t1, a5, t4 -; RV64I-NEXT: or t1, t1, t6 -; RV64I-NEXT: beqz a1, .LBB9_16 +; RV64I-NEXT: mv a3, t0 ; RV64I-NEXT: .LBB9_15: -; RV64I-NEXT: mv a3, t1 -; RV64I-NEXT: .LBB9_16: -; RV64I-NEXT: bltz t2, .LBB9_18 -; RV64I-NEXT: # %bb.17: -; RV64I-NEXT: mv a6, a4 -; RV64I-NEXT: j .LBB9_19 -; RV64I-NEXT: .LBB9_18: -; RV64I-NEXT: sll a6, t0, a6 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: .LBB9_19: +; RV64I-NEXT: bltz a5, .LBB9_17 +; RV64I-NEXT: # %bb.16: +; RV64I-NEXT: mv a6, a7 +; RV64I-NEXT: .LBB9_17: ; RV64I-NEXT: sltiu a1, a1, 128 ; RV64I-NEXT: neg a1, a1 -; RV64I-NEXT: and a6, a1, a6 -; RV64I-NEXT: and a4, a5, a4 +; RV64I-NEXT: and a5, a1, a6 +; RV64I-NEXT: and a4, a4, a7 ; RV64I-NEXT: and a1, a1, a4 -; RV64I-NEXT: sb a6, 16(a2) +; RV64I-NEXT: sb a5, 16(a2) ; RV64I-NEXT: sb a1, 24(a2) -; RV64I-NEXT: srli a4, a6, 56 +; RV64I-NEXT: srli a4, a5, 56 ; RV64I-NEXT: sb a4, 23(a2) -; RV64I-NEXT: srli a4, a6, 48 +; RV64I-NEXT: srli a4, a5, 48 ; RV64I-NEXT: sb a4, 22(a2) -; RV64I-NEXT: srli a4, a6, 40 +; RV64I-NEXT: srli a4, a5, 40 ; RV64I-NEXT: sb a4, 21(a2) -; RV64I-NEXT: srli a4, a6, 32 +; RV64I-NEXT: srli a4, a5, 32 ; RV64I-NEXT: sb a4, 20(a2) -; RV64I-NEXT: srli a4, a6, 24 +; RV64I-NEXT: srli a4, a5, 24 ; RV64I-NEXT: sb a4, 19(a2) -; RV64I-NEXT: srli a4, a6, 16 +; RV64I-NEXT: srli a4, a5, 16 ; RV64I-NEXT: sb a4, 18(a2) -; RV64I-NEXT: srli a4, a6, 8 -; RV64I-NEXT: sb a4, 17(a2) +; RV64I-NEXT: srli a5, a5, 8 +; RV64I-NEXT: sb a5, 17(a2) ; RV64I-NEXT: srli a4, a1, 56 ; RV64I-NEXT: sb a4, 31(a2) ; RV64I-NEXT: srli a4, a1, 48 @@ -1759,596 +1719,572 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: sb a0, 10(a2) ; RV64I-NEXT: srli a3, a3, 8 ; RV64I-NEXT: sb a3, 9(a2) -; RV64I-NEXT: ld s0, 24(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s1, 16(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s2, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s3, 0(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 32 +; RV64I-NEXT: ld s0, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s1, 0(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; ; RV32I-LABEL: lshr_32bytes: ; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -144 -; RV32I-NEXT: sw ra, 140(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 136(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 132(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 128(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 124(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s4, 120(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s5, 116(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s6, 112(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s7, 108(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s8, 104(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s9, 100(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s10, 96(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s11, 92(sp) # 4-byte Folded Spill -; RV32I-NEXT: lbu a7, 4(a0) +; RV32I-NEXT: addi sp, sp, -112 +; RV32I-NEXT: sw ra, 108(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 104(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 100(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 96(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s3, 92(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s4, 88(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s5, 84(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s6, 80(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s7, 76(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s8, 72(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s9, 68(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s10, 64(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s11, 60(sp) # 4-byte Folded Spill +; RV32I-NEXT: lbu a6, 4(a0) ; RV32I-NEXT: lbu t4, 5(a0) -; RV32I-NEXT: lbu t5, 6(a0) +; RV32I-NEXT: lbu t6, 6(a0) ; RV32I-NEXT: lbu s0, 7(a0) -; RV32I-NEXT: lbu t0, 0(a0) -; RV32I-NEXT: lbu t1, 1(a0) -; RV32I-NEXT: lbu t2, 2(a0) +; RV32I-NEXT: lbu a7, 0(a0) +; RV32I-NEXT: lbu t0, 1(a0) +; RV32I-NEXT: lbu t1, 2(a0) ; RV32I-NEXT: lbu t3, 3(a0) ; RV32I-NEXT: lbu s1, 12(a0) -; RV32I-NEXT: lbu t6, 13(a0) +; RV32I-NEXT: lbu t5, 13(a0) ; RV32I-NEXT: lbu s3, 14(a0) -; RV32I-NEXT: lbu s4, 15(a0) +; RV32I-NEXT: lbu s5, 15(a0) ; RV32I-NEXT: lbu s2, 8(a0) -; RV32I-NEXT: lbu s5, 9(a0) -; RV32I-NEXT: lbu s6, 10(a0) -; RV32I-NEXT: lbu s7, 11(a0) +; RV32I-NEXT: lbu s7, 9(a0) +; RV32I-NEXT: lbu s8, 10(a0) +; RV32I-NEXT: lbu s9, 11(a0) ; RV32I-NEXT: lbu a3, 21(a0) ; RV32I-NEXT: lbu a4, 20(a0) ; RV32I-NEXT: lbu a5, 22(a0) -; RV32I-NEXT: lbu a6, 23(a0) +; RV32I-NEXT: lbu t2, 23(a0) ; RV32I-NEXT: slli a3, a3, 8 ; RV32I-NEXT: or a3, a3, a4 ; RV32I-NEXT: slli a5, a5, 16 -; RV32I-NEXT: slli a6, a6, 24 +; RV32I-NEXT: slli t2, t2, 24 ; RV32I-NEXT: or a3, a5, a3 -; RV32I-NEXT: or a3, a6, a3 +; RV32I-NEXT: or a3, t2, a3 ; RV32I-NEXT: lbu a4, 17(a0) ; RV32I-NEXT: lbu a5, 16(a0) -; RV32I-NEXT: lbu a6, 18(a0) -; RV32I-NEXT: lbu s8, 19(a0) +; RV32I-NEXT: lbu t2, 18(a0) +; RV32I-NEXT: lbu s4, 19(a0) ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: or a4, a4, a5 -; RV32I-NEXT: slli a6, a6, 16 -; RV32I-NEXT: slli s8, s8, 24 -; RV32I-NEXT: or a4, a6, a4 -; RV32I-NEXT: or a5, s8, a4 +; RV32I-NEXT: slli t2, t2, 16 +; RV32I-NEXT: slli s4, s4, 24 +; RV32I-NEXT: or a4, t2, a4 +; RV32I-NEXT: or s10, s4, a4 ; RV32I-NEXT: lbu a4, 29(a0) -; RV32I-NEXT: lbu a6, 28(a0) -; RV32I-NEXT: lbu s8, 30(a0) -; RV32I-NEXT: lbu s9, 31(a0) -; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a4, a4, a6 -; RV32I-NEXT: slli s8, s8, 16 -; RV32I-NEXT: slli s9, s9, 24 -; RV32I-NEXT: or a4, s8, a4 -; RV32I-NEXT: or s10, s9, a4 -; RV32I-NEXT: lbu a4, 25(a0) -; RV32I-NEXT: lbu a6, 24(a0) -; RV32I-NEXT: lbu s8, 26(a0) -; RV32I-NEXT: lbu a0, 27(a0) +; RV32I-NEXT: lbu a5, 28(a0) +; RV32I-NEXT: lbu t2, 30(a0) +; RV32I-NEXT: lbu s4, 31(a0) ; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a4, a4, a6 -; RV32I-NEXT: slli s8, s8, 16 +; RV32I-NEXT: or a4, a4, a5 +; RV32I-NEXT: slli t2, t2, 16 +; RV32I-NEXT: slli s4, s4, 24 +; RV32I-NEXT: or a4, t2, a4 +; RV32I-NEXT: or s11, s4, a4 +; RV32I-NEXT: lbu a4, 25(a0) +; RV32I-NEXT: lbu a5, 24(a0) +; RV32I-NEXT: lbu t2, 26(a0) +; RV32I-NEXT: lbu a0, 27(a0) +; RV32I-NEXT: slli a4, a4, 8 +; RV32I-NEXT: or a4, a4, a5 +; RV32I-NEXT: slli t2, t2, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a4, s8, a4 -; RV32I-NEXT: or s9, a0, a4 +; RV32I-NEXT: or a4, t2, a4 +; RV32I-NEXT: or s6, a0, a4 ; RV32I-NEXT: lbu a0, 1(a1) ; RV32I-NEXT: lbu a4, 0(a1) -; RV32I-NEXT: lbu a6, 2(a1) +; RV32I-NEXT: lbu a5, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a0, a0, 8 ; RV32I-NEXT: or a0, a0, a4 -; RV32I-NEXT: slli a6, a6, 16 +; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a0, a6, a0 -; RV32I-NEXT: or a6, a1, a0 -; RV32I-NEXT: srl a1, s9, a6 -; RV32I-NEXT: slli a4, s10, 1 -; RV32I-NEXT: addi s8, a6, -224 -; RV32I-NEXT: sw s10, 84(sp) # 4-byte Folded Spill -; RV32I-NEXT: srl a0, s10, a6 -; RV32I-NEXT: sw s8, 28(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a0, 88(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a1, 68(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a4, 64(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgez s8, .LBB9_2 +; RV32I-NEXT: or a0, a5, a0 +; RV32I-NEXT: or a5, a1, a0 +; RV32I-NEXT: srl a0, s6, a5 +; RV32I-NEXT: not s4, a5 +; RV32I-NEXT: slli a1, s11, 1 +; RV32I-NEXT: sll a1, a1, s4 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: addi a4, a5, -224 +; RV32I-NEXT: sw s11, 44(sp) # 4-byte Folded Spill +; RV32I-NEXT: srl a1, s11, a5 +; RV32I-NEXT: sw a0, 52(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a4, 20(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz a4, .LBB9_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: addi a0, a6, -192 -; RV32I-NEXT: xori a0, a0, 31 -; RV32I-NEXT: sll a0, a4, a0 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: .LBB9_2: -; RV32I-NEXT: slli a4, t6, 8 +; RV32I-NEXT: sw a1, 56(sp) # 4-byte Folded Spill +; RV32I-NEXT: slli t2, t5, 8 ; RV32I-NEXT: slli s3, s3, 16 -; RV32I-NEXT: slli s4, s4, 24 -; RV32I-NEXT: slli s5, s5, 8 -; RV32I-NEXT: slli s6, s6, 16 -; RV32I-NEXT: slli s8, s7, 24 -; RV32I-NEXT: srl s10, a5, a6 -; RV32I-NEXT: slli a1, a3, 1 -; RV32I-NEXT: addi s11, a6, -128 -; RV32I-NEXT: xori t6, s11, 31 -; RV32I-NEXT: addi ra, a6, -160 -; RV32I-NEXT: srl s7, a3, a6 -; RV32I-NEXT: sw ra, 72(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s7, 60(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a1, 44(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz ra, .LBB9_4 +; RV32I-NEXT: slli s11, s5, 24 +; RV32I-NEXT: slli ra, s7, 8 +; RV32I-NEXT: slli s8, s8, 16 +; RV32I-NEXT: slli s9, s9, 24 +; RV32I-NEXT: srl a1, s10, a5 +; RV32I-NEXT: slli t5, a3, 1 +; RV32I-NEXT: sll a4, t5, s4 +; RV32I-NEXT: or s5, a1, a4 +; RV32I-NEXT: addi s7, a5, -160 +; RV32I-NEXT: srl a1, a3, a5 +; RV32I-NEXT: sw a1, 48(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s5, 32(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz s7, .LBB9_4 ; RV32I-NEXT: # %bb.3: -; RV32I-NEXT: mv ra, t6 -; RV32I-NEXT: j .LBB9_5 +; RV32I-NEXT: lw s5, 48(sp) # 4-byte Folded Reload ; RV32I-NEXT: .LBB9_4: -; RV32I-NEXT: mv ra, t6 -; RV32I-NEXT: sll a1, a1, t6 -; RV32I-NEXT: or s7, s10, a1 -; RV32I-NEXT: .LBB9_5: -; RV32I-NEXT: slli t4, t4, 8 -; RV32I-NEXT: slli a1, t5, 16 +; RV32I-NEXT: slli a4, t4, 8 +; RV32I-NEXT: slli t6, t6, 16 ; RV32I-NEXT: slli s0, s0, 24 -; RV32I-NEXT: or a4, a4, s1 -; RV32I-NEXT: or s1, s4, s3 -; RV32I-NEXT: or s2, s5, s2 -; RV32I-NEXT: or s3, s8, s6 -; RV32I-NEXT: neg s4, a6 -; RV32I-NEXT: sll s6, s9, s4 -; RV32I-NEXT: li s5, 160 -; RV32I-NEXT: li t5, 64 -; RV32I-NEXT: sub t6, s5, a6 -; RV32I-NEXT: sw s6, 80(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgeu s11, t5, .LBB9_7 -; RV32I-NEXT: # %bb.6: -; RV32I-NEXT: slti a0, t6, 0 +; RV32I-NEXT: or t2, t2, s1 +; RV32I-NEXT: or s1, s11, s3 +; RV32I-NEXT: or s2, ra, s2 +; RV32I-NEXT: or s3, s9, s8 +; RV32I-NEXT: neg s11, a5 +; RV32I-NEXT: sll t4, s6, s11 +; RV32I-NEXT: li a1, 160 +; RV32I-NEXT: addi s8, a5, -128 +; RV32I-NEXT: li s9, 64 +; RV32I-NEXT: sub a1, a1, a5 +; RV32I-NEXT: bltu s8, s9, .LBB9_6 +; RV32I-NEXT: # %bb.5: +; RV32I-NEXT: mv ra, t4 +; RV32I-NEXT: j .LBB9_7 +; RV32I-NEXT: .LBB9_6: +; RV32I-NEXT: slti a0, a1, 0 ; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: and a0, a0, s6 -; RV32I-NEXT: or a0, s7, a0 +; RV32I-NEXT: mv ra, t4 +; RV32I-NEXT: and a0, a0, t4 +; RV32I-NEXT: or a0, s5, a0 ; RV32I-NEXT: .LBB9_7: -; RV32I-NEXT: sw s10, 36(sp) # 4-byte Folded Spill -; RV32I-NEXT: slli t1, t1, 8 -; RV32I-NEXT: slli t2, t2, 16 +; RV32I-NEXT: sw a1, 28(sp) # 4-byte Folded Spill +; RV32I-NEXT: slli t0, t0, 8 +; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli s5, t3, 24 -; RV32I-NEXT: or t3, t4, a7 -; RV32I-NEXT: or a1, s0, a1 -; RV32I-NEXT: or a7, s1, a4 -; RV32I-NEXT: or s1, s3, s2 -; RV32I-NEXT: mv s8, a5 -; RV32I-NEXT: beqz s11, .LBB9_9 +; RV32I-NEXT: or t3, a4, a6 +; RV32I-NEXT: or t6, s0, t6 +; RV32I-NEXT: or a6, s1, t2 +; RV32I-NEXT: or s3, s3, s2 +; RV32I-NEXT: mv s9, s10 +; RV32I-NEXT: beqz s8, .LBB9_9 ; RV32I-NEXT: # %bb.8: -; RV32I-NEXT: mv s8, a0 +; RV32I-NEXT: mv s9, a0 ; RV32I-NEXT: .LBB9_9: -; RV32I-NEXT: or a0, t1, t0 -; RV32I-NEXT: or t0, s5, t2 -; RV32I-NEXT: or a1, a1, t3 -; RV32I-NEXT: srl s6, s1, a6 -; RV32I-NEXT: slli s10, a7, 1 -; RV32I-NEXT: addi a4, a6, -64 -; RV32I-NEXT: xori a4, a4, 31 -; RV32I-NEXT: addi t1, a6, -96 -; RV32I-NEXT: srl t2, a7, a6 -; RV32I-NEXT: sw t1, 76(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a4, 32(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw t2, 48(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz t1, .LBB9_11 +; RV32I-NEXT: or a4, t0, a7 +; RV32I-NEXT: or t0, s5, t1 +; RV32I-NEXT: or a0, t6, t3 +; RV32I-NEXT: srl a1, s3, a5 +; RV32I-NEXT: slli a7, a6, 1 +; RV32I-NEXT: sll a7, a7, s4 +; RV32I-NEXT: or s2, a1, a7 +; RV32I-NEXT: addi t2, a5, -96 +; RV32I-NEXT: srl a1, a6, a5 +; RV32I-NEXT: sw a1, 40(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv a7, s2 +; RV32I-NEXT: bltz t2, .LBB9_11 ; RV32I-NEXT: # %bb.10: -; RV32I-NEXT: mv a4, t2 -; RV32I-NEXT: j .LBB9_12 +; RV32I-NEXT: lw a7, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: .LBB9_11: -; RV32I-NEXT: sll a4, s10, a4 -; RV32I-NEXT: or a4, s6, a4 -; RV32I-NEXT: .LBB9_12: -; RV32I-NEXT: or t2, t0, a0 -; RV32I-NEXT: xori t1, a6, 31 -; RV32I-NEXT: addi s2, a6, -32 -; RV32I-NEXT: srl s0, a1, a6 -; RV32I-NEXT: sw t1, 56(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz s2, .LBB9_14 -; RV32I-NEXT: # %bb.13: -; RV32I-NEXT: mv t0, s0 -; RV32I-NEXT: j .LBB9_15 -; RV32I-NEXT: .LBB9_14: -; RV32I-NEXT: srl a0, t2, a6 -; RV32I-NEXT: slli t0, a1, 1 -; RV32I-NEXT: sll t0, t0, t1 -; RV32I-NEXT: or t0, a0, t0 +; RV32I-NEXT: or t0, t0, a4 +; RV32I-NEXT: addi t6, a5, -32 +; RV32I-NEXT: srl t1, a0, a5 +; RV32I-NEXT: sw t1, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgez t6, .LBB9_13 +; RV32I-NEXT: # %bb.12: +; RV32I-NEXT: srl a1, t0, a5 +; RV32I-NEXT: slli a4, a0, 1 +; RV32I-NEXT: sll a4, a4, s4 +; RV32I-NEXT: or t1, a1, a4 +; RV32I-NEXT: .LBB9_13: +; RV32I-NEXT: sll t3, s3, s11 +; RV32I-NEXT: li a4, 32 +; RV32I-NEXT: sub s0, a4, a5 +; RV32I-NEXT: slti a1, s0, 0 +; RV32I-NEXT: neg s1, a1 +; RV32I-NEXT: li a1, 64 +; RV32I-NEXT: bgeu a5, a1, .LBB9_15 +; RV32I-NEXT: # %bb.14: +; RV32I-NEXT: and a1, s1, t3 +; RV32I-NEXT: or a7, t1, a1 ; RV32I-NEXT: .LBB9_15: -; RV32I-NEXT: sll t4, s1, s4 -; RV32I-NEXT: li a0, 32 -; RV32I-NEXT: sub s3, a0, a6 -; RV32I-NEXT: slti t1, s3, 0 -; RV32I-NEXT: neg t1, t1 -; RV32I-NEXT: bgeu a6, t5, .LBB9_17 +; RV32I-NEXT: mv t4, s7 +; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv s4, t0 +; RV32I-NEXT: beqz a5, .LBB9_17 ; RV32I-NEXT: # %bb.16: -; RV32I-NEXT: and a4, t1, t4 -; RV32I-NEXT: or a4, t0, a4 +; RV32I-NEXT: mv s4, a7 ; RV32I-NEXT: .LBB9_17: -; RV32I-NEXT: sw t6, 40(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw t1, 52(sp) # 4-byte Folded Spill -; RV32I-NEXT: mv t0, t2 -; RV32I-NEXT: beqz a6, .LBB9_19 +; RV32I-NEXT: sll s1, s10, s11 +; RV32I-NEXT: li a1, 96 +; RV32I-NEXT: sub s5, a1, a5 +; RV32I-NEXT: slti a1, s5, 0 +; RV32I-NEXT: neg a7, a1 +; RV32I-NEXT: li s7, 128 +; RV32I-NEXT: sub t1, s7, a5 +; RV32I-NEXT: sltiu a1, t1, 64 +; RV32I-NEXT: neg a1, a1 +; RV32I-NEXT: sw a1, 4(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgeu a5, s7, .LBB9_19 ; RV32I-NEXT: # %bb.18: -; RV32I-NEXT: mv t0, a4 +; RV32I-NEXT: mv s7, a1 +; RV32I-NEXT: and a1, a7, s1 +; RV32I-NEXT: and a1, s7, a1 +; RV32I-NEXT: or s9, s4, a1 ; RV32I-NEXT: .LBB9_19: -; RV32I-NEXT: sll s5, a5, s4 -; RV32I-NEXT: li a4, 96 -; RV32I-NEXT: sub s7, a4, a6 -; RV32I-NEXT: slti a4, s7, 0 -; RV32I-NEXT: neg a4, a4 -; RV32I-NEXT: li t6, 128 -; RV32I-NEXT: sub t1, t6, a6 -; RV32I-NEXT: sltiu t3, t1, 64 -; RV32I-NEXT: neg t3, t3 -; RV32I-NEXT: sw t3, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgeu a6, t6, .LBB9_21 +; RV32I-NEXT: mv s4, ra +; RV32I-NEXT: mv s7, t4 +; RV32I-NEXT: li ra, 64 +; RV32I-NEXT: beqz a5, .LBB9_21 ; RV32I-NEXT: # %bb.20: -; RV32I-NEXT: mv t6, t3 -; RV32I-NEXT: and t3, a4, s5 -; RV32I-NEXT: and t3, t6, t3 -; RV32I-NEXT: or s8, t0, t3 +; RV32I-NEXT: mv t0, s9 ; RV32I-NEXT: .LBB9_21: -; RV32I-NEXT: beqz a6, .LBB9_23 +; RV32I-NEXT: neg a1, t1 +; RV32I-NEXT: sub a4, a4, t1 +; RV32I-NEXT: srl t4, a3, a1 +; RV32I-NEXT: sw a4, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz a4, .LBB9_24 ; RV32I-NEXT: # %bb.22: -; RV32I-NEXT: mv t2, s8 +; RV32I-NEXT: mv a1, t4 +; RV32I-NEXT: lw t5, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgeu t1, ra, .LBB9_25 ; RV32I-NEXT: .LBB9_23: -; RV32I-NEXT: neg t0, t1 -; RV32I-NEXT: sub t3, a0, t1 -; RV32I-NEXT: srl a0, a3, t0 -; RV32I-NEXT: sw t3, 20(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgez t3, .LBB9_25 -; RV32I-NEXT: # %bb.24: -; RV32I-NEXT: srl a0, a5, t0 -; RV32I-NEXT: sub t0, t5, t1 -; RV32I-NEXT: xori t0, t0, 31 -; RV32I-NEXT: lw t3, 44(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll t0, t3, t0 -; RV32I-NEXT: or a0, a0, t0 +; RV32I-NEXT: and a4, a7, s4 +; RV32I-NEXT: or a7, a4, a1 +; RV32I-NEXT: mv a4, s6 +; RV32I-NEXT: bnez t1, .LBB9_26 +; RV32I-NEXT: j .LBB9_27 +; RV32I-NEXT: .LBB9_24: +; RV32I-NEXT: srl a1, s10, a1 +; RV32I-NEXT: sub a4, ra, t1 +; RV32I-NEXT: not a4, a4 +; RV32I-NEXT: sll a4, t5, a4 +; RV32I-NEXT: or a1, a1, a4 +; RV32I-NEXT: lw t5, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltu t1, ra, .LBB9_23 ; RV32I-NEXT: .LBB9_25: -; RV32I-NEXT: bltu t1, t5, .LBB9_27 -; RV32I-NEXT: # %bb.26: -; RV32I-NEXT: lw a0, 52(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a0, s5 -; RV32I-NEXT: mv a0, s9 -; RV32I-NEXT: bnez t1, .LBB9_28 -; RV32I-NEXT: j .LBB9_29 +; RV32I-NEXT: lw a1, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a7, a1, s1 +; RV32I-NEXT: mv a4, s6 +; RV32I-NEXT: beqz t1, .LBB9_27 +; RV32I-NEXT: .LBB9_26: +; RV32I-NEXT: mv a4, a7 ; RV32I-NEXT: .LBB9_27: -; RV32I-NEXT: lw t0, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a4, t0 -; RV32I-NEXT: or a4, a4, a0 -; RV32I-NEXT: mv a0, s9 -; RV32I-NEXT: beqz t1, .LBB9_29 -; RV32I-NEXT: .LBB9_28: -; RV32I-NEXT: mv a0, a4 +; RV32I-NEXT: bltz t6, .LBB9_29 +; RV32I-NEXT: # %bb.28: +; RV32I-NEXT: lw s2, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: .LBB9_29: -; RV32I-NEXT: bltz s2, .LBB9_31 +; RV32I-NEXT: sltiu a1, a5, 64 +; RV32I-NEXT: mv a7, t5 +; RV32I-NEXT: bltz s7, .LBB9_31 ; RV32I-NEXT: # %bb.30: -; RV32I-NEXT: lw a4, 48(sp) # 4-byte Folded Reload -; RV32I-NEXT: j .LBB9_32 +; RV32I-NEXT: lw a7, 56(sp) # 4-byte Folded Reload ; RV32I-NEXT: .LBB9_31: -; RV32I-NEXT: lw a4, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a4, s10, a4 -; RV32I-NEXT: or a4, s6, a4 -; RV32I-NEXT: .LBB9_32: -; RV32I-NEXT: sltiu t0, a6, 64 -; RV32I-NEXT: lw t3, 72(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz t3, .LBB9_34 -; RV32I-NEXT: # %bb.33: -; RV32I-NEXT: lw t3, 88(sp) # 4-byte Folded Reload +; RV32I-NEXT: neg s9, a1 +; RV32I-NEXT: sltiu a1, s8, 64 +; RV32I-NEXT: neg t5, a1 +; RV32I-NEXT: li a1, 128 +; RV32I-NEXT: bltu a5, a1, .LBB9_33 +; RV32I-NEXT: # %bb.32: +; RV32I-NEXT: and a4, t5, a7 +; RV32I-NEXT: mv s2, s3 +; RV32I-NEXT: bnez a5, .LBB9_34 ; RV32I-NEXT: j .LBB9_35 +; RV32I-NEXT: .LBB9_33: +; RV32I-NEXT: and a1, s9, s2 +; RV32I-NEXT: or a4, a1, a4 +; RV32I-NEXT: mv s2, s3 +; RV32I-NEXT: beqz a5, .LBB9_35 ; RV32I-NEXT: .LBB9_34: -; RV32I-NEXT: lw t3, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll t3, t3, ra -; RV32I-NEXT: lw t6, 68(sp) # 4-byte Folded Reload -; RV32I-NEXT: or t3, t6, t3 +; RV32I-NEXT: mv s2, a4 ; RV32I-NEXT: .LBB9_35: -; RV32I-NEXT: neg t6, t0 -; RV32I-NEXT: sltiu t0, s11, 64 -; RV32I-NEXT: neg s6, t0 -; RV32I-NEXT: li t0, 128 -; RV32I-NEXT: sw s6, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltu a6, t0, .LBB9_37 +; RV32I-NEXT: sub a1, ra, a5 +; RV32I-NEXT: not a7, a1 +; RV32I-NEXT: bgez s0, .LBB9_37 ; RV32I-NEXT: # %bb.36: -; RV32I-NEXT: and a0, s6, t3 -; RV32I-NEXT: mv s6, s1 -; RV32I-NEXT: bnez a6, .LBB9_38 -; RV32I-NEXT: j .LBB9_39 +; RV32I-NEXT: sll a1, a6, s11 +; RV32I-NEXT: srli a4, s3, 1 +; RV32I-NEXT: srl a4, a4, a7 +; RV32I-NEXT: or t3, a1, a4 ; RV32I-NEXT: .LBB9_37: -; RV32I-NEXT: and a4, t6, a4 -; RV32I-NEXT: or a0, a4, a0 -; RV32I-NEXT: mv s6, s1 -; RV32I-NEXT: beqz a6, .LBB9_39 -; RV32I-NEXT: .LBB9_38: -; RV32I-NEXT: mv s6, a0 +; RV32I-NEXT: slti a1, t6, 0 +; RV32I-NEXT: neg s3, a1 +; RV32I-NEXT: slti a1, t2, 0 +; RV32I-NEXT: neg a4, a1 +; RV32I-NEXT: sw a7, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a4, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltu a5, ra, .LBB9_39 +; RV32I-NEXT: # %bb.38: +; RV32I-NEXT: lw a1, 40(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a4, a4, a1 +; RV32I-NEXT: j .LBB9_40 ; RV32I-NEXT: .LBB9_39: -; RV32I-NEXT: sub a0, t5, a6 -; RV32I-NEXT: xori s10, a0, 31 -; RV32I-NEXT: bgez s3, .LBB9_41 -; RV32I-NEXT: # %bb.40: -; RV32I-NEXT: sll a0, a7, s4 -; RV32I-NEXT: srli s1, s1, 1 -; RV32I-NEXT: srl a4, s1, s10 -; RV32I-NEXT: or t4, a0, a4 -; RV32I-NEXT: .LBB9_41: -; RV32I-NEXT: slti a0, s2, 0 -; RV32I-NEXT: neg s1, a0 -; RV32I-NEXT: lw a0, 76(sp) # 4-byte Folded Reload -; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: neg a4, a0 -; RV32I-NEXT: sw a4, 16(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltu a6, t5, .LBB9_43 -; RV32I-NEXT: # %bb.42: -; RV32I-NEXT: lw a0, 48(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a4, a0 -; RV32I-NEXT: mv t0, a1 -; RV32I-NEXT: bnez a6, .LBB9_44 +; RV32I-NEXT: lw a1, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, s3, a1 +; RV32I-NEXT: or a4, a1, t3 +; RV32I-NEXT: .LBB9_40: +; RV32I-NEXT: sw t5, 0(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t4, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv a7, a0 +; RV32I-NEXT: beqz a5, .LBB9_42 +; RV32I-NEXT: # %bb.41: +; RV32I-NEXT: mv a7, a4 +; RV32I-NEXT: .LBB9_42: +; RV32I-NEXT: mv t4, t2 +; RV32I-NEXT: mv ra, s4 +; RV32I-NEXT: sll s4, a3, s11 +; RV32I-NEXT: srli a4, s10, 1 +; RV32I-NEXT: not t5, t1 +; RV32I-NEXT: bltz s5, .LBB9_44 +; RV32I-NEXT: # %bb.43: +; RV32I-NEXT: mv t2, s1 ; RV32I-NEXT: j .LBB9_45 -; RV32I-NEXT: .LBB9_43: -; RV32I-NEXT: and s0, s1, s0 -; RV32I-NEXT: or a0, s0, t4 -; RV32I-NEXT: mv t0, a1 -; RV32I-NEXT: beqz a6, .LBB9_45 ; RV32I-NEXT: .LBB9_44: -; RV32I-NEXT: mv t0, a0 +; RV32I-NEXT: srl a1, a4, t5 +; RV32I-NEXT: or t2, s4, a1 ; RV32I-NEXT: .LBB9_45: -; RV32I-NEXT: sll s8, a3, s4 -; RV32I-NEXT: srli a4, a5, 1 -; RV32I-NEXT: xori a0, t1, 31 -; RV32I-NEXT: bltz s7, .LBB9_47 +; RV32I-NEXT: lw a1, 44(sp) # 4-byte Folded Reload +; RV32I-NEXT: sll t3, a1, s11 +; RV32I-NEXT: srli s6, s6, 1 +; RV32I-NEXT: lw a1, 28(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a1, .LBB9_47 ; RV32I-NEXT: # %bb.46: -; RV32I-NEXT: mv t3, s5 +; RV32I-NEXT: mv s11, ra ; RV32I-NEXT: j .LBB9_48 ; RV32I-NEXT: .LBB9_47: -; RV32I-NEXT: srl t3, a4, a0 -; RV32I-NEXT: or t3, s8, t3 +; RV32I-NEXT: li a1, 192 +; RV32I-NEXT: sub a1, a1, a5 +; RV32I-NEXT: not a1, a1 +; RV32I-NEXT: srl a1, s6, a1 +; RV32I-NEXT: or s11, t3, a1 ; RV32I-NEXT: .LBB9_48: -; RV32I-NEXT: lw t4, 84(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll s0, t4, s4 -; RV32I-NEXT: srli s4, s9, 1 -; RV32I-NEXT: lw t4, 40(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz t4, .LBB9_50 +; RV32I-NEXT: slti a1, s7, 0 +; RV32I-NEXT: neg s7, a1 +; RV32I-NEXT: li a1, 64 +; RV32I-NEXT: bltu s8, a1, .LBB9_50 ; RV32I-NEXT: # %bb.49: -; RV32I-NEXT: lw s9, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: j .LBB9_51 +; RV32I-NEXT: lw a1, 20(sp) # 4-byte Folded Reload +; RV32I-NEXT: slti a1, a1, 0 +; RV32I-NEXT: neg a1, a1 +; RV32I-NEXT: lw s11, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, a1, s11 +; RV32I-NEXT: mv s11, a3 +; RV32I-NEXT: bnez s8, .LBB9_51 +; RV32I-NEXT: j .LBB9_52 ; RV32I-NEXT: .LBB9_50: -; RV32I-NEXT: li t4, 192 -; RV32I-NEXT: sub t4, t4, a6 -; RV32I-NEXT: xori t4, t4, 31 -; RV32I-NEXT: srl t4, s4, t4 -; RV32I-NEXT: or s9, s0, t4 +; RV32I-NEXT: lw a1, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, s7, a1 +; RV32I-NEXT: or a1, a1, s11 +; RV32I-NEXT: mv s11, a3 +; RV32I-NEXT: beqz s8, .LBB9_52 ; RV32I-NEXT: .LBB9_51: -; RV32I-NEXT: lw t4, 72(sp) # 4-byte Folded Reload -; RV32I-NEXT: slti t4, t4, 0 -; RV32I-NEXT: neg t4, t4 -; RV32I-NEXT: bltu s11, t5, .LBB9_53 -; RV32I-NEXT: # %bb.52: -; RV32I-NEXT: lw s9, 28(sp) # 4-byte Folded Reload -; RV32I-NEXT: slti s9, s9, 0 -; RV32I-NEXT: neg s9, s9 -; RV32I-NEXT: lw ra, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: and ra, s9, ra -; RV32I-NEXT: mv s9, a3 -; RV32I-NEXT: bnez s11, .LBB9_54 -; RV32I-NEXT: j .LBB9_55 -; RV32I-NEXT: .LBB9_53: -; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload -; RV32I-NEXT: and ra, t4, ra -; RV32I-NEXT: or ra, ra, s9 -; RV32I-NEXT: mv s9, a3 -; RV32I-NEXT: beqz s11, .LBB9_55 +; RV32I-NEXT: mv s11, a1 +; RV32I-NEXT: .LBB9_52: +; RV32I-NEXT: li a1, 128 +; RV32I-NEXT: bltu a5, a1, .LBB9_57 +; RV32I-NEXT: # %bb.53: +; RV32I-NEXT: bnez a5, .LBB9_58 ; RV32I-NEXT: .LBB9_54: -; RV32I-NEXT: mv s9, ra +; RV32I-NEXT: bltz s0, .LBB9_59 ; RV32I-NEXT: .LBB9_55: -; RV32I-NEXT: li s11, 128 -; RV32I-NEXT: bgeu a6, s11, .LBB9_57 -; RV32I-NEXT: # %bb.56: -; RV32I-NEXT: lw s9, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: and t3, s9, t3 -; RV32I-NEXT: or s9, t0, t3 +; RV32I-NEXT: bltz s5, .LBB9_60 +; RV32I-NEXT: .LBB9_56: +; RV32I-NEXT: mv a4, ra +; RV32I-NEXT: j .LBB9_61 ; RV32I-NEXT: .LBB9_57: -; RV32I-NEXT: lw t3, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s11, 68(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw ra, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: bnez a6, .LBB9_61 -; RV32I-NEXT: # %bb.58: -; RV32I-NEXT: bltz s3, .LBB9_62 +; RV32I-NEXT: lw a1, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, a1, t2 +; RV32I-NEXT: or s11, a7, a1 +; RV32I-NEXT: beqz a5, .LBB9_54 +; RV32I-NEXT: .LBB9_58: +; RV32I-NEXT: mv a0, s11 +; RV32I-NEXT: bgez s0, .LBB9_55 ; RV32I-NEXT: .LBB9_59: -; RV32I-NEXT: lw s8, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz s7, .LBB9_63 +; RV32I-NEXT: lw a1, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: srl a1, a4, a1 +; RV32I-NEXT: or s1, s4, a1 +; RV32I-NEXT: bgez s5, .LBB9_56 ; RV32I-NEXT: .LBB9_60: -; RV32I-NEXT: mv a0, s8 -; RV32I-NEXT: lw t0, 60(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltu t1, t5, .LBB9_64 -; RV32I-NEXT: j .LBB9_65 +; RV32I-NEXT: srl a1, s6, t5 +; RV32I-NEXT: or a4, t3, a1 ; RV32I-NEXT: .LBB9_61: -; RV32I-NEXT: mv a1, s9 -; RV32I-NEXT: bgez s3, .LBB9_59 -; RV32I-NEXT: .LBB9_62: -; RV32I-NEXT: srl a4, a4, s10 -; RV32I-NEXT: or s5, s8, a4 -; RV32I-NEXT: lw s8, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgez s7, .LBB9_60 +; RV32I-NEXT: lw t5, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: li a1, 64 +; RV32I-NEXT: bltu t1, a1, .LBB9_65 +; RV32I-NEXT: # %bb.62: +; RV32I-NEXT: bnez t1, .LBB9_66 ; RV32I-NEXT: .LBB9_63: -; RV32I-NEXT: srl a0, s4, a0 -; RV32I-NEXT: or a0, s0, a0 -; RV32I-NEXT: lw t0, 60(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgeu t1, t5, .LBB9_65 +; RV32I-NEXT: li a1, 128 +; RV32I-NEXT: bltu a5, a1, .LBB9_67 ; RV32I-NEXT: .LBB9_64: -; RV32I-NEXT: lw a4, 20(sp) # 4-byte Folded Reload -; RV32I-NEXT: slti a4, a4, 0 -; RV32I-NEXT: neg a4, a4 -; RV32I-NEXT: lw s5, 24(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a4, s5 -; RV32I-NEXT: or s5, a0, a4 +; RV32I-NEXT: lw t2, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, s7, t2 +; RV32I-NEXT: lw a4, 0(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, a4, a1 +; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: bnez a5, .LBB9_68 +; RV32I-NEXT: j .LBB9_69 ; RV32I-NEXT: .LBB9_65: -; RV32I-NEXT: bnez t1, .LBB9_68 -; RV32I-NEXT: # %bb.66: -; RV32I-NEXT: li a0, 128 -; RV32I-NEXT: bltu a6, a0, .LBB9_69 +; RV32I-NEXT: lw a1, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: slti a1, a1, 0 +; RV32I-NEXT: neg a1, a1 +; RV32I-NEXT: lw t2, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, a1, t2 +; RV32I-NEXT: or s1, a4, a1 +; RV32I-NEXT: beqz t1, .LBB9_63 +; RV32I-NEXT: .LBB9_66: +; RV32I-NEXT: sw s1, 44(sp) # 4-byte Folded Spill +; RV32I-NEXT: li a1, 128 +; RV32I-NEXT: bgeu a5, a1, .LBB9_64 ; RV32I-NEXT: .LBB9_67: -; RV32I-NEXT: and a0, t4, t3 -; RV32I-NEXT: lw a4, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a4, a0 -; RV32I-NEXT: lw t4, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: bnez a6, .LBB9_70 -; RV32I-NEXT: j .LBB9_71 +; RV32I-NEXT: lw a1, 40(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, s3, a1 +; RV32I-NEXT: and a1, s9, a1 +; RV32I-NEXT: lw a4, 44(sp) # 4-byte Folded Reload +; RV32I-NEXT: or a1, a1, a4 +; RV32I-NEXT: lw t2, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: beqz a5, .LBB9_69 ; RV32I-NEXT: .LBB9_68: -; RV32I-NEXT: sw s5, 84(sp) # 4-byte Folded Spill -; RV32I-NEXT: li a0, 128 -; RV32I-NEXT: bgeu a6, a0, .LBB9_67 +; RV32I-NEXT: mv a6, a1 ; RV32I-NEXT: .LBB9_69: -; RV32I-NEXT: lw a0, 48(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, s1, a0 -; RV32I-NEXT: and a0, t6, a0 -; RV32I-NEXT: lw a4, 84(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a0, a0, a4 -; RV32I-NEXT: lw t4, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: beqz a6, .LBB9_71 -; RV32I-NEXT: .LBB9_70: -; RV32I-NEXT: mv a7, a0 +; RV32I-NEXT: mv a4, t5 +; RV32I-NEXT: bgez t4, .LBB9_76 +; RV32I-NEXT: # %bb.70: +; RV32I-NEXT: bgez t6, .LBB9_77 ; RV32I-NEXT: .LBB9_71: -; RV32I-NEXT: lw a0, 76(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz a0, .LBB9_74 -; RV32I-NEXT: # %bb.72: -; RV32I-NEXT: mv a0, t3 -; RV32I-NEXT: bgez s2, .LBB9_75 +; RV32I-NEXT: li t1, 64 +; RV32I-NEXT: bltu a5, t1, .LBB9_78 +; RV32I-NEXT: .LBB9_72: +; RV32I-NEXT: bnez a5, .LBB9_79 ; RV32I-NEXT: .LBB9_73: -; RV32I-NEXT: lw a4, 44(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a4, a4, t4 -; RV32I-NEXT: lw t1, 36(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a4, t1, a4 -; RV32I-NEXT: lw t1, 52(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltu a6, t5, .LBB9_76 -; RV32I-NEXT: j .LBB9_77 +; RV32I-NEXT: bltz s0, .LBB9_80 ; RV32I-NEXT: .LBB9_74: -; RV32I-NEXT: lw a0, 32(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a0, ra, a0 -; RV32I-NEXT: or a0, s11, a0 -; RV32I-NEXT: bltz s2, .LBB9_73 +; RV32I-NEXT: sltiu a4, a5, 128 +; RV32I-NEXT: bltu a5, t1, .LBB9_81 ; RV32I-NEXT: .LBB9_75: -; RV32I-NEXT: mv a4, t0 -; RV32I-NEXT: lw t1, 52(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgeu a6, t5, .LBB9_77 +; RV32I-NEXT: lw a1, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: and t1, a1, t2 +; RV32I-NEXT: neg a7, a4 +; RV32I-NEXT: bnez a5, .LBB9_82 +; RV32I-NEXT: j .LBB9_83 ; RV32I-NEXT: .LBB9_76: -; RV32I-NEXT: and a0, t1, s8 -; RV32I-NEXT: or a0, a4, a0 +; RV32I-NEXT: mv a4, t2 +; RV32I-NEXT: bltz t6, .LBB9_71 ; RV32I-NEXT: .LBB9_77: -; RV32I-NEXT: bnez a6, .LBB9_81 -; RV32I-NEXT: # %bb.78: -; RV32I-NEXT: bltz s3, .LBB9_82 +; RV32I-NEXT: lw a1, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a1, 32(sp) # 4-byte Folded Spill +; RV32I-NEXT: li t1, 64 +; RV32I-NEXT: bgeu a5, t1, .LBB9_72 +; RV32I-NEXT: .LBB9_78: +; RV32I-NEXT: and a1, s1, ra +; RV32I-NEXT: lw a4, 32(sp) # 4-byte Folded Reload +; RV32I-NEXT: or a4, a4, a1 +; RV32I-NEXT: beqz a5, .LBB9_73 ; RV32I-NEXT: .LBB9_79: -; RV32I-NEXT: sltiu a0, a6, 128 -; RV32I-NEXT: bltu a6, t5, .LBB9_83 +; RV32I-NEXT: mv s10, a4 +; RV32I-NEXT: bgez s0, .LBB9_74 ; RV32I-NEXT: .LBB9_80: -; RV32I-NEXT: lw a4, 16(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a4, t3 -; RV32I-NEXT: neg t0, a0 -; RV32I-NEXT: bnez a6, .LBB9_84 -; RV32I-NEXT: j .LBB9_85 +; RV32I-NEXT: lw a1, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: srl a1, s6, a1 +; RV32I-NEXT: or ra, t3, a1 +; RV32I-NEXT: sltiu a4, a5, 128 +; RV32I-NEXT: bgeu a5, t1, .LBB9_75 ; RV32I-NEXT: .LBB9_81: -; RV32I-NEXT: mv a5, a0 -; RV32I-NEXT: bgez s3, .LBB9_79 +; RV32I-NEXT: lw a1, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a1, s3, a1 +; RV32I-NEXT: or t1, a1, ra +; RV32I-NEXT: neg a7, a4 +; RV32I-NEXT: beqz a5, .LBB9_83 ; RV32I-NEXT: .LBB9_82: -; RV32I-NEXT: srl a0, s4, s10 -; RV32I-NEXT: or s8, s0, a0 -; RV32I-NEXT: sltiu a0, a6, 128 -; RV32I-NEXT: bgeu a6, t5, .LBB9_80 +; RV32I-NEXT: mv a3, t1 ; RV32I-NEXT: .LBB9_83: -; RV32I-NEXT: and a4, s1, t0 -; RV32I-NEXT: or a4, a4, s8 -; RV32I-NEXT: neg t0, a0 -; RV32I-NEXT: beqz a6, .LBB9_85 -; RV32I-NEXT: .LBB9_84: -; RV32I-NEXT: mv a3, a4 +; RV32I-NEXT: and a4, a7, s10 +; RV32I-NEXT: and a3, a7, a3 +; RV32I-NEXT: bltz t6, .LBB9_85 +; RV32I-NEXT: # %bb.84: +; RV32I-NEXT: mv t5, t2 ; RV32I-NEXT: .LBB9_85: -; RV32I-NEXT: and a4, t0, a5 -; RV32I-NEXT: and a0, t0, a3 -; RV32I-NEXT: bltz s2, .LBB9_87 -; RV32I-NEXT: # %bb.86: -; RV32I-NEXT: mv a3, t3 -; RV32I-NEXT: j .LBB9_88 -; RV32I-NEXT: .LBB9_87: -; RV32I-NEXT: sll a3, ra, t4 -; RV32I-NEXT: or a3, s11, a3 -; RV32I-NEXT: .LBB9_88: -; RV32I-NEXT: and a3, t6, a3 -; RV32I-NEXT: and a3, t0, a3 -; RV32I-NEXT: and a5, s1, t3 -; RV32I-NEXT: and a5, t6, a5 -; RV32I-NEXT: and a5, t0, a5 -; RV32I-NEXT: sb a3, 24(a2) +; RV32I-NEXT: and a1, s9, t5 +; RV32I-NEXT: and a1, a7, a1 +; RV32I-NEXT: and a5, s3, t2 +; RV32I-NEXT: and a5, s9, a5 +; RV32I-NEXT: and a5, a7, a5 +; RV32I-NEXT: sb a1, 24(a2) ; RV32I-NEXT: sb a5, 28(a2) -; RV32I-NEXT: srli a6, a3, 24 -; RV32I-NEXT: sb a6, 27(a2) -; RV32I-NEXT: srli a6, a3, 16 -; RV32I-NEXT: sb a6, 26(a2) -; RV32I-NEXT: srli a3, a3, 8 -; RV32I-NEXT: sb a3, 25(a2) -; RV32I-NEXT: srli a3, a5, 24 -; RV32I-NEXT: sb a3, 31(a2) -; RV32I-NEXT: srli a3, a5, 16 -; RV32I-NEXT: sb a3, 30(a2) +; RV32I-NEXT: srli a7, a1, 24 +; RV32I-NEXT: sb a7, 27(a2) +; RV32I-NEXT: srli a7, a1, 16 +; RV32I-NEXT: sb a7, 26(a2) +; RV32I-NEXT: srli a1, a1, 8 +; RV32I-NEXT: sb a1, 25(a2) +; RV32I-NEXT: srli a1, a5, 24 +; RV32I-NEXT: sb a1, 31(a2) +; RV32I-NEXT: srli a1, a5, 16 +; RV32I-NEXT: sb a1, 30(a2) ; RV32I-NEXT: srli a5, a5, 8 ; RV32I-NEXT: sb a5, 29(a2) ; RV32I-NEXT: sb a4, 16(a2) -; RV32I-NEXT: srli a3, a4, 24 -; RV32I-NEXT: sb a3, 19(a2) -; RV32I-NEXT: srli a3, a4, 16 -; RV32I-NEXT: sb a3, 18(a2) +; RV32I-NEXT: srli a1, a4, 24 +; RV32I-NEXT: sb a1, 19(a2) +; RV32I-NEXT: srli a1, a4, 16 +; RV32I-NEXT: sb a1, 18(a2) ; RV32I-NEXT: srli a4, a4, 8 ; RV32I-NEXT: sb a4, 17(a2) -; RV32I-NEXT: sb a0, 20(a2) -; RV32I-NEXT: srli a3, a0, 24 -; RV32I-NEXT: sb a3, 23(a2) -; RV32I-NEXT: srli a3, a0, 16 -; RV32I-NEXT: sb a3, 22(a2) +; RV32I-NEXT: sb a3, 20(a2) +; RV32I-NEXT: srli a1, a3, 24 +; RV32I-NEXT: sb a1, 23(a2) +; RV32I-NEXT: srli a1, a3, 16 +; RV32I-NEXT: sb a1, 22(a2) +; RV32I-NEXT: srli a3, a3, 8 +; RV32I-NEXT: sb a3, 21(a2) +; RV32I-NEXT: sb t0, 0(a2) +; RV32I-NEXT: sb a6, 12(a2) +; RV32I-NEXT: srli a1, t0, 24 +; RV32I-NEXT: sb a1, 3(a2) +; RV32I-NEXT: srli a1, t0, 16 +; RV32I-NEXT: sb a1, 2(a2) +; RV32I-NEXT: srli a1, t0, 8 +; RV32I-NEXT: sb a1, 1(a2) +; RV32I-NEXT: sb a0, 4(a2) +; RV32I-NEXT: sb s2, 8(a2) +; RV32I-NEXT: srli a1, a6, 24 +; RV32I-NEXT: sb a1, 15(a2) +; RV32I-NEXT: srli a1, a6, 16 +; RV32I-NEXT: sb a1, 14(a2) +; RV32I-NEXT: srli a1, a6, 8 +; RV32I-NEXT: sb a1, 13(a2) +; RV32I-NEXT: srli a1, a0, 24 +; RV32I-NEXT: sb a1, 7(a2) +; RV32I-NEXT: srli a1, a0, 16 +; RV32I-NEXT: sb a1, 6(a2) ; RV32I-NEXT: srli a0, a0, 8 -; RV32I-NEXT: sb a0, 21(a2) -; RV32I-NEXT: sb t2, 0(a2) -; RV32I-NEXT: sb a7, 12(a2) -; RV32I-NEXT: srli a0, t2, 24 -; RV32I-NEXT: sb a0, 3(a2) -; RV32I-NEXT: srli a0, t2, 16 -; RV32I-NEXT: sb a0, 2(a2) -; RV32I-NEXT: srli a0, t2, 8 -; RV32I-NEXT: sb a0, 1(a2) -; RV32I-NEXT: sb a1, 4(a2) -; RV32I-NEXT: sb s6, 8(a2) -; RV32I-NEXT: srli a0, a7, 24 -; RV32I-NEXT: sb a0, 15(a2) -; RV32I-NEXT: srli a0, a7, 16 -; RV32I-NEXT: sb a0, 14(a2) -; RV32I-NEXT: srli a0, a7, 8 -; RV32I-NEXT: sb a0, 13(a2) -; RV32I-NEXT: srli a0, a1, 24 -; RV32I-NEXT: sb a0, 7(a2) -; RV32I-NEXT: srli a0, a1, 16 -; RV32I-NEXT: sb a0, 6(a2) -; RV32I-NEXT: srli a1, a1, 8 -; RV32I-NEXT: sb a1, 5(a2) -; RV32I-NEXT: srli a0, s6, 24 +; RV32I-NEXT: sb a0, 5(a2) +; RV32I-NEXT: srli a0, s2, 24 ; RV32I-NEXT: sb a0, 11(a2) -; RV32I-NEXT: srli a0, s6, 16 +; RV32I-NEXT: srli a0, s2, 16 ; RV32I-NEXT: sb a0, 10(a2) -; RV32I-NEXT: srli a0, s6, 8 +; RV32I-NEXT: srli a0, s2, 8 ; RV32I-NEXT: sb a0, 9(a2) -; RV32I-NEXT: lw ra, 140(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 136(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 132(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 128(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s3, 124(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s4, 120(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s5, 116(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s6, 112(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s7, 108(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s8, 104(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s9, 100(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s10, 96(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s11, 92(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 144 +; RV32I-NEXT: lw ra, 108(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 104(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 100(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 96(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s3, 92(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s4, 88(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s5, 84(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s6, 80(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s7, 76(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s8, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s9, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s10, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s11, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 112 ; RV32I-NEXT: ret %src = load i256, ptr %src.ptr, align 1 %bitOff = load i256, ptr %bitOff.ptr, align 1 @@ -2359,11 +2295,9 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-LABEL: shl_32bytes: ; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -32 -; RV64I-NEXT: sd s0, 24(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s1, 16(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s2, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s3, 0(sp) # 8-byte Folded Spill +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd s0, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s1, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: lbu a3, 17(a0) ; RV64I-NEXT: lbu a4, 16(a0) ; RV64I-NEXT: lbu a5, 18(a0) @@ -2395,171 +2329,164 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a6, a6, 16 ; RV64I-NEXT: slli a7, a7, 24 ; RV64I-NEXT: or a4, a6, a4 -; RV64I-NEXT: or a6, a7, a4 +; RV64I-NEXT: or a5, a7, a4 ; RV64I-NEXT: lbu a4, 29(a0) -; RV64I-NEXT: lbu a5, 28(a0) +; RV64I-NEXT: lbu a6, 28(a0) ; RV64I-NEXT: lbu a7, 30(a0) ; RV64I-NEXT: lbu t0, 31(a0) ; RV64I-NEXT: slli a4, a4, 8 -; RV64I-NEXT: or a4, a4, a5 +; RV64I-NEXT: or a4, a4, a6 ; RV64I-NEXT: slli a7, a7, 16 ; RV64I-NEXT: slli t0, t0, 24 ; RV64I-NEXT: or a4, a7, a4 -; RV64I-NEXT: or a4, t0, a4 -; RV64I-NEXT: lbu a5, 1(a0) -; RV64I-NEXT: lbu a7, 0(a0) -; RV64I-NEXT: lbu t0, 2(a0) +; RV64I-NEXT: or t0, t0, a4 +; RV64I-NEXT: slli t0, t0, 32 +; RV64I-NEXT: lbu a4, 1(a0) +; RV64I-NEXT: lbu a6, 0(a0) +; RV64I-NEXT: lbu a7, 2(a0) ; RV64I-NEXT: lbu t1, 3(a0) -; RV64I-NEXT: slli a5, a5, 8 -; RV64I-NEXT: or a5, a5, a7 -; RV64I-NEXT: slli t0, t0, 16 +; RV64I-NEXT: slli a4, a4, 8 +; RV64I-NEXT: or a4, a4, a6 +; RV64I-NEXT: slli a7, a7, 16 ; RV64I-NEXT: slli t1, t1, 24 -; RV64I-NEXT: or a5, t0, a5 -; RV64I-NEXT: lbu a7, 5(a0) -; RV64I-NEXT: lbu t0, 4(a0) +; RV64I-NEXT: or a4, a7, a4 +; RV64I-NEXT: lbu a6, 5(a0) +; RV64I-NEXT: lbu a7, 4(a0) ; RV64I-NEXT: lbu t2, 6(a0) ; RV64I-NEXT: lbu t3, 7(a0) -; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a7, a7, t0 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: or a6, a6, a7 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or a7, t2, a7 -; RV64I-NEXT: or a7, t3, a7 -; RV64I-NEXT: slli a7, a7, 32 -; RV64I-NEXT: or a5, a7, a5 -; RV64I-NEXT: lbu a7, 9(a0) -; RV64I-NEXT: lbu t0, 8(a0) -; RV64I-NEXT: lbu t2, 10(a0) -; RV64I-NEXT: or a5, a5, t1 -; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a7, a7, t0 -; RV64I-NEXT: slli t2, t2, 16 -; RV64I-NEXT: lbu t0, 13(a0) -; RV64I-NEXT: lbu t1, 11(a0) -; RV64I-NEXT: or a7, t2, a7 -; RV64I-NEXT: lbu t2, 12(a0) -; RV64I-NEXT: slli t0, t0, 8 +; RV64I-NEXT: or a6, t2, a6 +; RV64I-NEXT: or a6, t3, a6 +; RV64I-NEXT: slli a6, a6, 32 +; RV64I-NEXT: or a4, a6, a4 +; RV64I-NEXT: or a4, a4, t1 +; RV64I-NEXT: lbu a6, 9(a0) +; RV64I-NEXT: lbu a7, 8(a0) +; RV64I-NEXT: lbu t1, 10(a0) +; RV64I-NEXT: lbu t2, 11(a0) +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: or a6, a6, a7 +; RV64I-NEXT: slli t1, t1, 16 +; RV64I-NEXT: slli t2, t2, 24 +; RV64I-NEXT: or a6, t1, a6 +; RV64I-NEXT: lbu a7, 13(a0) +; RV64I-NEXT: lbu t1, 12(a0) ; RV64I-NEXT: lbu t3, 14(a0) ; RV64I-NEXT: lbu a0, 15(a0) -; RV64I-NEXT: or t0, t0, t2 -; RV64I-NEXT: slli t1, t1, 24 +; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: or a7, a7, t1 ; RV64I-NEXT: slli t3, t3, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or t0, t3, t0 -; RV64I-NEXT: or a0, a0, t0 -; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: or a7, t3, a7 ; RV64I-NEXT: or a0, a0, a7 -; RV64I-NEXT: lbu a7, 1(a1) -; RV64I-NEXT: lbu t0, 0(a1) -; RV64I-NEXT: lbu t2, 2(a1) -; RV64I-NEXT: or t1, a0, t1 -; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a0, a7, t0 -; RV64I-NEXT: slli t2, t2, 16 -; RV64I-NEXT: lbu a7, 5(a1) -; RV64I-NEXT: lbu t0, 4(a1) -; RV64I-NEXT: or t2, t2, a0 -; RV64I-NEXT: lbu t3, 3(a1) -; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a7, a7, t0 -; RV64I-NEXT: lbu t0, 6(a1) +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: or t1, a0, t2 +; RV64I-NEXT: lbu a0, 1(a1) +; RV64I-NEXT: lbu a6, 0(a1) +; RV64I-NEXT: lbu a7, 2(a1) +; RV64I-NEXT: lbu t2, 3(a1) +; RV64I-NEXT: slli a0, a0, 8 +; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: slli a7, a7, 16 +; RV64I-NEXT: slli t2, t2, 24 +; RV64I-NEXT: or a0, a7, a0 +; RV64I-NEXT: lbu a6, 5(a1) +; RV64I-NEXT: lbu a7, 4(a1) +; RV64I-NEXT: lbu t3, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli a0, a4, 32 -; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: slli t0, t0, 16 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: or a6, a6, a7 +; RV64I-NEXT: slli t3, t3, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a4, t0, a7 -; RV64I-NEXT: or a1, a1, a4 +; RV64I-NEXT: or a6, t3, a6 +; RV64I-NEXT: or a1, a1, a6 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a1, a1, t2 -; RV64I-NEXT: or a1, a1, t3 -; RV64I-NEXT: sll a7, t1, a1 -; RV64I-NEXT: srli t0, a5, 1 -; RV64I-NEXT: addi t3, a1, -192 -; RV64I-NEXT: sll a4, a5, a1 -; RV64I-NEXT: bltz t3, .LBB10_2 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: or a1, a0, t2 +; RV64I-NEXT: sll a0, t1, a1 +; RV64I-NEXT: not t4, a1 +; RV64I-NEXT: srli a6, a4, 1 +; RV64I-NEXT: srl a6, a6, t4 +; RV64I-NEXT: or a6, a0, a6 +; RV64I-NEXT: addi t2, a1, -192 +; RV64I-NEXT: sll a7, a4, a1 +; RV64I-NEXT: mv t3, a6 +; RV64I-NEXT: bltz t2, .LBB10_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv t5, a4 -; RV64I-NEXT: j .LBB10_3 +; RV64I-NEXT: mv t3, a7 ; RV64I-NEXT: .LBB10_2: -; RV64I-NEXT: addiw t2, a1, -128 -; RV64I-NEXT: xori t2, t2, 63 -; RV64I-NEXT: srl t2, t0, t2 -; RV64I-NEXT: or t5, a7, t2 -; RV64I-NEXT: .LBB10_3: -; RV64I-NEXT: or a0, a0, a6 -; RV64I-NEXT: xori a6, a1, 63 -; RV64I-NEXT: addi t2, a1, -64 -; RV64I-NEXT: sll t4, a3, a1 -; RV64I-NEXT: bltz t2, .LBB10_5 -; RV64I-NEXT: # %bb.4: -; RV64I-NEXT: mv s3, t4 -; RV64I-NEXT: j .LBB10_6 +; RV64I-NEXT: or a0, t0, a5 +; RV64I-NEXT: addi a5, a1, -64 +; RV64I-NEXT: sll t0, a3, a1 +; RV64I-NEXT: bltz a5, .LBB10_4 +; RV64I-NEXT: # %bb.3: +; RV64I-NEXT: mv s1, t0 +; RV64I-NEXT: j .LBB10_5 +; RV64I-NEXT: .LBB10_4: +; RV64I-NEXT: sll t5, a0, a1 +; RV64I-NEXT: srli t6, a3, 1 +; RV64I-NEXT: srl t4, t6, t4 +; RV64I-NEXT: or s1, t5, t4 ; RV64I-NEXT: .LBB10_5: -; RV64I-NEXT: sll t6, a0, a1 -; RV64I-NEXT: srli s0, a3, 1 -; RV64I-NEXT: srl s0, s0, a6 -; RV64I-NEXT: or s3, t6, s0 -; RV64I-NEXT: .LBB10_6: -; RV64I-NEXT: negw s1, a1 -; RV64I-NEXT: srl t6, t1, s1 -; RV64I-NEXT: li s2, 64 -; RV64I-NEXT: li s0, 128 -; RV64I-NEXT: sub s2, s2, a1 -; RV64I-NEXT: bltu a1, s0, .LBB10_12 -; RV64I-NEXT: # %bb.7: -; RV64I-NEXT: bnez a1, .LBB10_13 +; RV64I-NEXT: negw t6, a1 +; RV64I-NEXT: srl t4, t1, t6 +; RV64I-NEXT: li s0, 64 +; RV64I-NEXT: li t5, 128 +; RV64I-NEXT: sub s0, s0, a1 +; RV64I-NEXT: bltu a1, t5, .LBB10_11 +; RV64I-NEXT: # %bb.6: +; RV64I-NEXT: bnez a1, .LBB10_12 +; RV64I-NEXT: .LBB10_7: +; RV64I-NEXT: bgez s0, .LBB10_9 ; RV64I-NEXT: .LBB10_8: -; RV64I-NEXT: bgez s2, .LBB10_10 -; RV64I-NEXT: .LBB10_9: -; RV64I-NEXT: srl a5, a5, s1 +; RV64I-NEXT: srl a4, a4, t6 ; RV64I-NEXT: slli t1, t1, 1 -; RV64I-NEXT: subw t5, s0, a1 -; RV64I-NEXT: xori t5, t5, 63 -; RV64I-NEXT: sll t1, t1, t5 -; RV64I-NEXT: or t6, a5, t1 -; RV64I-NEXT: .LBB10_10: -; RV64I-NEXT: slti a5, t2, 0 -; RV64I-NEXT: neg a5, a5 -; RV64I-NEXT: bltu a1, s0, .LBB10_14 -; RV64I-NEXT: # %bb.11: -; RV64I-NEXT: slti t1, t3, 0 -; RV64I-NEXT: neg t1, t1 -; RV64I-NEXT: and t1, t1, a4 -; RV64I-NEXT: bnez a1, .LBB10_15 -; RV64I-NEXT: j .LBB10_16 +; RV64I-NEXT: subw t3, t5, a1 +; RV64I-NEXT: not t3, t3 +; RV64I-NEXT: sll t1, t1, t3 +; RV64I-NEXT: or t4, a4, t1 +; RV64I-NEXT: .LBB10_9: +; RV64I-NEXT: slti a4, a5, 0 +; RV64I-NEXT: neg a4, a4 +; RV64I-NEXT: bltu a1, t5, .LBB10_13 +; RV64I-NEXT: # %bb.10: +; RV64I-NEXT: slti t0, t2, 0 +; RV64I-NEXT: neg t0, t0 +; RV64I-NEXT: and t0, t0, a7 +; RV64I-NEXT: bnez a1, .LBB10_14 +; RV64I-NEXT: j .LBB10_15 +; RV64I-NEXT: .LBB10_11: +; RV64I-NEXT: slti t3, s0, 0 +; RV64I-NEXT: neg t3, t3 +; RV64I-NEXT: and t3, t3, t4 +; RV64I-NEXT: or t3, s1, t3 +; RV64I-NEXT: beqz a1, .LBB10_7 ; RV64I-NEXT: .LBB10_12: -; RV64I-NEXT: slti t5, s2, 0 -; RV64I-NEXT: neg t5, t5 -; RV64I-NEXT: and t5, t5, t6 -; RV64I-NEXT: or t5, s3, t5 -; RV64I-NEXT: beqz a1, .LBB10_8 +; RV64I-NEXT: mv a0, t3 +; RV64I-NEXT: bltz s0, .LBB10_8 +; RV64I-NEXT: j .LBB10_9 ; RV64I-NEXT: .LBB10_13: -; RV64I-NEXT: mv a0, t5 -; RV64I-NEXT: bltz s2, .LBB10_9 -; RV64I-NEXT: j .LBB10_10 +; RV64I-NEXT: and t0, a4, t0 +; RV64I-NEXT: or t0, t0, t4 +; RV64I-NEXT: beqz a1, .LBB10_15 ; RV64I-NEXT: .LBB10_14: -; RV64I-NEXT: and t1, a5, t4 -; RV64I-NEXT: or t1, t1, t6 -; RV64I-NEXT: beqz a1, .LBB10_16 +; RV64I-NEXT: mv a3, t0 ; RV64I-NEXT: .LBB10_15: -; RV64I-NEXT: mv a3, t1 -; RV64I-NEXT: .LBB10_16: -; RV64I-NEXT: bltz t2, .LBB10_18 -; RV64I-NEXT: # %bb.17: -; RV64I-NEXT: mv a6, a4 -; RV64I-NEXT: j .LBB10_19 -; RV64I-NEXT: .LBB10_18: -; RV64I-NEXT: srl a6, t0, a6 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: .LBB10_19: +; RV64I-NEXT: bltz a5, .LBB10_17 +; RV64I-NEXT: # %bb.16: +; RV64I-NEXT: mv a6, a7 +; RV64I-NEXT: .LBB10_17: ; RV64I-NEXT: sltiu a1, a1, 128 ; RV64I-NEXT: neg a1, a1 -; RV64I-NEXT: and a6, a1, a6 -; RV64I-NEXT: and a4, a5, a4 +; RV64I-NEXT: and a5, a1, a6 +; RV64I-NEXT: and a4, a4, a7 ; RV64I-NEXT: and a1, a1, a4 ; RV64I-NEXT: sb a1, 0(a2) -; RV64I-NEXT: sb a6, 8(a2) +; RV64I-NEXT: sb a5, 8(a2) ; RV64I-NEXT: srli a4, a1, 56 ; RV64I-NEXT: sb a4, 7(a2) ; RV64I-NEXT: srli a4, a1, 48 @@ -2574,20 +2501,20 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: sb a4, 2(a2) ; RV64I-NEXT: srli a1, a1, 8 ; RV64I-NEXT: sb a1, 1(a2) -; RV64I-NEXT: srli a1, a6, 56 +; RV64I-NEXT: srli a1, a5, 56 ; RV64I-NEXT: sb a1, 15(a2) -; RV64I-NEXT: srli a1, a6, 48 +; RV64I-NEXT: srli a1, a5, 48 ; RV64I-NEXT: sb a1, 14(a2) -; RV64I-NEXT: srli a1, a6, 40 +; RV64I-NEXT: srli a1, a5, 40 ; RV64I-NEXT: sb a1, 13(a2) -; RV64I-NEXT: srli a1, a6, 32 +; RV64I-NEXT: srli a1, a5, 32 ; RV64I-NEXT: sb a1, 12(a2) -; RV64I-NEXT: srli a1, a6, 24 +; RV64I-NEXT: srli a1, a5, 24 ; RV64I-NEXT: sb a1, 11(a2) -; RV64I-NEXT: srli a1, a6, 16 +; RV64I-NEXT: srli a1, a5, 16 ; RV64I-NEXT: sb a1, 10(a2) -; RV64I-NEXT: srli a1, a6, 8 -; RV64I-NEXT: sb a1, 9(a2) +; RV64I-NEXT: srli a5, a5, 8 +; RV64I-NEXT: sb a5, 9(a2) ; RV64I-NEXT: sb a0, 24(a2) ; RV64I-NEXT: sb a3, 16(a2) ; RV64I-NEXT: srli a1, a0, 56 @@ -2618,527 +2545,494 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: sb a0, 18(a2) ; RV64I-NEXT: srli a3, a3, 8 ; RV64I-NEXT: sb a3, 17(a2) -; RV64I-NEXT: ld s0, 24(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s1, 16(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s2, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s3, 0(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 32 +; RV64I-NEXT: ld s0, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s1, 0(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; ; RV32I-LABEL: shl_32bytes: ; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -144 -; RV32I-NEXT: sw ra, 140(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 136(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 132(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 128(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 124(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s4, 120(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s5, 116(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s6, 112(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s7, 108(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s8, 104(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s9, 100(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s10, 96(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s11, 92(sp) # 4-byte Folded Spill -; RV32I-NEXT: lbu a5, 24(a0) -; RV32I-NEXT: lbu t3, 25(a0) -; RV32I-NEXT: lbu t6, 26(a0) -; RV32I-NEXT: lbu s0, 27(a0) -; RV32I-NEXT: lbu a7, 28(a0) -; RV32I-NEXT: lbu t0, 29(a0) -; RV32I-NEXT: lbu t1, 30(a0) -; RV32I-NEXT: lbu t5, 31(a0) -; RV32I-NEXT: lbu a4, 16(a0) -; RV32I-NEXT: lbu t2, 17(a0) -; RV32I-NEXT: lbu t4, 18(a0) +; RV32I-NEXT: addi sp, sp, -128 +; RV32I-NEXT: sw ra, 124(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 120(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 116(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 112(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s3, 108(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s4, 104(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s5, 100(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s6, 96(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s7, 92(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s8, 88(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s9, 84(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s10, 80(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s11, 76(sp) # 4-byte Folded Spill +; RV32I-NEXT: lbu a7, 24(a0) +; RV32I-NEXT: lbu a4, 25(a0) +; RV32I-NEXT: lbu t2, 26(a0) +; RV32I-NEXT: lbu t5, 27(a0) +; RV32I-NEXT: lbu a6, 28(a0) +; RV32I-NEXT: lbu t1, 29(a0) +; RV32I-NEXT: lbu t3, 30(a0) +; RV32I-NEXT: lbu t4, 31(a0) +; RV32I-NEXT: lbu t6, 16(a0) +; RV32I-NEXT: lbu t0, 17(a0) +; RV32I-NEXT: lbu s1, 18(a0) ; RV32I-NEXT: lbu s2, 19(a0) -; RV32I-NEXT: lbu s1, 20(a0) -; RV32I-NEXT: lbu s3, 21(a0) -; RV32I-NEXT: lbu s4, 22(a0) +; RV32I-NEXT: lbu s0, 20(a0) +; RV32I-NEXT: lbu s5, 21(a0) +; RV32I-NEXT: lbu s6, 22(a0) ; RV32I-NEXT: lbu s7, 23(a0) ; RV32I-NEXT: lbu a3, 9(a0) -; RV32I-NEXT: lbu a6, 8(a0) -; RV32I-NEXT: lbu s5, 10(a0) -; RV32I-NEXT: lbu s6, 11(a0) +; RV32I-NEXT: lbu a5, 8(a0) +; RV32I-NEXT: lbu s3, 10(a0) +; RV32I-NEXT: lbu s4, 11(a0) ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a3, a6 -; RV32I-NEXT: slli s5, s5, 16 -; RV32I-NEXT: slli s6, s6, 24 -; RV32I-NEXT: or a3, s5, a3 -; RV32I-NEXT: or a3, s6, a3 -; RV32I-NEXT: lbu a6, 13(a0) -; RV32I-NEXT: lbu s5, 12(a0) -; RV32I-NEXT: lbu s6, 14(a0) +; RV32I-NEXT: or a3, a3, a5 +; RV32I-NEXT: slli s3, s3, 16 +; RV32I-NEXT: slli s4, s4, 24 +; RV32I-NEXT: or a3, s3, a3 +; RV32I-NEXT: or a3, s4, a3 +; RV32I-NEXT: lbu a5, 13(a0) +; RV32I-NEXT: lbu s3, 12(a0) +; RV32I-NEXT: lbu s4, 14(a0) ; RV32I-NEXT: lbu s8, 15(a0) -; RV32I-NEXT: slli a6, a6, 8 -; RV32I-NEXT: or a6, a6, s5 -; RV32I-NEXT: slli s6, s6, 16 +; RV32I-NEXT: slli a5, a5, 8 +; RV32I-NEXT: or a5, a5, s3 +; RV32I-NEXT: slli s4, s4, 16 ; RV32I-NEXT: slli s8, s8, 24 -; RV32I-NEXT: or a6, s6, a6 -; RV32I-NEXT: or a6, s8, a6 -; RV32I-NEXT: sw a6, 88(sp) # 4-byte Folded Spill -; RV32I-NEXT: lbu a6, 1(a0) -; RV32I-NEXT: lbu s5, 0(a0) -; RV32I-NEXT: lbu s6, 2(a0) +; RV32I-NEXT: or a5, s4, a5 +; RV32I-NEXT: or a5, s8, a5 +; RV32I-NEXT: sw a5, 72(sp) # 4-byte Folded Spill +; RV32I-NEXT: lbu a5, 1(a0) +; RV32I-NEXT: lbu s3, 0(a0) +; RV32I-NEXT: lbu s4, 2(a0) ; RV32I-NEXT: lbu s8, 3(a0) -; RV32I-NEXT: slli a6, a6, 8 -; RV32I-NEXT: or a6, a6, s5 -; RV32I-NEXT: slli s6, s6, 16 +; RV32I-NEXT: slli a5, a5, 8 +; RV32I-NEXT: or a5, a5, s3 +; RV32I-NEXT: slli s4, s4, 16 ; RV32I-NEXT: slli s8, s8, 24 -; RV32I-NEXT: or a6, s6, a6 -; RV32I-NEXT: or s5, s8, a6 -; RV32I-NEXT: lbu a6, 5(a0) -; RV32I-NEXT: lbu s6, 4(a0) +; RV32I-NEXT: or a5, s4, a5 +; RV32I-NEXT: or s4, s8, a5 +; RV32I-NEXT: lbu a5, 5(a0) +; RV32I-NEXT: lbu s3, 4(a0) ; RV32I-NEXT: lbu s8, 6(a0) ; RV32I-NEXT: lbu a0, 7(a0) -; RV32I-NEXT: slli a6, a6, 8 -; RV32I-NEXT: or a6, a6, s6 +; RV32I-NEXT: slli a5, a5, 8 +; RV32I-NEXT: or a5, a5, s3 ; RV32I-NEXT: slli s8, s8, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a6, s8, a6 -; RV32I-NEXT: or s10, a0, a6 +; RV32I-NEXT: or a5, s8, a5 +; RV32I-NEXT: or s8, a0, a5 ; RV32I-NEXT: lbu a0, 1(a1) -; RV32I-NEXT: lbu a6, 0(a1) -; RV32I-NEXT: lbu s6, 2(a1) +; RV32I-NEXT: lbu a5, 0(a1) +; RV32I-NEXT: lbu s3, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a0, a0, 8 -; RV32I-NEXT: or a0, a0, a6 -; RV32I-NEXT: slli s6, s6, 16 +; RV32I-NEXT: or a0, a0, a5 +; RV32I-NEXT: slli s3, s3, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a0, s6, a0 -; RV32I-NEXT: or a6, a1, a0 -; RV32I-NEXT: sll s6, s10, a6 -; RV32I-NEXT: srli s8, s5, 1 -; RV32I-NEXT: addi a0, a6, -224 -; RV32I-NEXT: sw s5, 80(sp) # 4-byte Folded Spill -; RV32I-NEXT: sll a1, s5, a6 -; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a1, 76(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s6, 72(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s8, 68(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgez a0, .LBB10_2 +; RV32I-NEXT: or a5, s3, a0 +; RV32I-NEXT: or a5, a1, a5 +; RV32I-NEXT: sll a1, s8, a5 +; RV32I-NEXT: not a0, a5 +; RV32I-NEXT: srli s3, s4, 1 +; RV32I-NEXT: srl s3, s3, a0 +; RV32I-NEXT: or s10, a1, s3 +; RV32I-NEXT: addi s3, a5, -224 +; RV32I-NEXT: sw s4, 56(sp) # 4-byte Folded Spill +; RV32I-NEXT: sll a1, s4, a5 +; RV32I-NEXT: sw s10, 64(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s3, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz s3, .LBB10_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: addi a0, a6, -192 -; RV32I-NEXT: xori a0, a0, 31 -; RV32I-NEXT: srl a0, s8, a0 -; RV32I-NEXT: or a1, s6, a0 +; RV32I-NEXT: mv s10, a1 ; RV32I-NEXT: .LBB10_2: -; RV32I-NEXT: slli s6, t2, 8 -; RV32I-NEXT: slli s8, t4, 16 -; RV32I-NEXT: slli s9, s2, 24 -; RV32I-NEXT: slli s11, s3, 8 -; RV32I-NEXT: slli s4, s4, 16 -; RV32I-NEXT: slli ra, s7, 24 -; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll s3, a0, a6 -; RV32I-NEXT: srli a0, a3, 1 -; RV32I-NEXT: addi s2, a6, -128 -; RV32I-NEXT: xori t2, s2, 31 -; RV32I-NEXT: addi t4, a6, -160 -; RV32I-NEXT: sll s7, a3, a6 -; RV32I-NEXT: sw s7, 60(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a0, 56(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgez t4, .LBB10_4 +; RV32I-NEXT: sw a1, 52(sp) # 4-byte Folded Spill +; RV32I-NEXT: slli s3, t0, 8 +; RV32I-NEXT: slli s11, s1, 16 +; RV32I-NEXT: slli s2, s2, 24 +; RV32I-NEXT: slli ra, s5, 8 +; RV32I-NEXT: slli s6, s6, 16 +; RV32I-NEXT: slli s7, s7, 24 +; RV32I-NEXT: lw a1, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: sll a1, a1, a5 +; RV32I-NEXT: srli t0, a3, 1 +; RV32I-NEXT: srl s1, t0, a0 +; RV32I-NEXT: or s5, a1, s1 +; RV32I-NEXT: addi s9, a5, -160 +; RV32I-NEXT: sll a1, a3, a5 +; RV32I-NEXT: sw s5, 44(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz s9, .LBB10_4 ; RV32I-NEXT: # %bb.3: -; RV32I-NEXT: srl a0, a0, t2 -; RV32I-NEXT: or s7, s3, a0 +; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: .LBB10_4: -; RV32I-NEXT: slli a0, t3, 8 -; RV32I-NEXT: slli t6, t6, 16 -; RV32I-NEXT: slli s0, s0, 24 -; RV32I-NEXT: or a4, s6, a4 -; RV32I-NEXT: or s3, s9, s8 -; RV32I-NEXT: or s1, s11, s1 -; RV32I-NEXT: or s4, ra, s4 -; RV32I-NEXT: neg s11, a6 -; RV32I-NEXT: srl s8, s10, s11 -; RV32I-NEXT: li s6, 160 -; RV32I-NEXT: li s5, 64 -; RV32I-NEXT: sub s6, s6, a6 -; RV32I-NEXT: sw s6, 40(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgeu s2, s5, .LBB10_6 +; RV32I-NEXT: sw a1, 48(sp) # 4-byte Folded Spill +; RV32I-NEXT: slli a4, a4, 8 +; RV32I-NEXT: slli a1, t2, 16 +; RV32I-NEXT: slli t5, t5, 24 +; RV32I-NEXT: or s1, s3, t6 +; RV32I-NEXT: or s2, s2, s11 +; RV32I-NEXT: or s0, ra, s0 +; RV32I-NEXT: or s3, s7, s6 +; RV32I-NEXT: neg s6, a5 +; RV32I-NEXT: srl ra, s8, s6 +; RV32I-NEXT: li s7, 160 +; RV32I-NEXT: addi t6, a5, -128 +; RV32I-NEXT: li t2, 64 +; RV32I-NEXT: sub s7, s7, a5 +; RV32I-NEXT: sw s7, 36(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgeu t6, t2, .LBB10_6 ; RV32I-NEXT: # %bb.5: -; RV32I-NEXT: slti a1, s6, 0 -; RV32I-NEXT: neg a1, a1 -; RV32I-NEXT: and a1, a1, s8 -; RV32I-NEXT: or a1, s7, a1 +; RV32I-NEXT: slti s7, s7, 0 +; RV32I-NEXT: neg s7, s7 +; RV32I-NEXT: and s7, s7, ra +; RV32I-NEXT: or s10, s5, s7 ; RV32I-NEXT: .LBB10_6: -; RV32I-NEXT: slli t0, t0, 8 -; RV32I-NEXT: slli t1, t1, 16 -; RV32I-NEXT: slli s6, t5, 24 -; RV32I-NEXT: or t5, a0, a5 -; RV32I-NEXT: or t6, s0, t6 -; RV32I-NEXT: or a5, s3, a4 -; RV32I-NEXT: or s7, s4, s1 -; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: beqz s2, .LBB10_8 +; RV32I-NEXT: slli t1, t1, 8 +; RV32I-NEXT: slli t3, t3, 16 +; RV32I-NEXT: slli t4, t4, 24 +; RV32I-NEXT: or a4, a4, a7 +; RV32I-NEXT: or s5, t5, a1 +; RV32I-NEXT: or t5, s2, s1 +; RV32I-NEXT: or s2, s3, s0 +; RV32I-NEXT: lw s3, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: beqz t6, .LBB10_8 ; RV32I-NEXT: # %bb.7: -; RV32I-NEXT: mv a0, a1 +; RV32I-NEXT: mv a1, s10 ; RV32I-NEXT: .LBB10_8: -; RV32I-NEXT: or a1, t0, a7 -; RV32I-NEXT: or t0, s6, t1 -; RV32I-NEXT: or a7, t6, t5 -; RV32I-NEXT: sll t5, s7, a6 -; RV32I-NEXT: srli s1, a5, 1 -; RV32I-NEXT: addi a4, a6, -64 -; RV32I-NEXT: xori a4, a4, 31 -; RV32I-NEXT: addi s4, a6, -96 -; RV32I-NEXT: sll t6, a5, a6 -; RV32I-NEXT: sw a4, 20(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz s4, .LBB10_10 +; RV32I-NEXT: or a7, t1, a6 +; RV32I-NEXT: or t3, t4, t3 +; RV32I-NEXT: or a6, s5, a4 +; RV32I-NEXT: sll a4, s2, a5 +; RV32I-NEXT: srli t1, t5, 1 +; RV32I-NEXT: srl t1, t1, a0 +; RV32I-NEXT: or t1, a4, t1 +; RV32I-NEXT: addi t4, a5, -96 +; RV32I-NEXT: sll a4, t5, a5 +; RV32I-NEXT: sw a4, 60(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv a4, t1 +; RV32I-NEXT: sw t4, 40(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz t4, .LBB10_10 ; RV32I-NEXT: # %bb.9: -; RV32I-NEXT: mv a4, t6 -; RV32I-NEXT: j .LBB10_11 +; RV32I-NEXT: lw a4, 60(sp) # 4-byte Folded Reload ; RV32I-NEXT: .LBB10_10: -; RV32I-NEXT: srl a4, s1, a4 -; RV32I-NEXT: or a4, t5, a4 -; RV32I-NEXT: .LBB10_11: -; RV32I-NEXT: or t1, t0, a1 -; RV32I-NEXT: xori ra, a6, 31 -; RV32I-NEXT: addi s0, a6, -32 -; RV32I-NEXT: sll t0, a7, a6 -; RV32I-NEXT: sw t6, 64(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw t0, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgez s0, .LBB10_13 -; RV32I-NEXT: # %bb.12: -; RV32I-NEXT: sll a1, t1, a6 -; RV32I-NEXT: srli t0, a7, 1 -; RV32I-NEXT: srl t0, t0, ra -; RV32I-NEXT: or t0, a1, t0 -; RV32I-NEXT: .LBB10_13: -; RV32I-NEXT: srl s6, s7, s11 -; RV32I-NEXT: li a1, 32 -; RV32I-NEXT: sub s3, a1, a6 -; RV32I-NEXT: slti t6, s3, 0 -; RV32I-NEXT: neg t6, t6 -; RV32I-NEXT: bgeu a6, s5, .LBB10_15 -; RV32I-NEXT: # %bb.14: -; RV32I-NEXT: and a4, t6, s6 -; RV32I-NEXT: or a4, t0, a4 -; RV32I-NEXT: .LBB10_15: -; RV32I-NEXT: sw s6, 36(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw t6, 44(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s4, 48(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s8, 84(sp) # 4-byte Folded Spill -; RV32I-NEXT: mv t0, t1 -; RV32I-NEXT: beqz a6, .LBB10_17 -; RV32I-NEXT: # %bb.16: -; RV32I-NEXT: mv t0, a4 -; RV32I-NEXT: .LBB10_17: -; RV32I-NEXT: lw a4, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl t3, a4, s11 +; RV32I-NEXT: or a7, t3, a7 +; RV32I-NEXT: addi s4, a5, -32 +; RV32I-NEXT: sll t3, a6, a5 +; RV32I-NEXT: sw t3, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgez s4, .LBB10_12 +; RV32I-NEXT: # %bb.11: +; RV32I-NEXT: sll t3, a7, a5 +; RV32I-NEXT: srli s0, a6, 1 +; RV32I-NEXT: srl a0, s0, a0 +; RV32I-NEXT: or t3, t3, a0 +; RV32I-NEXT: .LBB10_12: +; RV32I-NEXT: srl s5, s2, s6 +; RV32I-NEXT: li a0, 32 +; RV32I-NEXT: sub s0, a0, a5 +; RV32I-NEXT: sw s0, 68(sp) # 4-byte Folded Spill +; RV32I-NEXT: slti s1, s0, 0 +; RV32I-NEXT: neg s7, s1 +; RV32I-NEXT: bgeu a5, t2, .LBB10_14 +; RV32I-NEXT: # %bb.13: +; RV32I-NEXT: and a4, s7, s5 +; RV32I-NEXT: or a4, t3, a4 +; RV32I-NEXT: .LBB10_14: +; RV32I-NEXT: sw s5, 28(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv t3, a7 +; RV32I-NEXT: beqz a5, .LBB10_16 +; RV32I-NEXT: # %bb.15: +; RV32I-NEXT: mv t3, a4 +; RV32I-NEXT: .LBB10_16: +; RV32I-NEXT: srl s10, s3, s6 ; RV32I-NEXT: li a4, 96 -; RV32I-NEXT: sub s8, a4, a6 -; RV32I-NEXT: slti a4, s8, 0 +; RV32I-NEXT: sub s5, a4, a5 +; RV32I-NEXT: slti a4, s5, 0 ; RV32I-NEXT: neg a4, a4 -; RV32I-NEXT: li s9, 128 -; RV32I-NEXT: sub t6, s9, a6 -; RV32I-NEXT: sltiu s6, t6, 64 -; RV32I-NEXT: neg s6, s6 -; RV32I-NEXT: bgeu a6, s9, .LBB10_19 -; RV32I-NEXT: # %bb.18: -; RV32I-NEXT: and a0, a4, t3 -; RV32I-NEXT: and a0, s6, a0 -; RV32I-NEXT: or a0, t0, a0 -; RV32I-NEXT: .LBB10_19: -; RV32I-NEXT: beqz a6, .LBB10_21 -; RV32I-NEXT: # %bb.20: -; RV32I-NEXT: mv t1, a0 -; RV32I-NEXT: .LBB10_21: -; RV32I-NEXT: neg t0, t6 -; RV32I-NEXT: sub s9, a1, t6 -; RV32I-NEXT: sll a0, a3, t0 -; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz s9, .LBB10_24 -; RV32I-NEXT: # %bb.22: -; RV32I-NEXT: mv a1, a0 -; RV32I-NEXT: bgeu t6, s5, .LBB10_25 +; RV32I-NEXT: li t2, 128 +; RV32I-NEXT: sub s11, t2, a5 +; RV32I-NEXT: sltiu s1, s11, 64 +; RV32I-NEXT: neg s1, s1 +; RV32I-NEXT: bgeu a5, t2, .LBB10_18 +; RV32I-NEXT: # %bb.17: +; RV32I-NEXT: and a1, a4, s10 +; RV32I-NEXT: and a1, s1, a1 +; RV32I-NEXT: or a1, t3, a1 +; RV32I-NEXT: .LBB10_18: +; RV32I-NEXT: li t2, 64 +; RV32I-NEXT: sw s1, 32(sp) # 4-byte Folded Spill +; RV32I-NEXT: beqz a5, .LBB10_20 +; RV32I-NEXT: # %bb.19: +; RV32I-NEXT: mv a7, a1 +; RV32I-NEXT: .LBB10_20: +; RV32I-NEXT: neg s1, s11 +; RV32I-NEXT: sub t3, a0, s11 +; RV32I-NEXT: sll a1, a3, s1 +; RV32I-NEXT: bltz t3, .LBB10_23 +; RV32I-NEXT: # %bb.21: +; RV32I-NEXT: mv a0, a1 +; RV32I-NEXT: bgeu s11, t2, .LBB10_24 +; RV32I-NEXT: .LBB10_22: +; RV32I-NEXT: and a4, a4, ra +; RV32I-NEXT: or a4, a4, a0 +; RV32I-NEXT: mv a0, s8 +; RV32I-NEXT: bnez s11, .LBB10_25 +; RV32I-NEXT: j .LBB10_26 ; RV32I-NEXT: .LBB10_23: -; RV32I-NEXT: lw t0, 84(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a4, t0 -; RV32I-NEXT: or a4, a4, a1 -; RV32I-NEXT: mv a1, s10 -; RV32I-NEXT: bnez t6, .LBB10_26 -; RV32I-NEXT: j .LBB10_27 +; RV32I-NEXT: sll a0, s3, s1 +; RV32I-NEXT: sub s1, t2, s11 +; RV32I-NEXT: not s1, s1 +; RV32I-NEXT: srl t0, t0, s1 +; RV32I-NEXT: or a0, a0, t0 +; RV32I-NEXT: bltu s11, t2, .LBB10_22 ; RV32I-NEXT: .LBB10_24: -; RV32I-NEXT: lw a1, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a1, a1, t0 -; RV32I-NEXT: sub t0, s5, t6 -; RV32I-NEXT: xori t0, t0, 31 -; RV32I-NEXT: lw s6, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl t0, s6, t0 -; RV32I-NEXT: or a1, a1, t0 -; RV32I-NEXT: bltu t6, s5, .LBB10_23 +; RV32I-NEXT: and a4, s7, s10 +; RV32I-NEXT: mv a0, s8 +; RV32I-NEXT: beqz s11, .LBB10_26 ; RV32I-NEXT: .LBB10_25: -; RV32I-NEXT: lw a1, 44(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a1, t3 -; RV32I-NEXT: mv a1, s10 -; RV32I-NEXT: beqz t6, .LBB10_27 +; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: .LBB10_26: -; RV32I-NEXT: mv a1, a4 -; RV32I-NEXT: .LBB10_27: -; RV32I-NEXT: bltz s0, .LBB10_29 -; RV32I-NEXT: # %bb.28: +; RV32I-NEXT: bltz s4, .LBB10_28 +; RV32I-NEXT: # %bb.27: +; RV32I-NEXT: lw t1, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: .LBB10_28: +; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sltiu t0, a5, 64 ; RV32I-NEXT: lw a4, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: j .LBB10_30 -; RV32I-NEXT: .LBB10_29: -; RV32I-NEXT: srl a4, s1, ra -; RV32I-NEXT: or a4, t5, a4 +; RV32I-NEXT: mv s0, s9 +; RV32I-NEXT: bltz s9, .LBB10_30 +; RV32I-NEXT: # %bb.29: +; RV32I-NEXT: lw a4, 52(sp) # 4-byte Folded Reload ; RV32I-NEXT: .LBB10_30: -; RV32I-NEXT: sltiu t0, a6, 64 -; RV32I-NEXT: sw ra, 52(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz t4, .LBB10_32 +; RV32I-NEXT: neg s9, t0 +; RV32I-NEXT: sltiu t0, t6, 64 +; RV32I-NEXT: neg s1, t0 +; RV32I-NEXT: li t0, 128 +; RV32I-NEXT: bltu a5, t0, .LBB10_32 ; RV32I-NEXT: # %bb.31: -; RV32I-NEXT: lw t2, 76(sp) # 4-byte Folded Reload -; RV32I-NEXT: j .LBB10_33 +; RV32I-NEXT: and a4, s1, a4 +; RV32I-NEXT: mv t0, s2 +; RV32I-NEXT: bnez a5, .LBB10_33 +; RV32I-NEXT: j .LBB10_34 ; RV32I-NEXT: .LBB10_32: -; RV32I-NEXT: lw t5, 68(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl t2, t5, t2 -; RV32I-NEXT: lw t5, 72(sp) # 4-byte Folded Reload -; RV32I-NEXT: or t2, t5, t2 +; RV32I-NEXT: and a4, s9, t1 +; RV32I-NEXT: or a4, a4, a0 +; RV32I-NEXT: mv t0, s2 +; RV32I-NEXT: beqz a5, .LBB10_34 ; RV32I-NEXT: .LBB10_33: -; RV32I-NEXT: neg ra, t0 -; RV32I-NEXT: sltiu t0, s2, 64 -; RV32I-NEXT: neg t0, t0 -; RV32I-NEXT: li t5, 128 -; RV32I-NEXT: bltu a6, t5, .LBB10_35 -; RV32I-NEXT: # %bb.34: -; RV32I-NEXT: and a1, t0, t2 -; RV32I-NEXT: mv s1, s7 -; RV32I-NEXT: bnez a6, .LBB10_36 +; RV32I-NEXT: mv t0, a4 +; RV32I-NEXT: .LBB10_34: +; RV32I-NEXT: srl t1, a3, s6 +; RV32I-NEXT: slli a4, s3, 1 +; RV32I-NEXT: sub a0, t2, a5 +; RV32I-NEXT: not a0, a0 +; RV32I-NEXT: lw s3, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s10, 20(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz s3, .LBB10_36 +; RV32I-NEXT: # %bb.35: +; RV32I-NEXT: mv s3, s10 ; RV32I-NEXT: j .LBB10_37 -; RV32I-NEXT: .LBB10_35: -; RV32I-NEXT: and a4, ra, a4 -; RV32I-NEXT: or a1, a4, a1 -; RV32I-NEXT: mv s1, s7 -; RV32I-NEXT: beqz a6, .LBB10_37 ; RV32I-NEXT: .LBB10_36: -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: sll a0, a4, a0 +; RV32I-NEXT: or s3, t1, a0 ; RV32I-NEXT: .LBB10_37: -; RV32I-NEXT: srl a1, a3, s11 -; RV32I-NEXT: lw a4, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: slli a4, a4, 1 -; RV32I-NEXT: sub t2, s5, a6 -; RV32I-NEXT: xori t2, t2, 31 -; RV32I-NEXT: sw t2, 32(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a1, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz s3, .LBB10_39 +; RV32I-NEXT: lw a0, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: srl s10, a0, s6 +; RV32I-NEXT: slli s8, s8, 1 +; RV32I-NEXT: not a0, s11 +; RV32I-NEXT: bltz s5, .LBB10_39 ; RV32I-NEXT: # %bb.38: -; RV32I-NEXT: mv s4, t3 -; RV32I-NEXT: mv s6, t3 -; RV32I-NEXT: j .LBB10_40 +; RV32I-NEXT: mv t4, s8 +; RV32I-NEXT: mv s7, s10 +; RV32I-NEXT: mv s8, ra +; RV32I-NEXT: bltu s11, t2, .LBB10_40 +; RV32I-NEXT: j .LBB10_41 ; RV32I-NEXT: .LBB10_39: -; RV32I-NEXT: mv s4, t3 -; RV32I-NEXT: sll t2, a4, t2 -; RV32I-NEXT: or s6, a1, t2 +; RV32I-NEXT: mv t4, s8 +; RV32I-NEXT: sll s8, s8, a0 +; RV32I-NEXT: mv s7, s10 +; RV32I-NEXT: or s8, s10, s8 +; RV32I-NEXT: bgeu s11, t2, .LBB10_41 ; RV32I-NEXT: .LBB10_40: -; RV32I-NEXT: li s5, 64 -; RV32I-NEXT: lw t2, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl t2, t2, s11 -; RV32I-NEXT: slli s10, s10, 1 -; RV32I-NEXT: xori t5, t6, 31 -; RV32I-NEXT: bltz s8, .LBB10_42 -; RV32I-NEXT: # %bb.41: -; RV32I-NEXT: mv a1, s10 -; RV32I-NEXT: mv t3, t2 -; RV32I-NEXT: lw s10, 84(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltu t6, s5, .LBB10_43 -; RV32I-NEXT: j .LBB10_44 -; RV32I-NEXT: .LBB10_42: -; RV32I-NEXT: mv a1, s10 -; RV32I-NEXT: sll s10, s10, t5 -; RV32I-NEXT: mv t3, t2 -; RV32I-NEXT: or s10, t2, s10 -; RV32I-NEXT: bgeu t6, s5, .LBB10_44 +; RV32I-NEXT: slti t3, t3, 0 +; RV32I-NEXT: neg t3, t3 +; RV32I-NEXT: and a1, t3, a1 +; RV32I-NEXT: or s3, s8, a1 +; RV32I-NEXT: .LBB10_41: +; RV32I-NEXT: beqz s11, .LBB10_43 +; RV32I-NEXT: # %bb.42: +; RV32I-NEXT: sw s3, 56(sp) # 4-byte Folded Spill ; RV32I-NEXT: .LBB10_43: -; RV32I-NEXT: slti s6, s9, 0 -; RV32I-NEXT: neg s6, s6 -; RV32I-NEXT: and a0, s6, a0 -; RV32I-NEXT: or s6, s10, a0 -; RV32I-NEXT: .LBB10_44: -; RV32I-NEXT: lw s9, 76(sp) # 4-byte Folded Reload -; RV32I-NEXT: beqz t6, .LBB10_46 -; RV32I-NEXT: # %bb.45: -; RV32I-NEXT: sw s6, 80(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv s11, s4 +; RV32I-NEXT: slti a1, s4, 0 +; RV32I-NEXT: neg s8, a1 +; RV32I-NEXT: slti a1, s0, 0 +; RV32I-NEXT: neg a1, a1 +; RV32I-NEXT: li t3, 128 +; RV32I-NEXT: bltu a5, t3, .LBB10_45 +; RV32I-NEXT: # %bb.44: +; RV32I-NEXT: lw s4, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: and t3, a1, s4 +; RV32I-NEXT: and t3, s1, t3 +; RV32I-NEXT: mv s3, t5 +; RV32I-NEXT: bnez a5, .LBB10_46 +; RV32I-NEXT: j .LBB10_47 +; RV32I-NEXT: .LBB10_45: +; RV32I-NEXT: lw t3, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: and t3, s8, t3 +; RV32I-NEXT: and t3, s9, t3 +; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: or t3, t3, s0 +; RV32I-NEXT: lw s4, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: mv s3, t5 +; RV32I-NEXT: beqz a5, .LBB10_47 ; RV32I-NEXT: .LBB10_46: -; RV32I-NEXT: slti a0, s0, 0 -; RV32I-NEXT: neg s10, a0 -; RV32I-NEXT: slti a0, t4, 0 -; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: li t4, 128 -; RV32I-NEXT: bltu a6, t4, .LBB10_48 -; RV32I-NEXT: # %bb.47: -; RV32I-NEXT: and t4, a0, s9 -; RV32I-NEXT: and t0, t0, t4 -; RV32I-NEXT: lw s6, 48(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw t6, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: mv t4, a5 -; RV32I-NEXT: bnez a6, .LBB10_49 -; RV32I-NEXT: j .LBB10_50 -; RV32I-NEXT: .LBB10_48: -; RV32I-NEXT: lw t6, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: and t0, s10, t6 -; RV32I-NEXT: and t0, ra, t0 -; RV32I-NEXT: lw t2, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: or t0, t0, t2 -; RV32I-NEXT: lw s6, 48(sp) # 4-byte Folded Reload -; RV32I-NEXT: mv t4, a5 -; RV32I-NEXT: beqz a6, .LBB10_50 +; RV32I-NEXT: mv s3, t3 +; RV32I-NEXT: .LBB10_47: +; RV32I-NEXT: lw t3, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgez t3, .LBB10_49 +; RV32I-NEXT: # %bb.48: +; RV32I-NEXT: srl t3, t5, s6 +; RV32I-NEXT: slli s2, s2, 1 +; RV32I-NEXT: lw t5, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: sll t5, s2, t5 +; RV32I-NEXT: or t3, t3, t5 +; RV32I-NEXT: sw t3, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: .LBB10_49: -; RV32I-NEXT: mv t4, t0 -; RV32I-NEXT: .LBB10_50: -; RV32I-NEXT: bgez s3, .LBB10_52 -; RV32I-NEXT: # %bb.51: -; RV32I-NEXT: srl a5, a5, s11 -; RV32I-NEXT: slli s7, s7, 1 -; RV32I-NEXT: lw t0, 32(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll t0, s7, t0 -; RV32I-NEXT: or a5, a5, t0 -; RV32I-NEXT: sw a5, 36(sp) # 4-byte Folded Spill +; RV32I-NEXT: lw s2, 40(sp) # 4-byte Folded Reload +; RV32I-NEXT: slti t3, s2, 0 +; RV32I-NEXT: neg t5, t3 +; RV32I-NEXT: bltu a5, t2, .LBB10_51 +; RV32I-NEXT: # %bb.50: +; RV32I-NEXT: lw t3, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: and s1, t5, t3 +; RV32I-NEXT: mv t3, a6 +; RV32I-NEXT: bnez a5, .LBB10_52 +; RV32I-NEXT: j .LBB10_53 +; RV32I-NEXT: .LBB10_51: +; RV32I-NEXT: lw t3, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: and t3, s8, t3 +; RV32I-NEXT: lw s1, 28(sp) # 4-byte Folded Reload +; RV32I-NEXT: or s1, t3, s1 +; RV32I-NEXT: mv t3, a6 +; RV32I-NEXT: beqz a5, .LBB10_53 ; RV32I-NEXT: .LBB10_52: -; RV32I-NEXT: lw s5, 60(sp) # 4-byte Folded Reload -; RV32I-NEXT: mv s7, t3 -; RV32I-NEXT: slti a5, s6, 0 -; RV32I-NEXT: neg a5, a5 -; RV32I-NEXT: li t2, 64 -; RV32I-NEXT: mv t3, a1 -; RV32I-NEXT: bltu a6, t2, .LBB10_54 -; RV32I-NEXT: # %bb.53: -; RV32I-NEXT: and t6, a5, t6 -; RV32I-NEXT: mv t0, a7 -; RV32I-NEXT: bnez a6, .LBB10_55 -; RV32I-NEXT: j .LBB10_56 -; RV32I-NEXT: .LBB10_54: -; RV32I-NEXT: lw t0, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: and t0, s10, t0 -; RV32I-NEXT: lw t6, 36(sp) # 4-byte Folded Reload -; RV32I-NEXT: or t6, t0, t6 -; RV32I-NEXT: mv t0, a7 -; RV32I-NEXT: beqz a6, .LBB10_56 +; RV32I-NEXT: mv t3, s1 +; RV32I-NEXT: .LBB10_53: +; RV32I-NEXT: bgez s5, .LBB10_55 +; RV32I-NEXT: # %bb.54: +; RV32I-NEXT: sll a0, a4, a0 +; RV32I-NEXT: or a0, t1, a0 +; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: .LBB10_55: -; RV32I-NEXT: mv t0, t6 -; RV32I-NEXT: .LBB10_56: -; RV32I-NEXT: bgez s8, .LBB10_58 -; RV32I-NEXT: # %bb.57: -; RV32I-NEXT: sll a4, a4, t5 -; RV32I-NEXT: lw a1, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: or s4, a1, a4 -; RV32I-NEXT: .LBB10_58: -; RV32I-NEXT: lw t5, 72(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw t6, 68(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw a4, 84(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw a1, 40(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz a1, .LBB10_61 -; RV32I-NEXT: # %bb.59: -; RV32I-NEXT: mv a1, a4 -; RV32I-NEXT: bgeu s2, t2, .LBB10_62 -; RV32I-NEXT: .LBB10_60: -; RV32I-NEXT: and a0, a0, s5 -; RV32I-NEXT: or a1, a0, a1 +; RV32I-NEXT: lw a4, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t1, 32(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a0, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a0, .LBB10_58 +; RV32I-NEXT: # %bb.56: +; RV32I-NEXT: mv a0, ra +; RV32I-NEXT: bgeu t6, t2, .LBB10_59 +; RV32I-NEXT: .LBB10_57: +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: or a1, a1, a0 ; RV32I-NEXT: mv a0, a3 -; RV32I-NEXT: bnez s2, .LBB10_63 -; RV32I-NEXT: j .LBB10_64 -; RV32I-NEXT: .LBB10_61: -; RV32I-NEXT: li a1, 192 -; RV32I-NEXT: sub a1, a1, a6 -; RV32I-NEXT: xori a1, a1, 31 -; RV32I-NEXT: sll a1, t3, a1 -; RV32I-NEXT: or a1, s7, a1 -; RV32I-NEXT: bltu s2, t2, .LBB10_60 -; RV32I-NEXT: .LBB10_62: -; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: bnez t6, .LBB10_60 +; RV32I-NEXT: j .LBB10_61 +; RV32I-NEXT: .LBB10_58: +; RV32I-NEXT: li a0, 192 +; RV32I-NEXT: sub a0, a0, a5 +; RV32I-NEXT: not a0, a0 +; RV32I-NEXT: sll a0, t4, a0 +; RV32I-NEXT: or a0, s7, a0 +; RV32I-NEXT: bltu t6, t2, .LBB10_57 +; RV32I-NEXT: .LBB10_59: +; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: and a1, a0, s9 +; RV32I-NEXT: and a1, a0, s4 ; RV32I-NEXT: mv a0, a3 -; RV32I-NEXT: beqz s2, .LBB10_64 -; RV32I-NEXT: .LBB10_63: +; RV32I-NEXT: beqz t6, .LBB10_61 +; RV32I-NEXT: .LBB10_60: ; RV32I-NEXT: mv a0, a1 -; RV32I-NEXT: .LBB10_64: +; RV32I-NEXT: .LBB10_61: ; RV32I-NEXT: li a1, 128 -; RV32I-NEXT: bltu a6, a1, .LBB10_69 -; RV32I-NEXT: # %bb.65: -; RV32I-NEXT: bnez a6, .LBB10_70 +; RV32I-NEXT: bltu a5, a1, .LBB10_70 +; RV32I-NEXT: # %bb.62: +; RV32I-NEXT: lw t3, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: bnez a5, .LBB10_71 +; RV32I-NEXT: .LBB10_63: +; RV32I-NEXT: mv a0, t3 +; RV32I-NEXT: bgez s2, .LBB10_72 +; RV32I-NEXT: .LBB10_64: +; RV32I-NEXT: bgez s11, .LBB10_73 +; RV32I-NEXT: .LBB10_65: +; RV32I-NEXT: bltu a5, t2, .LBB10_74 ; RV32I-NEXT: .LBB10_66: -; RV32I-NEXT: bltz s6, .LBB10_71 +; RV32I-NEXT: bnez a5, .LBB10_75 ; RV32I-NEXT: .LBB10_67: -; RV32I-NEXT: mv a0, s9 -; RV32I-NEXT: bgez s0, .LBB10_72 +; RV32I-NEXT: lw a0, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a0, .LBB10_76 ; RV32I-NEXT: .LBB10_68: -; RV32I-NEXT: lw a1, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw t0, 52(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl a1, a1, t0 -; RV32I-NEXT: lw t0, 28(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a1, t0, a1 -; RV32I-NEXT: bltu a6, t2, .LBB10_73 -; RV32I-NEXT: j .LBB10_74 +; RV32I-NEXT: sltiu a0, a5, 128 +; RV32I-NEXT: bltu a5, t2, .LBB10_77 ; RV32I-NEXT: .LBB10_69: -; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a0, s4 -; RV32I-NEXT: or a0, t0, a0 -; RV32I-NEXT: beqz a6, .LBB10_66 +; RV32I-NEXT: and a1, t5, s4 +; RV32I-NEXT: neg a4, a0 +; RV32I-NEXT: bnez a5, .LBB10_78 +; RV32I-NEXT: j .LBB10_79 ; RV32I-NEXT: .LBB10_70: -; RV32I-NEXT: mv a7, a0 -; RV32I-NEXT: bgez s6, .LBB10_67 -; RV32I-NEXT: .LBB10_71: ; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl a0, t6, a0 -; RV32I-NEXT: or a0, t5, a0 -; RV32I-NEXT: bltz s0, .LBB10_68 +; RV32I-NEXT: and a0, t1, a0 +; RV32I-NEXT: or a0, t3, a0 +; RV32I-NEXT: lw t3, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: beqz a5, .LBB10_63 +; RV32I-NEXT: .LBB10_71: +; RV32I-NEXT: mv a6, a0 +; RV32I-NEXT: mv a0, t3 +; RV32I-NEXT: bltz s2, .LBB10_64 ; RV32I-NEXT: .LBB10_72: -; RV32I-NEXT: mv a1, s5 -; RV32I-NEXT: bgeu a6, t2, .LBB10_74 +; RV32I-NEXT: mv a0, s4 +; RV32I-NEXT: bltz s11, .LBB10_65 ; RV32I-NEXT: .LBB10_73: -; RV32I-NEXT: lw a0, 44(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a0, a4 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: sw a4, 44(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgeu a5, t2, .LBB10_66 ; RV32I-NEXT: .LBB10_74: -; RV32I-NEXT: bnez a6, .LBB10_78 -; RV32I-NEXT: # %bb.75: -; RV32I-NEXT: bltz s3, .LBB10_79 +; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a0, a0, ra +; RV32I-NEXT: lw a1, 44(sp) # 4-byte Folded Reload +; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: beqz a5, .LBB10_67 +; RV32I-NEXT: .LBB10_75: +; RV32I-NEXT: sw a0, 72(sp) # 4-byte Folded Spill +; RV32I-NEXT: lw a0, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgez a0, .LBB10_68 ; RV32I-NEXT: .LBB10_76: -; RV32I-NEXT: sltiu a0, a6, 128 -; RV32I-NEXT: bltu a6, t2, .LBB10_80 +; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: sll a0, t4, a0 +; RV32I-NEXT: or ra, s7, a0 +; RV32I-NEXT: sltiu a0, a5, 128 +; RV32I-NEXT: bgeu a5, t2, .LBB10_69 ; RV32I-NEXT: .LBB10_77: -; RV32I-NEXT: and a1, a5, s9 +; RV32I-NEXT: and a1, s8, a4 +; RV32I-NEXT: or a1, a1, ra ; RV32I-NEXT: neg a4, a0 -; RV32I-NEXT: bnez a6, .LBB10_81 -; RV32I-NEXT: j .LBB10_82 +; RV32I-NEXT: beqz a5, .LBB10_79 ; RV32I-NEXT: .LBB10_78: -; RV32I-NEXT: sw a0, 88(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgez s3, .LBB10_76 -; RV32I-NEXT: .LBB10_79: -; RV32I-NEXT: lw a0, 32(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a0, t3, a0 -; RV32I-NEXT: or a4, s7, a0 -; RV32I-NEXT: sltiu a0, a6, 128 -; RV32I-NEXT: bgeu a6, t2, .LBB10_77 -; RV32I-NEXT: .LBB10_80: -; RV32I-NEXT: and a1, s10, s5 -; RV32I-NEXT: or a1, a1, a4 -; RV32I-NEXT: neg a4, a0 -; RV32I-NEXT: beqz a6, .LBB10_82 -; RV32I-NEXT: .LBB10_81: ; RV32I-NEXT: mv a3, a1 -; RV32I-NEXT: .LBB10_82: -; RV32I-NEXT: lw a1, 88(sp) # 4-byte Folded Reload +; RV32I-NEXT: .LBB10_79: +; RV32I-NEXT: lw a1, 72(sp) # 4-byte Folded Reload ; RV32I-NEXT: and a1, a4, a1 ; RV32I-NEXT: and a0, a4, a3 -; RV32I-NEXT: bltz s0, .LBB10_84 -; RV32I-NEXT: # %bb.83: -; RV32I-NEXT: mv a3, s9 -; RV32I-NEXT: j .LBB10_85 -; RV32I-NEXT: .LBB10_84: -; RV32I-NEXT: lw a3, 52(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl a3, t6, a3 -; RV32I-NEXT: or a3, t5, a3 -; RV32I-NEXT: .LBB10_85: -; RV32I-NEXT: and a3, ra, a3 +; RV32I-NEXT: bltz s11, .LBB10_81 +; RV32I-NEXT: # %bb.80: +; RV32I-NEXT: mv t3, s4 +; RV32I-NEXT: .LBB10_81: +; RV32I-NEXT: and a3, s9, t3 ; RV32I-NEXT: and a3, a4, a3 -; RV32I-NEXT: and a5, s10, s9 -; RV32I-NEXT: and a5, ra, a5 +; RV32I-NEXT: and a5, s8, s4 +; RV32I-NEXT: and a5, s9, a5 ; RV32I-NEXT: and a4, a4, a5 ; RV32I-NEXT: sb a4, 0(a2) ; RV32I-NEXT: sb a3, 4(a2) @@ -3162,54 +3056,54 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sb a3, 14(a2) ; RV32I-NEXT: srli a1, a1, 8 ; RV32I-NEXT: sb a1, 13(a2) -; RV32I-NEXT: sb t1, 28(a2) +; RV32I-NEXT: sb a7, 28(a2) ; RV32I-NEXT: srli a1, a0, 24 ; RV32I-NEXT: sb a1, 11(a2) ; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: sb a1, 10(a2) ; RV32I-NEXT: srli a0, a0, 8 ; RV32I-NEXT: sb a0, 9(a2) -; RV32I-NEXT: sb a7, 24(a2) -; RV32I-NEXT: srli a0, t1, 24 +; RV32I-NEXT: sb a6, 24(a2) +; RV32I-NEXT: srli a0, a7, 24 ; RV32I-NEXT: sb a0, 31(a2) -; RV32I-NEXT: srli a0, t1, 16 +; RV32I-NEXT: srli a0, a7, 16 ; RV32I-NEXT: sb a0, 30(a2) -; RV32I-NEXT: srli a0, t1, 8 +; RV32I-NEXT: srli a0, a7, 8 ; RV32I-NEXT: sb a0, 29(a2) -; RV32I-NEXT: sb t4, 16(a2) -; RV32I-NEXT: srli a0, a7, 24 +; RV32I-NEXT: sb s3, 16(a2) +; RV32I-NEXT: srli a0, a6, 24 ; RV32I-NEXT: sb a0, 27(a2) -; RV32I-NEXT: srli a0, a7, 16 +; RV32I-NEXT: srli a0, a6, 16 ; RV32I-NEXT: sb a0, 26(a2) -; RV32I-NEXT: srli a0, a7, 8 +; RV32I-NEXT: srli a0, a6, 8 ; RV32I-NEXT: sb a0, 25(a2) -; RV32I-NEXT: srli a0, t4, 24 +; RV32I-NEXT: srli a0, s3, 24 ; RV32I-NEXT: sb a0, 19(a2) -; RV32I-NEXT: srli a0, t4, 16 +; RV32I-NEXT: srli a0, s3, 16 ; RV32I-NEXT: sb a0, 18(a2) -; RV32I-NEXT: srli a0, t4, 8 +; RV32I-NEXT: srli a0, s3, 8 ; RV32I-NEXT: sb a0, 17(a2) -; RV32I-NEXT: sb s1, 20(a2) -; RV32I-NEXT: srli a0, s1, 24 +; RV32I-NEXT: sb t0, 20(a2) +; RV32I-NEXT: srli a0, t0, 24 ; RV32I-NEXT: sb a0, 23(a2) -; RV32I-NEXT: srli a0, s1, 16 +; RV32I-NEXT: srli a0, t0, 16 ; RV32I-NEXT: sb a0, 22(a2) -; RV32I-NEXT: srli s1, s1, 8 -; RV32I-NEXT: sb s1, 21(a2) -; RV32I-NEXT: lw ra, 140(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 136(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 132(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 128(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s3, 124(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s4, 120(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s5, 116(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s6, 112(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s7, 108(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s8, 104(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s9, 100(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s10, 96(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s11, 92(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 144 +; RV32I-NEXT: srli a0, t0, 8 +; RV32I-NEXT: sb a0, 21(a2) +; RV32I-NEXT: lw ra, 124(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 120(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 116(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 112(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s3, 108(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s4, 104(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s5, 100(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s6, 96(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s7, 92(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s8, 88(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s9, 84(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s10, 80(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s11, 76(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 128 ; RV32I-NEXT: ret %src = load i256, ptr %src.ptr, align 1 %bitOff = load i256, ptr %bitOff.ptr, align 1 @@ -3220,12 +3114,10 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-LABEL: ashr_32bytes: ; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -48 -; RV64I-NEXT: sd s0, 40(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s1, 32(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s2, 24(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s3, 16(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s4, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: addi sp, sp, -32 +; RV64I-NEXT: sd s0, 24(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s1, 16(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s2, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lbu a3, 9(a0) ; RV64I-NEXT: lbu a4, 8(a0) ; RV64I-NEXT: lbu a5, 10(a0) @@ -3257,7 +3149,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a6, a6, 16 ; RV64I-NEXT: slli a7, a7, 24 ; RV64I-NEXT: or a4, a6, a4 -; RV64I-NEXT: or t1, a7, a4 +; RV64I-NEXT: or t0, a7, a4 ; RV64I-NEXT: lbu a4, 5(a0) ; RV64I-NEXT: lbu a5, 4(a0) ; RV64I-NEXT: lbu a6, 6(a0) @@ -3267,198 +3159,165 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a6, a6, 16 ; RV64I-NEXT: slli a7, a7, 24 ; RV64I-NEXT: or a4, a6, a4 -; RV64I-NEXT: or a4, a7, a4 -; RV64I-NEXT: lbu a5, 25(a0) -; RV64I-NEXT: lbu a6, 24(a0) -; RV64I-NEXT: lbu a7, 26(a0) -; RV64I-NEXT: lbu t0, 27(a0) -; RV64I-NEXT: slli a5, a5, 8 -; RV64I-NEXT: or a5, a5, a6 -; RV64I-NEXT: slli a7, a7, 16 -; RV64I-NEXT: slli t0, t0, 24 -; RV64I-NEXT: or a6, a7, a5 +; RV64I-NEXT: or t1, a7, a4 +; RV64I-NEXT: slli t1, t1, 32 +; RV64I-NEXT: lbu a4, 25(a0) +; RV64I-NEXT: lbu a5, 24(a0) +; RV64I-NEXT: lbu a6, 26(a0) +; RV64I-NEXT: lbu a7, 27(a0) +; RV64I-NEXT: slli a4, a4, 8 +; RV64I-NEXT: or a4, a4, a5 +; RV64I-NEXT: slli a6, a6, 16 +; RV64I-NEXT: slli a7, a7, 24 +; RV64I-NEXT: or a4, a6, a4 ; RV64I-NEXT: lbu a5, 29(a0) -; RV64I-NEXT: lbu a7, 28(a0) +; RV64I-NEXT: lbu a6, 28(a0) ; RV64I-NEXT: lbu t2, 30(a0) ; RV64I-NEXT: lbu t3, 31(a0) ; RV64I-NEXT: slli a5, a5, 8 -; RV64I-NEXT: or a5, a5, a7 +; RV64I-NEXT: or a5, a5, a6 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli t3, t3, 24 ; RV64I-NEXT: or a5, t2, a5 ; RV64I-NEXT: or a5, t3, a5 -; RV64I-NEXT: slli a7, a5, 32 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: lbu t2, 17(a0) -; RV64I-NEXT: lbu t3, 16(a0) -; RV64I-NEXT: lbu t4, 18(a0) -; RV64I-NEXT: or a7, a6, t0 -; RV64I-NEXT: slli t2, t2, 8 -; RV64I-NEXT: or a6, t2, t3 -; RV64I-NEXT: slli t4, t4, 16 -; RV64I-NEXT: lbu t0, 21(a0) -; RV64I-NEXT: lbu t2, 19(a0) -; RV64I-NEXT: or a6, t4, a6 -; RV64I-NEXT: lbu t3, 20(a0) -; RV64I-NEXT: slli t0, t0, 8 +; RV64I-NEXT: slli a6, a5, 32 +; RV64I-NEXT: or a4, a6, a4 +; RV64I-NEXT: or a7, a4, a7 +; RV64I-NEXT: lbu a4, 17(a0) +; RV64I-NEXT: lbu a6, 16(a0) +; RV64I-NEXT: lbu t2, 18(a0) +; RV64I-NEXT: lbu t3, 19(a0) +; RV64I-NEXT: slli a4, a4, 8 +; RV64I-NEXT: or a4, a4, a6 +; RV64I-NEXT: slli t2, t2, 16 +; RV64I-NEXT: slli t3, t3, 24 +; RV64I-NEXT: or a4, t2, a4 +; RV64I-NEXT: lbu a6, 21(a0) +; RV64I-NEXT: lbu t2, 20(a0) ; RV64I-NEXT: lbu t4, 22(a0) ; RV64I-NEXT: lbu a0, 23(a0) -; RV64I-NEXT: or t0, t0, t3 -; RV64I-NEXT: slli t2, t2, 24 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: or a6, a6, t2 ; RV64I-NEXT: slli t4, t4, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or t0, t4, t0 -; RV64I-NEXT: or a0, a0, t0 -; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: or a6, t4, a6 ; RV64I-NEXT: or a0, a0, a6 -; RV64I-NEXT: lbu a6, 1(a1) -; RV64I-NEXT: lbu t0, 0(a1) -; RV64I-NEXT: lbu t3, 2(a1) -; RV64I-NEXT: or t4, a0, t2 -; RV64I-NEXT: slli a6, a6, 8 -; RV64I-NEXT: or a0, a6, t0 -; RV64I-NEXT: slli t3, t3, 16 -; RV64I-NEXT: lbu a6, 5(a1) -; RV64I-NEXT: lbu t0, 4(a1) -; RV64I-NEXT: or t2, t3, a0 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: or a0, a0, a4 +; RV64I-NEXT: or t2, a0, t3 +; RV64I-NEXT: lbu a0, 1(a1) +; RV64I-NEXT: lbu a4, 0(a1) +; RV64I-NEXT: lbu a6, 2(a1) ; RV64I-NEXT: lbu t3, 3(a1) -; RV64I-NEXT: slli a6, a6, 8 -; RV64I-NEXT: or a6, a6, t0 -; RV64I-NEXT: lbu t0, 6(a1) -; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli a0, a4, 32 +; RV64I-NEXT: slli a0, a0, 8 +; RV64I-NEXT: or a0, a0, a4 +; RV64I-NEXT: slli a6, a6, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: slli t0, t0, 16 +; RV64I-NEXT: or a0, a6, a0 +; RV64I-NEXT: lbu a4, 5(a1) +; RV64I-NEXT: lbu a6, 4(a1) +; RV64I-NEXT: lbu t4, 6(a1) +; RV64I-NEXT: lbu a1, 7(a1) +; RV64I-NEXT: slli a4, a4, 8 +; RV64I-NEXT: or a4, a4, a6 +; RV64I-NEXT: slli t4, t4, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a4, t0, a6 +; RV64I-NEXT: or a4, t4, a4 ; RV64I-NEXT: or a1, a1, a4 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a1, a1, t2 -; RV64I-NEXT: or a4, a1, t3 -; RV64I-NEXT: srl a6, t4, a4 -; RV64I-NEXT: slli t0, a7, 1 -; RV64I-NEXT: addi t5, a4, -192 -; RV64I-NEXT: sra a1, a7, a4 -; RV64I-NEXT: bltz t5, .LBB11_2 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: or a6, a0, t3 +; RV64I-NEXT: srl a0, t2, a6 +; RV64I-NEXT: not t5, a6 +; RV64I-NEXT: slli a1, a7, 1 +; RV64I-NEXT: sll a1, a1, t5 +; RV64I-NEXT: or a1, a0, a1 +; RV64I-NEXT: addi t3, a6, -192 +; RV64I-NEXT: sra a4, a7, a6 +; RV64I-NEXT: mv t6, a1 +; RV64I-NEXT: bltz t3, .LBB11_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv s1, a1 -; RV64I-NEXT: j .LBB11_3 +; RV64I-NEXT: mv t6, a4 ; RV64I-NEXT: .LBB11_2: -; RV64I-NEXT: addiw t2, a4, -128 -; RV64I-NEXT: xori t2, t2, 63 -; RV64I-NEXT: sll t2, t0, t2 -; RV64I-NEXT: or s1, a6, t2 -; RV64I-NEXT: .LBB11_3: -; RV64I-NEXT: or a0, a0, t1 -; RV64I-NEXT: xori t3, a4, 63 -; RV64I-NEXT: addi t1, a4, -64 -; RV64I-NEXT: srl t6, a3, a4 -; RV64I-NEXT: bltz t1, .LBB11_5 -; RV64I-NEXT: # %bb.4: -; RV64I-NEXT: mv s4, t6 -; RV64I-NEXT: j .LBB11_6 -; RV64I-NEXT: .LBB11_5: -; RV64I-NEXT: srl t2, a0, a4 +; RV64I-NEXT: or a0, t1, t0 +; RV64I-NEXT: addi t0, a6, -64 +; RV64I-NEXT: srl t4, a3, a6 +; RV64I-NEXT: bltz t0, .LBB11_4 +; RV64I-NEXT: # %bb.3: +; RV64I-NEXT: mv s2, t4 +; RV64I-NEXT: j .LBB11_5 +; RV64I-NEXT: .LBB11_4: +; RV64I-NEXT: srl t1, a0, a6 ; RV64I-NEXT: slli s0, a3, 1 -; RV64I-NEXT: sll s0, s0, t3 -; RV64I-NEXT: or s4, t2, s0 -; RV64I-NEXT: .LBB11_6: -; RV64I-NEXT: negw s2, a4 -; RV64I-NEXT: sll s0, t4, s2 -; RV64I-NEXT: li s3, 64 -; RV64I-NEXT: li t2, 128 -; RV64I-NEXT: sub s3, s3, a4 -; RV64I-NEXT: bltu a4, t2, .LBB11_15 -; RV64I-NEXT: # %bb.7: -; RV64I-NEXT: bnez a4, .LBB11_16 +; RV64I-NEXT: sll t5, s0, t5 +; RV64I-NEXT: or s2, t1, t5 +; RV64I-NEXT: .LBB11_5: +; RV64I-NEXT: negw s0, a6 +; RV64I-NEXT: sll t5, t2, s0 +; RV64I-NEXT: li s1, 64 +; RV64I-NEXT: li t1, 128 +; RV64I-NEXT: sub s1, s1, a6 +; RV64I-NEXT: bltu a6, t1, .LBB11_18 +; RV64I-NEXT: # %bb.6: +; RV64I-NEXT: bnez a6, .LBB11_19 +; RV64I-NEXT: .LBB11_7: +; RV64I-NEXT: bgez s1, .LBB11_9 ; RV64I-NEXT: .LBB11_8: -; RV64I-NEXT: bgez s3, .LBB11_10 +; RV64I-NEXT: sll a7, a7, s0 +; RV64I-NEXT: srli t2, t2, 1 +; RV64I-NEXT: subw t5, t1, a6 +; RV64I-NEXT: not t5, t5 +; RV64I-NEXT: srl t2, t2, t5 +; RV64I-NEXT: or t5, a7, t2 ; RV64I-NEXT: .LBB11_9: -; RV64I-NEXT: sll a7, a7, s2 -; RV64I-NEXT: srli t4, t4, 1 -; RV64I-NEXT: subw s0, t2, a4 -; RV64I-NEXT: xori s0, s0, 63 -; RV64I-NEXT: srl t4, t4, s0 -; RV64I-NEXT: or s0, a7, t4 -; RV64I-NEXT: .LBB11_10: -; RV64I-NEXT: sraiw a7, a5, 31 -; RV64I-NEXT: mv a5, a1 -; RV64I-NEXT: bgez t5, .LBB11_17 -; RV64I-NEXT: # %bb.11: -; RV64I-NEXT: bltu a4, t2, .LBB11_18 +; RV64I-NEXT: sraiw a5, a5, 31 +; RV64I-NEXT: mv a7, a4 +; RV64I-NEXT: bgez t3, .LBB11_20 +; RV64I-NEXT: # %bb.10: +; RV64I-NEXT: bltu a6, t1, .LBB11_21 +; RV64I-NEXT: .LBB11_11: +; RV64I-NEXT: bnez a6, .LBB11_22 ; RV64I-NEXT: .LBB11_12: -; RV64I-NEXT: bnez a4, .LBB11_19 +; RV64I-NEXT: bgez t0, .LBB11_23 ; RV64I-NEXT: .LBB11_13: -; RV64I-NEXT: bltz t1, .LBB11_20 +; RV64I-NEXT: bgeu a6, t1, .LBB11_24 ; RV64I-NEXT: .LBB11_14: -; RV64I-NEXT: mv a5, a1 -; RV64I-NEXT: bgeu a4, t2, .LBB11_21 -; RV64I-NEXT: j .LBB11_22 +; RV64I-NEXT: bgez t0, .LBB11_25 ; RV64I-NEXT: .LBB11_15: -; RV64I-NEXT: slti s1, s3, 0 -; RV64I-NEXT: neg s1, s1 -; RV64I-NEXT: and s1, s1, s0 -; RV64I-NEXT: or s1, s4, s1 -; RV64I-NEXT: beqz a4, .LBB11_8 +; RV64I-NEXT: bltu a6, t1, .LBB11_17 ; RV64I-NEXT: .LBB11_16: -; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: bltz s3, .LBB11_9 -; RV64I-NEXT: j .LBB11_10 +; RV64I-NEXT: mv a4, a5 ; RV64I-NEXT: .LBB11_17: -; RV64I-NEXT: mv a5, a7 -; RV64I-NEXT: bgeu a4, t2, .LBB11_12 -; RV64I-NEXT: .LBB11_18: -; RV64I-NEXT: slti a5, t1, 0 -; RV64I-NEXT: neg a5, a5 -; RV64I-NEXT: and a5, a5, t6 -; RV64I-NEXT: or a5, a5, s0 -; RV64I-NEXT: beqz a4, .LBB11_13 -; RV64I-NEXT: .LBB11_19: -; RV64I-NEXT: mv a3, a5 -; RV64I-NEXT: bgez t1, .LBB11_14 -; RV64I-NEXT: .LBB11_20: -; RV64I-NEXT: sll a5, t0, t3 -; RV64I-NEXT: or a5, a6, a5 -; RV64I-NEXT: bltu a4, t2, .LBB11_22 -; RV64I-NEXT: .LBB11_21: -; RV64I-NEXT: mv a5, a7 -; RV64I-NEXT: .LBB11_22: -; RV64I-NEXT: bgez t1, .LBB11_26 -; RV64I-NEXT: # %bb.23: -; RV64I-NEXT: bltu a4, t2, .LBB11_25 -; RV64I-NEXT: .LBB11_24: -; RV64I-NEXT: mv a1, a7 -; RV64I-NEXT: .LBB11_25: -; RV64I-NEXT: sb a1, 24(a2) +; RV64I-NEXT: sb a4, 24(a2) +; RV64I-NEXT: srli a5, a4, 56 +; RV64I-NEXT: sb a5, 31(a2) +; RV64I-NEXT: srli a5, a4, 48 +; RV64I-NEXT: sb a5, 30(a2) +; RV64I-NEXT: srli a5, a4, 40 +; RV64I-NEXT: sb a5, 29(a2) +; RV64I-NEXT: srli a5, a4, 32 +; RV64I-NEXT: sb a5, 28(a2) +; RV64I-NEXT: srli a5, a4, 24 +; RV64I-NEXT: sb a5, 27(a2) +; RV64I-NEXT: srli a5, a4, 16 +; RV64I-NEXT: sb a5, 26(a2) +; RV64I-NEXT: srli a4, a4, 8 +; RV64I-NEXT: sb a4, 25(a2) +; RV64I-NEXT: sb a1, 16(a2) ; RV64I-NEXT: srli a4, a1, 56 -; RV64I-NEXT: sb a4, 31(a2) +; RV64I-NEXT: sb a4, 23(a2) ; RV64I-NEXT: srli a4, a1, 48 -; RV64I-NEXT: sb a4, 30(a2) +; RV64I-NEXT: sb a4, 22(a2) ; RV64I-NEXT: srli a4, a1, 40 -; RV64I-NEXT: sb a4, 29(a2) +; RV64I-NEXT: sb a4, 21(a2) ; RV64I-NEXT: srli a4, a1, 32 -; RV64I-NEXT: sb a4, 28(a2) +; RV64I-NEXT: sb a4, 20(a2) ; RV64I-NEXT: srli a4, a1, 24 -; RV64I-NEXT: sb a4, 27(a2) +; RV64I-NEXT: sb a4, 19(a2) ; RV64I-NEXT: srli a4, a1, 16 -; RV64I-NEXT: sb a4, 26(a2) +; RV64I-NEXT: sb a4, 18(a2) ; RV64I-NEXT: srli a1, a1, 8 -; RV64I-NEXT: sb a1, 25(a2) -; RV64I-NEXT: sb a5, 16(a2) -; RV64I-NEXT: srli a1, a5, 56 -; RV64I-NEXT: sb a1, 23(a2) -; RV64I-NEXT: srli a1, a5, 48 -; RV64I-NEXT: sb a1, 22(a2) -; RV64I-NEXT: srli a1, a5, 40 -; RV64I-NEXT: sb a1, 21(a2) -; RV64I-NEXT: srli a1, a5, 32 -; RV64I-NEXT: sb a1, 20(a2) -; RV64I-NEXT: srli a1, a5, 24 -; RV64I-NEXT: sb a1, 19(a2) -; RV64I-NEXT: srli a1, a5, 16 -; RV64I-NEXT: sb a1, 18(a2) -; RV64I-NEXT: srli a5, a5, 8 -; RV64I-NEXT: sb a5, 17(a2) +; RV64I-NEXT: sb a1, 17(a2) ; RV64I-NEXT: sb a0, 0(a2) ; RV64I-NEXT: srli a1, a0, 56 ; RV64I-NEXT: sb a1, 7(a2) @@ -3489,582 +3348,538 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: sb a0, 10(a2) ; RV64I-NEXT: srli a3, a3, 8 ; RV64I-NEXT: sb a3, 9(a2) -; RV64I-NEXT: ld s0, 40(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s1, 32(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s2, 24(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s3, 16(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s4, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 48 +; RV64I-NEXT: ld s0, 24(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s1, 16(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s2, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB11_26: -; RV64I-NEXT: mv a1, a7 -; RV64I-NEXT: bgeu a4, t2, .LBB11_24 -; RV64I-NEXT: j .LBB11_25 +; RV64I-NEXT: .LBB11_18: +; RV64I-NEXT: slti t6, s1, 0 +; RV64I-NEXT: neg t6, t6 +; RV64I-NEXT: and t6, t6, t5 +; RV64I-NEXT: or t6, s2, t6 +; RV64I-NEXT: beqz a6, .LBB11_7 +; RV64I-NEXT: .LBB11_19: +; RV64I-NEXT: mv a0, t6 +; RV64I-NEXT: bltz s1, .LBB11_8 +; RV64I-NEXT: j .LBB11_9 +; RV64I-NEXT: .LBB11_20: +; RV64I-NEXT: mv a7, a5 +; RV64I-NEXT: bgeu a6, t1, .LBB11_11 +; RV64I-NEXT: .LBB11_21: +; RV64I-NEXT: slti a7, t0, 0 +; RV64I-NEXT: neg a7, a7 +; RV64I-NEXT: and a7, a7, t4 +; RV64I-NEXT: or a7, a7, t5 +; RV64I-NEXT: beqz a6, .LBB11_12 +; RV64I-NEXT: .LBB11_22: +; RV64I-NEXT: mv a3, a7 +; RV64I-NEXT: bltz t0, .LBB11_13 +; RV64I-NEXT: .LBB11_23: +; RV64I-NEXT: mv a1, a4 +; RV64I-NEXT: bltu a6, t1, .LBB11_14 +; RV64I-NEXT: .LBB11_24: +; RV64I-NEXT: mv a1, a5 +; RV64I-NEXT: bltz t0, .LBB11_15 +; RV64I-NEXT: .LBB11_25: +; RV64I-NEXT: mv a4, a5 +; RV64I-NEXT: bgeu a6, t1, .LBB11_16 +; RV64I-NEXT: j .LBB11_17 ; ; RV32I-LABEL: ashr_32bytes: ; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -144 -; RV32I-NEXT: sw ra, 140(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 136(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 132(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 128(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 124(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s4, 120(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s5, 116(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s6, 112(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s7, 108(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s8, 104(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s9, 100(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s10, 96(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s11, 92(sp) # 4-byte Folded Spill -; RV32I-NEXT: lbu a5, 4(a0) -; RV32I-NEXT: lbu a7, 5(a0) -; RV32I-NEXT: lbu t1, 6(a0) -; RV32I-NEXT: lbu t5, 7(a0) +; RV32I-NEXT: addi sp, sp, -128 +; RV32I-NEXT: sw ra, 124(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 120(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 116(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 112(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s3, 108(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s4, 104(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s5, 100(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s6, 96(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s7, 92(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s8, 88(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s9, 84(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s10, 80(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s11, 76(sp) # 4-byte Folded Spill +; RV32I-NEXT: lbu a6, 4(a0) +; RV32I-NEXT: lbu t1, 5(a0) +; RV32I-NEXT: lbu t5, 6(a0) +; RV32I-NEXT: lbu t6, 7(a0) ; RV32I-NEXT: lbu a3, 0(a0) -; RV32I-NEXT: sw a3, 64(sp) # 4-byte Folded Spill -; RV32I-NEXT: lbu t2, 1(a0) -; RV32I-NEXT: lbu t3, 2(a0) -; RV32I-NEXT: lbu t4, 3(a0) -; RV32I-NEXT: lbu t6, 12(a0) -; RV32I-NEXT: lbu s2, 13(a0) +; RV32I-NEXT: sw a3, 72(sp) # 4-byte Folded Spill +; RV32I-NEXT: lbu a5, 1(a0) +; RV32I-NEXT: lbu t2, 2(a0) +; RV32I-NEXT: lbu t3, 3(a0) +; RV32I-NEXT: lbu s0, 12(a0) +; RV32I-NEXT: lbu a4, 13(a0) ; RV32I-NEXT: lbu s3, 14(a0) ; RV32I-NEXT: lbu s4, 15(a0) -; RV32I-NEXT: lbu s0, 8(a0) -; RV32I-NEXT: lbu s5, 9(a0) -; RV32I-NEXT: lbu s6, 10(a0) -; RV32I-NEXT: lbu s7, 11(a0) +; RV32I-NEXT: lbu s2, 8(a0) +; RV32I-NEXT: lbu s1, 9(a0) +; RV32I-NEXT: lbu s7, 10(a0) +; RV32I-NEXT: lbu s8, 11(a0) ; RV32I-NEXT: lbu a3, 21(a0) -; RV32I-NEXT: lbu a4, 20(a0) -; RV32I-NEXT: lbu t0, 22(a0) -; RV32I-NEXT: lbu s1, 23(a0) +; RV32I-NEXT: lbu t0, 20(a0) +; RV32I-NEXT: lbu t4, 22(a0) +; RV32I-NEXT: lbu s5, 23(a0) ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a3, a4 -; RV32I-NEXT: slli t0, t0, 16 -; RV32I-NEXT: slli s1, s1, 24 -; RV32I-NEXT: or a3, t0, a3 -; RV32I-NEXT: or a3, s1, a3 -; RV32I-NEXT: lbu a4, 17(a0) -; RV32I-NEXT: lbu t0, 16(a0) -; RV32I-NEXT: lbu s1, 18(a0) -; RV32I-NEXT: lbu s8, 19(a0) -; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a4, a4, t0 -; RV32I-NEXT: slli s1, s1, 16 -; RV32I-NEXT: slli s8, s8, 24 -; RV32I-NEXT: or a4, s1, a4 -; RV32I-NEXT: or t0, s8, a4 -; RV32I-NEXT: lbu a4, 29(a0) -; RV32I-NEXT: lbu s1, 28(a0) -; RV32I-NEXT: lbu s8, 30(a0) +; RV32I-NEXT: or a3, a3, t0 +; RV32I-NEXT: slli t4, t4, 16 +; RV32I-NEXT: slli s5, s5, 24 +; RV32I-NEXT: or a3, t4, a3 +; RV32I-NEXT: or a3, s5, a3 +; RV32I-NEXT: lbu t0, 17(a0) +; RV32I-NEXT: lbu t4, 16(a0) +; RV32I-NEXT: lbu s5, 18(a0) +; RV32I-NEXT: lbu s6, 19(a0) +; RV32I-NEXT: slli t0, t0, 8 +; RV32I-NEXT: or t0, t0, t4 +; RV32I-NEXT: slli s5, s5, 16 +; RV32I-NEXT: slli s6, s6, 24 +; RV32I-NEXT: or t0, s5, t0 +; RV32I-NEXT: or t4, s6, t0 +; RV32I-NEXT: lbu t0, 29(a0) +; RV32I-NEXT: lbu s5, 28(a0) +; RV32I-NEXT: lbu s6, 30(a0) ; RV32I-NEXT: lbu s9, 31(a0) -; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a4, a4, s1 -; RV32I-NEXT: slli s8, s8, 16 +; RV32I-NEXT: slli t0, t0, 8 +; RV32I-NEXT: or t0, t0, s5 +; RV32I-NEXT: slli s6, s6, 16 ; RV32I-NEXT: slli s9, s9, 24 -; RV32I-NEXT: or a4, s8, a4 -; RV32I-NEXT: sw s9, 36(sp) # 4-byte Folded Spill -; RV32I-NEXT: or s10, s9, a4 -; RV32I-NEXT: lbu a4, 25(a0) -; RV32I-NEXT: lbu s1, 24(a0) -; RV32I-NEXT: lbu s8, 26(a0) +; RV32I-NEXT: or t0, s6, t0 +; RV32I-NEXT: sw s9, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: or s10, s9, t0 +; RV32I-NEXT: lbu t0, 25(a0) +; RV32I-NEXT: lbu s5, 24(a0) +; RV32I-NEXT: lbu s6, 26(a0) ; RV32I-NEXT: lbu a0, 27(a0) -; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a4, a4, s1 -; RV32I-NEXT: slli s8, s8, 16 +; RV32I-NEXT: slli t0, t0, 8 +; RV32I-NEXT: or t0, t0, s5 +; RV32I-NEXT: slli s6, s6, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a4, s8, a4 -; RV32I-NEXT: or s9, a0, a4 +; RV32I-NEXT: or t0, s6, t0 +; RV32I-NEXT: or s9, a0, t0 ; RV32I-NEXT: lbu a0, 1(a1) -; RV32I-NEXT: lbu a4, 0(a1) -; RV32I-NEXT: lbu s1, 2(a1) +; RV32I-NEXT: lbu t0, 0(a1) +; RV32I-NEXT: lbu s5, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a0, a0, 8 -; RV32I-NEXT: or a0, a0, a4 -; RV32I-NEXT: slli s1, s1, 16 +; RV32I-NEXT: or a0, a0, t0 +; RV32I-NEXT: slli s5, s5, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a0, s1, a0 +; RV32I-NEXT: or a0, s5, a0 ; RV32I-NEXT: or a1, a1, a0 -; RV32I-NEXT: srl a4, s9, a1 -; RV32I-NEXT: slli s8, s10, 1 +; RV32I-NEXT: srl a0, s9, a1 +; RV32I-NEXT: not s5, a1 +; RV32I-NEXT: slli t0, s10, 1 +; RV32I-NEXT: sll t0, t0, s5 +; RV32I-NEXT: or t0, a0, t0 ; RV32I-NEXT: addi a0, a1, -224 -; RV32I-NEXT: sw s10, 84(sp) # 4-byte Folded Spill -; RV32I-NEXT: sra s1, s10, a1 -; RV32I-NEXT: sw a0, 44(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a4, 80(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s8, 76(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s10, 60(sp) # 4-byte Folded Spill +; RV32I-NEXT: sra s6, s10, a1 +; RV32I-NEXT: mv s10, t0 +; RV32I-NEXT: sw a0, 32(sp) # 4-byte Folded Spill ; RV32I-NEXT: bltz a0, .LBB11_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: mv a4, s1 -; RV32I-NEXT: j .LBB11_3 +; RV32I-NEXT: mv s10, s6 ; RV32I-NEXT: .LBB11_2: -; RV32I-NEXT: addi a0, a1, -192 -; RV32I-NEXT: xori a0, a0, 31 -; RV32I-NEXT: sll a0, s8, a0 -; RV32I-NEXT: or a4, a4, a0 -; RV32I-NEXT: .LBB11_3: -; RV32I-NEXT: slli s8, s2, 8 -; RV32I-NEXT: slli s10, s3, 16 +; RV32I-NEXT: slli ra, a4, 8 +; RV32I-NEXT: slli s3, s3, 16 ; RV32I-NEXT: slli s4, s4, 24 -; RV32I-NEXT: slli s11, s5, 8 -; RV32I-NEXT: slli s6, s6, 16 -; RV32I-NEXT: slli ra, s7, 24 -; RV32I-NEXT: srl s2, t0, a1 +; RV32I-NEXT: slli s1, s1, 8 +; RV32I-NEXT: slli s7, s7, 16 +; RV32I-NEXT: slli s8, s8, 24 +; RV32I-NEXT: srl a4, t4, a1 ; RV32I-NEXT: slli a0, a3, 1 -; RV32I-NEXT: addi s5, a1, -128 -; RV32I-NEXT: xori a6, s5, 31 -; RV32I-NEXT: addi s3, a1, -160 -; RV32I-NEXT: srl s7, a3, a1 -; RV32I-NEXT: sw s3, 88(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s7, 72(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 28(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a0, 52(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a6, 32(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgez s3, .LBB11_5 -; RV32I-NEXT: # %bb.4: -; RV32I-NEXT: sll a0, a0, a6 -; RV32I-NEXT: or s7, s2, a0 -; RV32I-NEXT: .LBB11_5: -; RV32I-NEXT: slli s2, a7, 8 -; RV32I-NEXT: slli s3, t1, 16 -; RV32I-NEXT: slli t5, t5, 24 -; RV32I-NEXT: or t6, s8, t6 -; RV32I-NEXT: or s4, s4, s10 -; RV32I-NEXT: or s0, s11, s0 -; RV32I-NEXT: or s6, ra, s6 -; RV32I-NEXT: neg a7, a1 -; RV32I-NEXT: sll s8, s9, a7 -; RV32I-NEXT: li a0, 160 +; RV32I-NEXT: sll s11, a0, s5 +; RV32I-NEXT: or s11, a4, s11 +; RV32I-NEXT: addi a7, a1, -160 +; RV32I-NEXT: srl a4, a3, a1 +; RV32I-NEXT: sw a4, 64(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s11, 40(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a7, 68(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz a7, .LBB11_4 +; RV32I-NEXT: # %bb.3: +; RV32I-NEXT: lw s11, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: .LBB11_4: +; RV32I-NEXT: slli a4, t1, 8 +; RV32I-NEXT: slli t5, t5, 16 +; RV32I-NEXT: slli t6, t6, 24 +; RV32I-NEXT: or s0, ra, s0 +; RV32I-NEXT: or s3, s4, s3 +; RV32I-NEXT: or s1, s1, s2 +; RV32I-NEXT: or s8, s8, s7 +; RV32I-NEXT: neg ra, a1 +; RV32I-NEXT: sll s7, s9, ra +; RV32I-NEXT: li s2, 160 +; RV32I-NEXT: addi s4, a1, -128 ; RV32I-NEXT: li t1, 64 -; RV32I-NEXT: sub a0, a0, a1 -; RV32I-NEXT: sw s8, 68(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a0, 40(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgeu s5, t1, .LBB11_7 -; RV32I-NEXT: # %bb.6: -; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: and a0, a0, s8 -; RV32I-NEXT: or a4, s7, a0 -; RV32I-NEXT: .LBB11_7: -; RV32I-NEXT: slli t2, t2, 8 -; RV32I-NEXT: slli t3, t3, 16 -; RV32I-NEXT: slli t4, t4, 24 -; RV32I-NEXT: or a0, s2, a5 -; RV32I-NEXT: or t5, t5, s3 -; RV32I-NEXT: or a5, s4, t6 -; RV32I-NEXT: or s7, s6, s0 -; RV32I-NEXT: mv s0, t0 -; RV32I-NEXT: beqz s5, .LBB11_9 -; RV32I-NEXT: # %bb.8: -; RV32I-NEXT: mv s0, a4 -; RV32I-NEXT: .LBB11_9: -; RV32I-NEXT: lw a4, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a4, t2, a4 -; RV32I-NEXT: or t2, t4, t3 -; RV32I-NEXT: or s4, t5, a0 -; RV32I-NEXT: srl ra, s7, a1 -; RV32I-NEXT: slli s11, a5, 1 -; RV32I-NEXT: addi a0, a1, -64 -; RV32I-NEXT: xori a6, a0, 31 -; RV32I-NEXT: addi a0, a1, -96 -; RV32I-NEXT: srl t3, a5, a1 -; RV32I-NEXT: sw a0, 60(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a6, 24(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw t3, 56(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz a0, .LBB11_11 -; RV32I-NEXT: # %bb.10: -; RV32I-NEXT: mv a6, t3 -; RV32I-NEXT: j .LBB11_12 -; RV32I-NEXT: .LBB11_11: -; RV32I-NEXT: sll a0, s11, a6 -; RV32I-NEXT: or a6, ra, a0 +; RV32I-NEXT: sub a7, s2, a1 +; RV32I-NEXT: sw s7, 52(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgeu s4, t1, .LBB11_6 +; RV32I-NEXT: # %bb.5: +; RV32I-NEXT: slti s2, a7, 0 +; RV32I-NEXT: neg s2, s2 +; RV32I-NEXT: and s2, s2, s7 +; RV32I-NEXT: or s10, s11, s2 +; RV32I-NEXT: .LBB11_6: +; RV32I-NEXT: sw a7, 28(sp) # 4-byte Folded Spill +; RV32I-NEXT: slli a5, a5, 8 +; RV32I-NEXT: slli t2, t2, 16 +; RV32I-NEXT: slli t3, t3, 24 +; RV32I-NEXT: or s2, a4, a6 +; RV32I-NEXT: or t5, t6, t5 +; RV32I-NEXT: or a6, s3, s0 +; RV32I-NEXT: or s8, s8, s1 +; RV32I-NEXT: mv a4, t4 +; RV32I-NEXT: beqz s4, .LBB11_8 +; RV32I-NEXT: # %bb.7: +; RV32I-NEXT: mv a4, s10 +; RV32I-NEXT: .LBB11_8: +; RV32I-NEXT: lw a7, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: or a5, a5, a7 +; RV32I-NEXT: or t3, t3, t2 +; RV32I-NEXT: or t1, t5, s2 +; RV32I-NEXT: srl t2, s8, a1 +; RV32I-NEXT: slli t5, a6, 1 +; RV32I-NEXT: sll t5, t5, s5 +; RV32I-NEXT: or t6, t2, t5 +; RV32I-NEXT: addi s0, a1, -96 +; RV32I-NEXT: srl t2, a6, a1 +; RV32I-NEXT: sw t2, 56(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv t2, t6 +; RV32I-NEXT: li a7, 64 +; RV32I-NEXT: bltz s0, .LBB11_10 +; RV32I-NEXT: # %bb.9: +; RV32I-NEXT: lw t2, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: .LBB11_10: +; RV32I-NEXT: or s3, t3, a5 +; RV32I-NEXT: addi t5, a1, -32 +; RV32I-NEXT: srl a5, t1, a1 +; RV32I-NEXT: sw s0, 48(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a5, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgez t5, .LBB11_12 +; RV32I-NEXT: # %bb.11: +; RV32I-NEXT: srl a5, s3, a1 +; RV32I-NEXT: slli t3, t1, 1 +; RV32I-NEXT: sll t3, t3, s5 +; RV32I-NEXT: or a5, a5, t3 ; RV32I-NEXT: .LBB11_12: -; RV32I-NEXT: or t2, t2, a4 -; RV32I-NEXT: xori t5, a1, 31 -; RV32I-NEXT: addi t6, a1, -32 -; RV32I-NEXT: srl t4, s4, a1 -; RV32I-NEXT: bltz t6, .LBB11_14 +; RV32I-NEXT: sll s10, s8, ra +; RV32I-NEXT: li t3, 32 +; RV32I-NEXT: sub s0, t3, a1 +; RV32I-NEXT: sw s0, 72(sp) # 4-byte Folded Spill +; RV32I-NEXT: slti s0, s0, 0 +; RV32I-NEXT: neg s0, s0 +; RV32I-NEXT: bgeu a1, a7, .LBB11_14 ; RV32I-NEXT: # %bb.13: -; RV32I-NEXT: mv a0, t4 -; RV32I-NEXT: j .LBB11_15 +; RV32I-NEXT: and t2, s0, s10 +; RV32I-NEXT: or t2, a5, t2 ; RV32I-NEXT: .LBB11_14: -; RV32I-NEXT: srl a0, t2, a1 -; RV32I-NEXT: slli a4, s4, 1 -; RV32I-NEXT: sll a4, a4, t5 -; RV32I-NEXT: or a0, a0, a4 -; RV32I-NEXT: .LBB11_15: -; RV32I-NEXT: sll s10, s7, a7 -; RV32I-NEXT: li a4, 32 -; RV32I-NEXT: sub s8, a4, a1 -; RV32I-NEXT: slti t3, s8, 0 -; RV32I-NEXT: neg t3, t3 -; RV32I-NEXT: bgeu a1, t1, .LBB11_17 -; RV32I-NEXT: # %bb.16: -; RV32I-NEXT: and a6, t3, s10 -; RV32I-NEXT: or a6, a0, a6 -; RV32I-NEXT: .LBB11_17: -; RV32I-NEXT: sw t3, 48(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw t5, 64(sp) # 4-byte Folded Spill -; RV32I-NEXT: mv t5, t2 -; RV32I-NEXT: beqz a1, .LBB11_19 -; RV32I-NEXT: # %bb.18: -; RV32I-NEXT: mv t5, a6 -; RV32I-NEXT: .LBB11_19: -; RV32I-NEXT: sll s6, t0, a7 -; RV32I-NEXT: li a0, 96 -; RV32I-NEXT: sub s2, a0, a1 -; RV32I-NEXT: slti a0, s2, 0 -; RV32I-NEXT: neg a6, a0 -; RV32I-NEXT: li s3, 128 -; RV32I-NEXT: sub t3, s3, a1 -; RV32I-NEXT: sltiu a0, t3, 64 -; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgeu a1, s3, .LBB11_21 -; RV32I-NEXT: # %bb.20: -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: and a0, a6, s6 -; RV32I-NEXT: and a0, s0, a0 -; RV32I-NEXT: or s0, t5, a0 -; RV32I-NEXT: .LBB11_21: -; RV32I-NEXT: beqz a1, .LBB11_23 -; RV32I-NEXT: # %bb.22: -; RV32I-NEXT: mv t2, s0 -; RV32I-NEXT: .LBB11_23: -; RV32I-NEXT: neg a0, t3 -; RV32I-NEXT: sub t5, a4, t3 -; RV32I-NEXT: srl a4, a3, a0 -; RV32I-NEXT: sw t5, 16(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw a4, 20(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz t5, .LBB11_25 -; RV32I-NEXT: # %bb.24: -; RV32I-NEXT: mv a0, a4 +; RV32I-NEXT: sw a6, 44(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 36(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv s2, s3 +; RV32I-NEXT: beqz a1, .LBB11_16 +; RV32I-NEXT: # %bb.15: +; RV32I-NEXT: mv s2, t2 +; RV32I-NEXT: .LBB11_16: +; RV32I-NEXT: sll a6, t4, ra +; RV32I-NEXT: li a5, 96 +; RV32I-NEXT: sub s7, a5, a1 +; RV32I-NEXT: slti a5, s7, 0 +; RV32I-NEXT: neg s11, a5 +; RV32I-NEXT: li t2, 128 +; RV32I-NEXT: sub s0, t2, a1 +; RV32I-NEXT: sltiu a5, s0, 64 +; RV32I-NEXT: neg a5, a5 +; RV32I-NEXT: bgeu a1, t2, .LBB11_18 +; RV32I-NEXT: # %bb.17: +; RV32I-NEXT: and a4, s11, a6 +; RV32I-NEXT: and a4, a5, a4 +; RV32I-NEXT: or a4, s2, a4 +; RV32I-NEXT: .LBB11_18: +; RV32I-NEXT: lw s2, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a5, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: beqz a1, .LBB11_20 +; RV32I-NEXT: # %bb.19: +; RV32I-NEXT: mv s3, a4 +; RV32I-NEXT: .LBB11_20: +; RV32I-NEXT: neg a4, s0 +; RV32I-NEXT: sub a5, t3, s0 +; RV32I-NEXT: srl t3, a3, a4 +; RV32I-NEXT: sw a5, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz a5, .LBB11_23 +; RV32I-NEXT: # %bb.21: +; RV32I-NEXT: mv a0, t3 +; RV32I-NEXT: bgeu s0, a7, .LBB11_24 +; RV32I-NEXT: .LBB11_22: +; RV32I-NEXT: and a4, s11, s2 +; RV32I-NEXT: or a0, a4, a0 +; RV32I-NEXT: mv a4, s9 +; RV32I-NEXT: bnez s0, .LBB11_25 ; RV32I-NEXT: j .LBB11_26 +; RV32I-NEXT: .LBB11_23: +; RV32I-NEXT: srl a4, t4, a4 +; RV32I-NEXT: sub a5, a7, s0 +; RV32I-NEXT: not a5, a5 +; RV32I-NEXT: sll a0, a0, a5 +; RV32I-NEXT: or a0, a4, a0 +; RV32I-NEXT: bltu s0, a7, .LBB11_22 +; RV32I-NEXT: .LBB11_24: +; RV32I-NEXT: lw a0, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a0, a0, a6 +; RV32I-NEXT: mv a4, s9 +; RV32I-NEXT: beqz s0, .LBB11_26 ; RV32I-NEXT: .LBB11_25: -; RV32I-NEXT: srl a0, t0, a0 -; RV32I-NEXT: sub a4, t1, t3 -; RV32I-NEXT: xori a4, a4, 31 -; RV32I-NEXT: lw t5, 52(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a4, t5, a4 -; RV32I-NEXT: or a0, a0, a4 +; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: .LBB11_26: -; RV32I-NEXT: lw s0, 68(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw t5, 32(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltu t3, t1, .LBB11_28 +; RV32I-NEXT: sw t3, 20(sp) # 4-byte Folded Spill +; RV32I-NEXT: bltz t5, .LBB11_28 ; RV32I-NEXT: # %bb.27: -; RV32I-NEXT: lw a0, 48(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a0, s6 -; RV32I-NEXT: mv a4, s9 -; RV32I-NEXT: bnez t3, .LBB11_29 -; RV32I-NEXT: j .LBB11_30 +; RV32I-NEXT: lw t6, 56(sp) # 4-byte Folded Reload ; RV32I-NEXT: .LBB11_28: -; RV32I-NEXT: and a4, a6, s0 -; RV32I-NEXT: or a0, a4, a0 -; RV32I-NEXT: mv a4, s9 -; RV32I-NEXT: beqz t3, .LBB11_30 -; RV32I-NEXT: .LBB11_29: -; RV32I-NEXT: mv a4, a0 +; RV32I-NEXT: mv t3, t0 +; RV32I-NEXT: lw a0, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a0, .LBB11_30 +; RV32I-NEXT: # %bb.29: +; RV32I-NEXT: mv t3, s6 ; RV32I-NEXT: .LBB11_30: -; RV32I-NEXT: bltz t6, .LBB11_33 +; RV32I-NEXT: sltiu a5, a1, 64 +; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: srai a0, a0, 31 +; RV32I-NEXT: bltu s4, a7, .LBB11_32 ; RV32I-NEXT: # %bb.31: -; RV32I-NEXT: lw a6, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgez a0, .LBB11_34 +; RV32I-NEXT: mv t3, a0 ; RV32I-NEXT: .LBB11_32: -; RV32I-NEXT: lw a0, 76(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a0, a0, t5 -; RV32I-NEXT: lw t5, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: or t5, t5, a0 -; RV32I-NEXT: j .LBB11_35 -; RV32I-NEXT: .LBB11_33: -; RV32I-NEXT: lw a0, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a0, s11, a0 -; RV32I-NEXT: or a6, ra, a0 -; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz a0, .LBB11_32 +; RV32I-NEXT: neg s1, a5 +; RV32I-NEXT: li a5, 128 +; RV32I-NEXT: bgeu a1, a5, .LBB11_34 +; RV32I-NEXT: # %bb.33: +; RV32I-NEXT: and a5, s1, t6 +; RV32I-NEXT: or t3, a5, a4 ; RV32I-NEXT: .LBB11_34: -; RV32I-NEXT: mv t5, s1 -; RV32I-NEXT: .LBB11_35: -; RV32I-NEXT: sltiu a0, a1, 64 -; RV32I-NEXT: lw s11, 36(sp) # 4-byte Folded Reload -; RV32I-NEXT: srai s11, s11, 31 -; RV32I-NEXT: bltu s5, t1, .LBB11_37 -; RV32I-NEXT: # %bb.36: -; RV32I-NEXT: mv t5, s11 -; RV32I-NEXT: .LBB11_37: -; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: bgeu a1, s3, .LBB11_39 -; RV32I-NEXT: # %bb.38: -; RV32I-NEXT: and a0, a0, a6 -; RV32I-NEXT: or t5, a0, a4 -; RV32I-NEXT: .LBB11_39: -; RV32I-NEXT: mv ra, s7 -; RV32I-NEXT: beqz a1, .LBB11_41 -; RV32I-NEXT: # %bb.40: -; RV32I-NEXT: mv ra, t5 +; RV32I-NEXT: mv a4, s8 +; RV32I-NEXT: beqz a1, .LBB11_36 +; RV32I-NEXT: # %bb.35: +; RV32I-NEXT: mv a4, t3 +; RV32I-NEXT: .LBB11_36: +; RV32I-NEXT: sw a4, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: sub a4, a7, a1 +; RV32I-NEXT: not t3, a4 +; RV32I-NEXT: lw a4, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgez a4, .LBB11_38 +; RV32I-NEXT: # %bb.37: +; RV32I-NEXT: lw a4, 44(sp) # 4-byte Folded Reload +; RV32I-NEXT: sll a4, a4, ra +; RV32I-NEXT: srli a5, s8, 1 +; RV32I-NEXT: srl a5, a5, t3 +; RV32I-NEXT: or s10, a4, a5 +; RV32I-NEXT: .LBB11_38: +; RV32I-NEXT: slti a4, t5, 0 +; RV32I-NEXT: neg s5, a4 +; RV32I-NEXT: li t2, 64 +; RV32I-NEXT: bltu a1, a7, .LBB11_40 +; RV32I-NEXT: # %bb.39: +; RV32I-NEXT: lw a4, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: slti a4, a4, 0 +; RV32I-NEXT: neg a4, a4 +; RV32I-NEXT: lw a5, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a4, a4, a5 +; RV32I-NEXT: j .LBB11_41 +; RV32I-NEXT: .LBB11_40: +; RV32I-NEXT: lw a4, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a4, s5, a4 +; RV32I-NEXT: or a4, a4, s10 ; RV32I-NEXT: .LBB11_41: -; RV32I-NEXT: sub a0, t1, a1 -; RV32I-NEXT: xori s3, a0, 31 -; RV32I-NEXT: bgez s8, .LBB11_43 +; RV32I-NEXT: sw t0, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv a7, t1 +; RV32I-NEXT: beqz a1, .LBB11_43 ; RV32I-NEXT: # %bb.42: -; RV32I-NEXT: sll a0, a5, a7 -; RV32I-NEXT: srli a4, s7, 1 -; RV32I-NEXT: srl a4, a4, s3 -; RV32I-NEXT: or s10, a0, a4 +; RV32I-NEXT: mv a7, a4 ; RV32I-NEXT: .LBB11_43: -; RV32I-NEXT: slti a0, t6, 0 -; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: sw a0, 36(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltu a1, t1, .LBB11_45 +; RV32I-NEXT: mv s10, t3 +; RV32I-NEXT: sll a4, a3, ra +; RV32I-NEXT: srli s8, t4, 1 +; RV32I-NEXT: not t3, s0 +; RV32I-NEXT: mv t0, s7 +; RV32I-NEXT: bltz s7, .LBB11_45 ; RV32I-NEXT: # %bb.44: -; RV32I-NEXT: lw a0, 60(sp) # 4-byte Folded Reload -; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: lw a4, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a0, a4 -; RV32I-NEXT: mv a6, s4 -; RV32I-NEXT: bnez a1, .LBB11_46 -; RV32I-NEXT: j .LBB11_47 +; RV32I-NEXT: mv s7, t5 +; RV32I-NEXT: mv s11, a6 +; RV32I-NEXT: j .LBB11_46 ; RV32I-NEXT: .LBB11_45: -; RV32I-NEXT: and a0, a0, t4 -; RV32I-NEXT: or a0, a0, s10 -; RV32I-NEXT: mv a6, s4 -; RV32I-NEXT: beqz a1, .LBB11_47 +; RV32I-NEXT: mv s7, t5 +; RV32I-NEXT: srl a5, s8, t3 +; RV32I-NEXT: or s11, a4, a5 ; RV32I-NEXT: .LBB11_46: -; RV32I-NEXT: mv a6, a0 -; RV32I-NEXT: .LBB11_47: -; RV32I-NEXT: sll s10, a3, a7 -; RV32I-NEXT: srli a4, t0, 1 -; RV32I-NEXT: xori t4, t3, 31 -; RV32I-NEXT: bltz s2, .LBB11_49 -; RV32I-NEXT: # %bb.48: -; RV32I-NEXT: mv t5, s6 -; RV32I-NEXT: j .LBB11_50 +; RV32I-NEXT: mv t5, t1 +; RV32I-NEXT: mv t6, s3 +; RV32I-NEXT: lw a5, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: sll s3, a5, ra +; RV32I-NEXT: srli s9, s9, 1 +; RV32I-NEXT: lw a5, 28(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a5, .LBB11_48 +; RV32I-NEXT: # %bb.47: +; RV32I-NEXT: mv t1, s9 +; RV32I-NEXT: mv s9, s3 +; RV32I-NEXT: mv s3, s2 +; RV32I-NEXT: j .LBB11_49 +; RV32I-NEXT: .LBB11_48: +; RV32I-NEXT: li a5, 192 +; RV32I-NEXT: sub a5, a5, a1 +; RV32I-NEXT: not a5, a5 +; RV32I-NEXT: mv t1, s9 +; RV32I-NEXT: srl a5, s9, a5 +; RV32I-NEXT: mv s9, s3 +; RV32I-NEXT: or s3, s3, a5 ; RV32I-NEXT: .LBB11_49: -; RV32I-NEXT: srl a0, a4, t4 -; RV32I-NEXT: or t5, s10, a0 -; RV32I-NEXT: .LBB11_50: -; RV32I-NEXT: lw a0, 84(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a7, a0, a7 -; RV32I-NEXT: srli s7, s9, 1 -; RV32I-NEXT: lw a0, 40(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw s3, 32(sp) # 4-byte Folded Spill -; RV32I-NEXT: bltz a0, .LBB11_52 -; RV32I-NEXT: # %bb.51: -; RV32I-NEXT: mv s9, s0 -; RV32I-NEXT: j .LBB11_53 -; RV32I-NEXT: .LBB11_52: -; RV32I-NEXT: li a0, 192 -; RV32I-NEXT: sub a0, a0, a1 -; RV32I-NEXT: xori a0, a0, 31 -; RV32I-NEXT: srl a0, s7, a0 -; RV32I-NEXT: or s9, a7, a0 +; RV32I-NEXT: mv a5, s6 +; RV32I-NEXT: lw ra, 32(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz ra, .LBB11_51 +; RV32I-NEXT: # %bb.50: +; RV32I-NEXT: mv a5, a0 +; RV32I-NEXT: .LBB11_51: +; RV32I-NEXT: bltu s4, t2, .LBB11_53 +; RV32I-NEXT: # %bb.52: +; RV32I-NEXT: mv t2, s2 +; RV32I-NEXT: j .LBB11_54 ; RV32I-NEXT: .LBB11_53: -; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: lw s3, 44(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz s3, .LBB11_55 -; RV32I-NEXT: # %bb.54: -; RV32I-NEXT: mv a0, s11 -; RV32I-NEXT: .LBB11_55: -; RV32I-NEXT: bgeu s5, t1, .LBB11_57 -; RV32I-NEXT: # %bb.56: -; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: lw s0, 72(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a0, s0 -; RV32I-NEXT: lw s0, 68(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a0, a0, s9 -; RV32I-NEXT: .LBB11_57: -; RV32I-NEXT: li s3, 128 -; RV32I-NEXT: mv s9, a3 -; RV32I-NEXT: bnez s5, .LBB11_64 -; RV32I-NEXT: # %bb.58: -; RV32I-NEXT: bltu a1, s3, .LBB11_65 +; RV32I-NEXT: lw a5, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: slti a5, a5, 0 +; RV32I-NEXT: neg a5, a5 +; RV32I-NEXT: lw t2, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a5, a5, t2 +; RV32I-NEXT: lw t2, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: or a5, a5, s3 +; RV32I-NEXT: .LBB11_54: +; RV32I-NEXT: mv s2, s1 +; RV32I-NEXT: mv ra, s9 +; RV32I-NEXT: mv s3, a3 +; RV32I-NEXT: mv s9, t1 +; RV32I-NEXT: beqz s4, .LBB11_56 +; RV32I-NEXT: # %bb.55: +; RV32I-NEXT: mv s3, a5 +; RV32I-NEXT: .LBB11_56: +; RV32I-NEXT: li a5, 128 +; RV32I-NEXT: mv t1, t5 +; RV32I-NEXT: bltu a1, a5, .LBB11_61 +; RV32I-NEXT: # %bb.57: +; RV32I-NEXT: li a7, 64 +; RV32I-NEXT: bnez a1, .LBB11_62 +; RV32I-NEXT: .LBB11_58: +; RV32I-NEXT: lw a5, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a5, .LBB11_63 ; RV32I-NEXT: .LBB11_59: -; RV32I-NEXT: bnez a1, .LBB11_66 +; RV32I-NEXT: bltz t0, .LBB11_64 ; RV32I-NEXT: .LBB11_60: -; RV32I-NEXT: bgez s8, .LBB11_62 +; RV32I-NEXT: mv a4, t2 +; RV32I-NEXT: j .LBB11_65 ; RV32I-NEXT: .LBB11_61: -; RV32I-NEXT: lw a0, 32(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl a0, a4, a0 -; RV32I-NEXT: or s6, s10, a0 +; RV32I-NEXT: lw a5, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a5, a5, s11 +; RV32I-NEXT: or s3, a7, a5 +; RV32I-NEXT: li a7, 64 +; RV32I-NEXT: beqz a1, .LBB11_58 ; RV32I-NEXT: .LBB11_62: -; RV32I-NEXT: lw a6, 80(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw t5, 76(sp) # 4-byte Folded Reload -; RV32I-NEXT: bltz s2, .LBB11_67 -; RV32I-NEXT: # %bb.63: -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: j .LBB11_68 +; RV32I-NEXT: mv t1, s3 +; RV32I-NEXT: lw a5, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgez a5, .LBB11_59 +; RV32I-NEXT: .LBB11_63: +; RV32I-NEXT: srl s1, s8, s10 +; RV32I-NEXT: or a6, a4, s1 +; RV32I-NEXT: bgez t0, .LBB11_60 ; RV32I-NEXT: .LBB11_64: -; RV32I-NEXT: mv s9, a0 -; RV32I-NEXT: bgeu a1, s3, .LBB11_59 +; RV32I-NEXT: srl a4, s9, t3 +; RV32I-NEXT: or a4, ra, a4 ; RV32I-NEXT: .LBB11_65: -; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a0, t5 -; RV32I-NEXT: or s9, a6, a0 -; RV32I-NEXT: beqz a1, .LBB11_60 -; RV32I-NEXT: .LBB11_66: -; RV32I-NEXT: mv s4, s9 -; RV32I-NEXT: bltz s8, .LBB11_61 -; RV32I-NEXT: j .LBB11_62 +; RV32I-NEXT: lw t3, 20(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t0, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgeu s0, a7, .LBB11_67 +; RV32I-NEXT: # %bb.66: +; RV32I-NEXT: lw a5, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: slti a5, a5, 0 +; RV32I-NEXT: neg a5, a5 +; RV32I-NEXT: and s1, a5, t3 +; RV32I-NEXT: or a6, a4, s1 ; RV32I-NEXT: .LBB11_67: -; RV32I-NEXT: srl a0, s7, t4 -; RV32I-NEXT: or a0, a7, a0 -; RV32I-NEXT: .LBB11_68: -; RV32I-NEXT: lw t4, 72(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgeu t3, t1, .LBB11_70 -; RV32I-NEXT: # %bb.69: -; RV32I-NEXT: lw a4, 16(sp) # 4-byte Folded Reload -; RV32I-NEXT: slti a4, a4, 0 -; RV32I-NEXT: neg a4, a4 -; RV32I-NEXT: lw s6, 20(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a4, s6 -; RV32I-NEXT: or s6, a0, a4 -; RV32I-NEXT: .LBB11_70: -; RV32I-NEXT: beqz t3, .LBB11_72 -; RV32I-NEXT: # %bb.71: -; RV32I-NEXT: sw s6, 84(sp) # 4-byte Folded Spill -; RV32I-NEXT: .LBB11_72: -; RV32I-NEXT: mv a4, s1 -; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: bgez a0, .LBB11_79 -; RV32I-NEXT: # %bb.73: -; RV32I-NEXT: bgeu s5, t1, .LBB11_80 +; RV32I-NEXT: beqz s0, .LBB11_69 +; RV32I-NEXT: # %bb.68: +; RV32I-NEXT: sw a6, 60(sp) # 4-byte Folded Spill +; RV32I-NEXT: .LBB11_69: +; RV32I-NEXT: mv a4, s6 +; RV32I-NEXT: lw a5, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a5, .LBB11_71 +; RV32I-NEXT: # %bb.70: +; RV32I-NEXT: mv a4, a0 +; RV32I-NEXT: .LBB11_71: +; RV32I-NEXT: li t3, 128 +; RV32I-NEXT: lw s0, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a6, 44(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgeu s4, a7, .LBB11_92 +; RV32I-NEXT: # %bb.72: +; RV32I-NEXT: bltu a1, t3, .LBB11_93 +; RV32I-NEXT: .LBB11_73: +; RV32I-NEXT: bnez a1, .LBB11_94 ; RV32I-NEXT: .LBB11_74: -; RV32I-NEXT: bltu a1, s3, .LBB11_81 +; RV32I-NEXT: mv a4, t0 +; RV32I-NEXT: bgez s0, .LBB11_95 ; RV32I-NEXT: .LBB11_75: -; RV32I-NEXT: lw s5, 60(sp) # 4-byte Folded Reload -; RV32I-NEXT: bnez a1, .LBB11_82 +; RV32I-NEXT: bgez s7, .LBB11_96 ; RV32I-NEXT: .LBB11_76: -; RV32I-NEXT: bltz s5, .LBB11_83 +; RV32I-NEXT: bltu a1, a7, .LBB11_97 ; RV32I-NEXT: .LBB11_77: -; RV32I-NEXT: mv a4, s1 -; RV32I-NEXT: bgez t6, .LBB11_84 +; RV32I-NEXT: bnez a1, .LBB11_98 ; RV32I-NEXT: .LBB11_78: -; RV32I-NEXT: lw a0, 52(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a0, a0, s2 -; RV32I-NEXT: lw t3, 28(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a0, t3, a0 -; RV32I-NEXT: bltu a1, t1, .LBB11_85 -; RV32I-NEXT: j .LBB11_86 +; RV32I-NEXT: bgeu a1, t3, .LBB11_99 ; RV32I-NEXT: .LBB11_79: -; RV32I-NEXT: mv a4, s11 -; RV32I-NEXT: bltu s5, t1, .LBB11_74 +; RV32I-NEXT: lw a4, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz a4, .LBB11_100 ; RV32I-NEXT: .LBB11_80: -; RV32I-NEXT: mv a4, s11 -; RV32I-NEXT: bgeu a1, s3, .LBB11_75 +; RV32I-NEXT: mv a4, s6 +; RV32I-NEXT: bgez s0, .LBB11_101 ; RV32I-NEXT: .LBB11_81: -; RV32I-NEXT: lw a0, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw a4, 36(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a4, a0 -; RV32I-NEXT: lw a4, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a4, a0 -; RV32I-NEXT: lw a4, 84(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a4, a0, a4 -; RV32I-NEXT: lw s5, 60(sp) # 4-byte Folded Reload -; RV32I-NEXT: beqz a1, .LBB11_76 +; RV32I-NEXT: bltu a1, a7, .LBB11_102 ; RV32I-NEXT: .LBB11_82: -; RV32I-NEXT: mv a5, a4 -; RV32I-NEXT: bgez s5, .LBB11_77 +; RV32I-NEXT: bnez a1, .LBB11_103 ; RV32I-NEXT: .LBB11_83: -; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload -; RV32I-NEXT: sll a0, t5, a0 -; RV32I-NEXT: or a4, a6, a0 -; RV32I-NEXT: bltz t6, .LBB11_78 +; RV32I-NEXT: bgeu a1, t3, .LBB11_104 ; RV32I-NEXT: .LBB11_84: -; RV32I-NEXT: mv a0, t4 -; RV32I-NEXT: bgeu a1, t1, .LBB11_86 +; RV32I-NEXT: lw a4, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgez s7, .LBB11_105 ; RV32I-NEXT: .LBB11_85: -; RV32I-NEXT: lw a4, 48(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a4, a4, s0 -; RV32I-NEXT: or a4, a0, a4 +; RV32I-NEXT: bgeu a1, a7, .LBB11_106 ; RV32I-NEXT: .LBB11_86: -; RV32I-NEXT: bnez a1, .LBB11_95 -; RV32I-NEXT: # %bb.87: -; RV32I-NEXT: bgeu a1, s3, .LBB11_96 +; RV32I-NEXT: bgeu a1, t3, .LBB11_107 +; RV32I-NEXT: .LBB11_87: +; RV32I-NEXT: bgez s7, .LBB11_108 ; RV32I-NEXT: .LBB11_88: -; RV32I-NEXT: bltz s8, .LBB11_97 +; RV32I-NEXT: bgeu a1, a7, .LBB11_109 ; RV32I-NEXT: .LBB11_89: -; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: bgez s5, .LBB11_98 +; RV32I-NEXT: bltu a1, t3, .LBB11_91 ; RV32I-NEXT: .LBB11_90: -; RV32I-NEXT: bltu a1, t1, .LBB11_99 +; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: .LBB11_91: -; RV32I-NEXT: bnez a1, .LBB11_100 -; RV32I-NEXT: .LBB11_92: -; RV32I-NEXT: bgeu a1, s3, .LBB11_101 -; RV32I-NEXT: .LBB11_93: -; RV32I-NEXT: bltz t6, .LBB11_102 -; RV32I-NEXT: .LBB11_94: -; RV32I-NEXT: mv a4, s1 -; RV32I-NEXT: bgeu a1, t1, .LBB11_103 -; RV32I-NEXT: j .LBB11_104 -; RV32I-NEXT: .LBB11_95: -; RV32I-NEXT: mv t0, a4 -; RV32I-NEXT: bltu a1, s3, .LBB11_88 -; RV32I-NEXT: .LBB11_96: -; RV32I-NEXT: mv t0, s11 -; RV32I-NEXT: bgez s8, .LBB11_89 -; RV32I-NEXT: .LBB11_97: -; RV32I-NEXT: lw a0, 32(sp) # 4-byte Folded Reload -; RV32I-NEXT: srl a0, s7, a0 -; RV32I-NEXT: or s0, a7, a0 -; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: bltz s5, .LBB11_90 -; RV32I-NEXT: .LBB11_98: -; RV32I-NEXT: mv a0, s11 -; RV32I-NEXT: bgeu a1, t1, .LBB11_91 -; RV32I-NEXT: .LBB11_99: -; RV32I-NEXT: lw a0, 36(sp) # 4-byte Folded Reload -; RV32I-NEXT: and a0, a0, t4 -; RV32I-NEXT: or a0, a0, s0 -; RV32I-NEXT: beqz a1, .LBB11_92 -; RV32I-NEXT: .LBB11_100: -; RV32I-NEXT: mv a3, a0 -; RV32I-NEXT: bltu a1, s3, .LBB11_93 -; RV32I-NEXT: .LBB11_101: -; RV32I-NEXT: mv a3, s11 -; RV32I-NEXT: bgez t6, .LBB11_94 -; RV32I-NEXT: .LBB11_102: -; RV32I-NEXT: sll a0, t5, s2 -; RV32I-NEXT: or a4, a6, a0 -; RV32I-NEXT: bltu a1, t1, .LBB11_104 -; RV32I-NEXT: .LBB11_103: -; RV32I-NEXT: mv a4, s11 -; RV32I-NEXT: .LBB11_104: -; RV32I-NEXT: bgeu a1, s3, .LBB11_110 -; RV32I-NEXT: # %bb.105: -; RV32I-NEXT: bgez t6, .LBB11_111 -; RV32I-NEXT: .LBB11_106: -; RV32I-NEXT: bgeu a1, t1, .LBB11_112 -; RV32I-NEXT: .LBB11_107: -; RV32I-NEXT: bltu a1, s3, .LBB11_109 -; RV32I-NEXT: .LBB11_108: -; RV32I-NEXT: mv s1, s11 -; RV32I-NEXT: .LBB11_109: -; RV32I-NEXT: sb s1, 28(a2) -; RV32I-NEXT: srli a0, s1, 24 +; RV32I-NEXT: sb s6, 28(a2) +; RV32I-NEXT: srli a0, s6, 24 ; RV32I-NEXT: sb a0, 31(a2) -; RV32I-NEXT: srli a0, s1, 16 +; RV32I-NEXT: srli a0, s6, 16 ; RV32I-NEXT: sb a0, 30(a2) -; RV32I-NEXT: srli s1, s1, 8 -; RV32I-NEXT: sb s1, 29(a2) -; RV32I-NEXT: sb a4, 24(a2) -; RV32I-NEXT: srli a0, a4, 24 +; RV32I-NEXT: srli a0, s6, 8 +; RV32I-NEXT: sb a0, 29(a2) +; RV32I-NEXT: sb t0, 24(a2) +; RV32I-NEXT: srli a0, t0, 24 ; RV32I-NEXT: sb a0, 27(a2) -; RV32I-NEXT: srli a0, a4, 16 +; RV32I-NEXT: srli a0, t0, 16 ; RV32I-NEXT: sb a0, 26(a2) -; RV32I-NEXT: srli a4, a4, 8 -; RV32I-NEXT: sb a4, 25(a2) -; RV32I-NEXT: sb t0, 16(a2) -; RV32I-NEXT: srli a0, t0, 24 +; RV32I-NEXT: srli a0, t0, 8 +; RV32I-NEXT: sb a0, 25(a2) +; RV32I-NEXT: sb t4, 16(a2) +; RV32I-NEXT: srli a0, t4, 24 ; RV32I-NEXT: sb a0, 19(a2) -; RV32I-NEXT: srli a0, t0, 16 +; RV32I-NEXT: srli a0, t4, 16 ; RV32I-NEXT: sb a0, 18(a2) -; RV32I-NEXT: srli a0, t0, 8 +; RV32I-NEXT: srli a0, t4, 8 ; RV32I-NEXT: sb a0, 17(a2) ; RV32I-NEXT: sb a3, 20(a2) ; RV32I-NEXT: srli a0, a3, 24 @@ -4073,59 +3888,119 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sb a0, 22(a2) ; RV32I-NEXT: srli a3, a3, 8 ; RV32I-NEXT: sb a3, 21(a2) -; RV32I-NEXT: sb t2, 0(a2) -; RV32I-NEXT: sb a5, 12(a2) -; RV32I-NEXT: srli a0, t2, 24 +; RV32I-NEXT: sb t6, 0(a2) +; RV32I-NEXT: sb a6, 12(a2) +; RV32I-NEXT: srli a0, t6, 24 ; RV32I-NEXT: sb a0, 3(a2) -; RV32I-NEXT: srli a0, t2, 16 +; RV32I-NEXT: srli a0, t6, 16 ; RV32I-NEXT: sb a0, 2(a2) -; RV32I-NEXT: srli a0, t2, 8 +; RV32I-NEXT: srli a0, t6, 8 ; RV32I-NEXT: sb a0, 1(a2) -; RV32I-NEXT: sb s4, 4(a2) -; RV32I-NEXT: sb ra, 8(a2) -; RV32I-NEXT: srli a0, a5, 24 +; RV32I-NEXT: sb t1, 4(a2) +; RV32I-NEXT: sb a4, 8(a2) +; RV32I-NEXT: srli a0, a6, 24 ; RV32I-NEXT: sb a0, 15(a2) -; RV32I-NEXT: srli a0, a5, 16 +; RV32I-NEXT: srli a0, a6, 16 ; RV32I-NEXT: sb a0, 14(a2) -; RV32I-NEXT: srli a5, a5, 8 -; RV32I-NEXT: sb a5, 13(a2) -; RV32I-NEXT: srli a0, s4, 24 +; RV32I-NEXT: srli a0, a6, 8 +; RV32I-NEXT: sb a0, 13(a2) +; RV32I-NEXT: srli a0, t1, 24 ; RV32I-NEXT: sb a0, 7(a2) -; RV32I-NEXT: srli a0, s4, 16 +; RV32I-NEXT: srli a0, t1, 16 ; RV32I-NEXT: sb a0, 6(a2) -; RV32I-NEXT: srli a0, s4, 8 +; RV32I-NEXT: srli a0, t1, 8 ; RV32I-NEXT: sb a0, 5(a2) -; RV32I-NEXT: srli a0, ra, 24 +; RV32I-NEXT: srli a0, a4, 24 ; RV32I-NEXT: sb a0, 11(a2) -; RV32I-NEXT: srli a0, ra, 16 +; RV32I-NEXT: srli a0, a4, 16 ; RV32I-NEXT: sb a0, 10(a2) -; RV32I-NEXT: srli a0, ra, 8 +; RV32I-NEXT: srli a0, a4, 8 ; RV32I-NEXT: sb a0, 9(a2) -; RV32I-NEXT: lw ra, 140(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 136(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 132(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 128(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s3, 124(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s4, 120(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s5, 116(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s6, 112(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s7, 108(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s8, 104(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s9, 100(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s10, 96(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s11, 92(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 144 +; RV32I-NEXT: lw ra, 124(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 120(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 116(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 112(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s3, 108(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s4, 104(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s5, 100(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s6, 96(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s7, 92(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s8, 88(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s9, 84(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s10, 80(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s11, 76(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 128 ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB11_110: -; RV32I-NEXT: mv a4, s11 -; RV32I-NEXT: bltz t6, .LBB11_106 -; RV32I-NEXT: .LBB11_111: -; RV32I-NEXT: mv s1, s11 -; RV32I-NEXT: bltu a1, t1, .LBB11_107 -; RV32I-NEXT: .LBB11_112: -; RV32I-NEXT: mv s1, s11 -; RV32I-NEXT: bgeu a1, s3, .LBB11_108 -; RV32I-NEXT: j .LBB11_109 +; RV32I-NEXT: .LBB11_92: +; RV32I-NEXT: mv a4, a0 +; RV32I-NEXT: bgeu a1, t3, .LBB11_73 +; RV32I-NEXT: .LBB11_93: +; RV32I-NEXT: lw a4, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a4, s5, a4 +; RV32I-NEXT: and a4, s2, a4 +; RV32I-NEXT: lw a5, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: or a4, a4, a5 +; RV32I-NEXT: beqz a1, .LBB11_74 +; RV32I-NEXT: .LBB11_94: +; RV32I-NEXT: mv a6, a4 +; RV32I-NEXT: mv a4, t0 +; RV32I-NEXT: bltz s0, .LBB11_75 +; RV32I-NEXT: .LBB11_95: +; RV32I-NEXT: mv a4, s6 +; RV32I-NEXT: bltz s7, .LBB11_76 +; RV32I-NEXT: .LBB11_96: +; RV32I-NEXT: lw a5, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a5, 40(sp) # 4-byte Folded Spill +; RV32I-NEXT: bgeu a1, a7, .LBB11_77 +; RV32I-NEXT: .LBB11_97: +; RV32I-NEXT: lw a4, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a4, a4, t2 +; RV32I-NEXT: lw a5, 40(sp) # 4-byte Folded Reload +; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: beqz a1, .LBB11_78 +; RV32I-NEXT: .LBB11_98: +; RV32I-NEXT: mv t4, a4 +; RV32I-NEXT: bltu a1, t3, .LBB11_79 +; RV32I-NEXT: .LBB11_99: +; RV32I-NEXT: mv t4, a0 +; RV32I-NEXT: lw a4, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: bgez a4, .LBB11_80 +; RV32I-NEXT: .LBB11_100: +; RV32I-NEXT: srl a4, s9, s10 +; RV32I-NEXT: or t2, ra, a4 +; RV32I-NEXT: mv a4, s6 +; RV32I-NEXT: bltz s0, .LBB11_81 +; RV32I-NEXT: .LBB11_101: +; RV32I-NEXT: mv a4, a0 +; RV32I-NEXT: bgeu a1, a7, .LBB11_82 +; RV32I-NEXT: .LBB11_102: +; RV32I-NEXT: lw a4, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: and a4, s5, a4 +; RV32I-NEXT: or a4, a4, t2 +; RV32I-NEXT: beqz a1, .LBB11_83 +; RV32I-NEXT: .LBB11_103: +; RV32I-NEXT: mv a3, a4 +; RV32I-NEXT: bltu a1, t3, .LBB11_84 +; RV32I-NEXT: .LBB11_104: +; RV32I-NEXT: mv a3, a0 +; RV32I-NEXT: lw a4, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: bltz s7, .LBB11_85 +; RV32I-NEXT: .LBB11_105: +; RV32I-NEXT: mv t0, s6 +; RV32I-NEXT: bltu a1, a7, .LBB11_86 +; RV32I-NEXT: .LBB11_106: +; RV32I-NEXT: mv t0, a0 +; RV32I-NEXT: bltu a1, t3, .LBB11_87 +; RV32I-NEXT: .LBB11_107: +; RV32I-NEXT: mv t0, a0 +; RV32I-NEXT: bltz s7, .LBB11_88 +; RV32I-NEXT: .LBB11_108: +; RV32I-NEXT: mv s6, a0 +; RV32I-NEXT: bltu a1, a7, .LBB11_89 +; RV32I-NEXT: .LBB11_109: +; RV32I-NEXT: mv s6, a0 +; RV32I-NEXT: bgeu a1, t3, .LBB11_90 +; RV32I-NEXT: j .LBB11_91 %src = load i256, ptr %src.ptr, align 1 %bitOff = load i256, ptr %bitOff.ptr, align 1 %res = ashr i256 %src, %bitOff