diff --git a/llvm/test/CodeGen/AArch64/cond-sel-value-prop.ll b/llvm/test/CodeGen/AArch64/cond-sel-value-prop.ll index 155e6e3773928..852a3e33167df 100644 --- a/llvm/test/CodeGen/AArch64/cond-sel-value-prop.ll +++ b/llvm/test/CodeGen/AArch64/cond-sel-value-prop.ll @@ -1,33 +1,40 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s ; Transform "a == C ? C : x" to "a == C ? a : x" to avoid materializing C. -; CHECK-LABEL: test1: -; CHECK: cmp w[[REG1:[0-9]+]], #2 -; CHECK: mov w[[REG2:[0-9]+]], #7 -; CHECK: csel w0, w[[REG1]], w[[REG2]], eq define i32 @test1(i32 %x) { +; CHECK-LABEL: test1: +; CHECK: // %bb.0: +; CHECK-NEXT: cmp w0, #2 +; CHECK-NEXT: mov w8, #7 +; CHECK-NEXT: csel w0, w0, w8, eq +; CHECK-NEXT: ret %cmp = icmp eq i32 %x, 2 %res = select i1 %cmp, i32 2, i32 7 ret i32 %res } ; Transform "a == C ? C : x" to "a == C ? a : x" to avoid materializing C. -; CHECK-LABEL: test2: -; CHECK: cmp x[[REG1:[0-9]+]], #2 -; CHECK: mov w[[REG2:[0-9]+]], #7 -; CHECK: csel x0, x[[REG1]], x[[REG2]], eq define i64 @test2(i64 %x) { +; CHECK-LABEL: test2: +; CHECK: // %bb.0: +; CHECK-NEXT: cmp x0, #2 +; CHECK-NEXT: mov w8, #7 +; CHECK-NEXT: csel x0, x0, x8, eq +; CHECK-NEXT: ret %cmp = icmp eq i64 %x, 2 %res = select i1 %cmp, i64 2, i64 7 ret i64 %res } ; Transform "a != C ? x : C" to "a != C ? x : a" to avoid materializing C. -; CHECK-LABEL: test3: -; CHECK: cmp x[[REG1:[0-9]+]], #7 -; CHECK: mov w[[REG2:[0-9]+]], #2 -; CHECK: csel x0, x[[REG2]], x[[REG1]], ne define i64 @test3(i64 %x) { +; CHECK-LABEL: test3: +; CHECK: // %bb.0: +; CHECK-NEXT: cmp x0, #7 +; CHECK-NEXT: mov w8, #2 +; CHECK-NEXT: csel x0, x8, x0, ne +; CHECK-NEXT: ret %cmp = icmp ne i64 %x, 7 %res = select i1 %cmp, i64 2, i64 7 ret i64 %res @@ -35,11 +42,13 @@ define i64 @test3(i64 %x) { ; Don't transform "a == C ? C : x" to "a == C ? a : x" if a == 0. If we did we ; would needlessly extend the live range of x0 when we can just use xzr. -; CHECK-LABEL: test4: -; CHECK: cmp x0, #0 -; CHECK: mov w8, #7 -; CHECK: csel x0, xzr, x8, eq define i64 @test4(i64 %x) { +; CHECK-LABEL: test4: +; CHECK: // %bb.0: +; CHECK-NEXT: cmp x0, #0 +; CHECK-NEXT: mov w8, #7 +; CHECK-NEXT: csel x0, xzr, x8, eq +; CHECK-NEXT: ret %cmp = icmp eq i64 %x, 0 %res = select i1 %cmp, i64 0, i64 7 ret i64 %res @@ -48,11 +57,13 @@ define i64 @test4(i64 %x) { ; Don't transform "a == C ? C : x" to "a == C ? a : x" if a == 1. If we did we ; would needlessly extend the live range of x0 when we can just use xzr with ; CSINC to materialize the 1. -; CHECK-LABEL: test5: -; CHECK: cmp x0, #1 -; CHECK: mov w[[REG:[0-9]+]], #7 -; CHECK: csinc x0, x[[REG]], xzr, ne define i64 @test5(i64 %x) { +; CHECK-LABEL: test5: +; CHECK: // %bb.0: +; CHECK-NEXT: cmp x0, #1 +; CHECK-NEXT: mov w8, #7 +; CHECK-NEXT: csinc x0, x8, xzr, ne +; CHECK-NEXT: ret %cmp = icmp eq i64 %x, 1 %res = select i1 %cmp, i64 1, i64 7 ret i64 %res @@ -61,38 +72,46 @@ define i64 @test5(i64 %x) { ; Don't transform "a == C ? C : x" to "a == C ? a : x" if a == -1. If we did we ; would needlessly extend the live range of x0 when we can just use xzr with ; CSINV to materialize the -1. -; CHECK-LABEL: test6: -; CHECK: cmn x0, #1 -; CHECK: mov w[[REG:[0-9]+]], #7 -; CHECK: csinv x0, x[[REG]], xzr, ne define i64 @test6(i64 %x) { +; CHECK-LABEL: test6: +; CHECK: // %bb.0: +; CHECK-NEXT: cmn x0, #1 +; CHECK-NEXT: mov w8, #7 +; CHECK-NEXT: csinv x0, x8, xzr, ne +; CHECK-NEXT: ret %cmp = icmp eq i64 %x, -1 %res = select i1 %cmp, i64 -1, i64 7 ret i64 %res } -; CHECK-LABEL: test7: -; CHECK: cmp x[[REG:[0-9]]], #7 -; CHECK: csinc x0, x[[REG]], xzr, eq define i64 @test7(i64 %x) { +; CHECK-LABEL: test7: +; CHECK: // %bb.0: +; CHECK-NEXT: cmp x0, #7 +; CHECK-NEXT: csinc x0, x0, xzr, eq +; CHECK-NEXT: ret %cmp = icmp eq i64 %x, 7 %res = select i1 %cmp, i64 7, i64 1 ret i64 %res } -; CHECK-LABEL: test8: -; CHECK: cmp x[[REG:[0-9]]], #7 -; CHECK: csinc x0, x[[REG]], xzr, eq define i64 @test8(i64 %x) { +; CHECK-LABEL: test8: +; CHECK: // %bb.0: +; CHECK-NEXT: cmp x0, #7 +; CHECK-NEXT: csinc x0, x0, xzr, eq +; CHECK-NEXT: ret %cmp = icmp ne i64 %x, 7 %res = select i1 %cmp, i64 1, i64 7 ret i64 %res } -; CHECK-LABEL: test9: -; CHECK: cmp x[[REG:[0-9]]], #7 -; CHECK: csinv x0, x[[REG]], xzr, eq define i64 @test9(i64 %x) { +; CHECK-LABEL: test9: +; CHECK: // %bb.0: +; CHECK-NEXT: cmp x0, #7 +; CHECK-NEXT: csinv x0, x0, xzr, eq +; CHECK-NEXT: ret %cmp = icmp eq i64 %x, 7 %res = select i1 %cmp, i64 7, i64 -1 ret i64 %res @@ -100,10 +119,12 @@ define i64 @test9(i64 %x) { ; Rather than use a CNEG, use a CSINV to transform "a == 1 ? 1 : -1" to ; "a == 1 ? a : -1" to avoid materializing a constant. -; CHECK-LABEL: test10: -; CHECK: cmp w[[REG:[0-9]]], #1 -; CHECK: csinv w0, w[[REG]], wzr, eq define i32 @test10(i32 %x) { +; CHECK-LABEL: test10: +; CHECK: // %bb.0: +; CHECK-NEXT: cmp w0, #1 +; CHECK-NEXT: csinv w0, w0, wzr, eq +; CHECK-NEXT: ret %cmp = icmp eq i32 %x, 1 %res = select i1 %cmp, i32 1, i32 -1 ret i32 %res diff --git a/llvm/test/CodeGen/AArch64/isinf.ll b/llvm/test/CodeGen/AArch64/isinf.ll index bcb249f82f3a5..2032ff9429b03 100644 --- a/llvm/test/CodeGen/AArch64/isinf.ll +++ b/llvm/test/CodeGen/AArch64/isinf.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 < %s -o -| FileCheck %s declare half @llvm.fabs.f16(half) @@ -8,11 +9,13 @@ declare fp128 @llvm.fabs.f128(fp128) ; INFINITY requires loading the constant for _Float16 define i32 @replace_isinf_call_f16(half %x) { ; CHECK-LABEL: replace_isinf_call_f16: -; CHECK: adrp [[ADDR:x[0-9]+]], [[CSTLABEL:.LCP.*]] -; CHECK: ldr [[INFINITY:h[0-9]+]], {{[[]}}[[ADDR]], :lo12:[[CSTLABEL]]{{[]]}} -; CHECK-NEXT: fabs [[ABS:h[0-9]+]], h0 -; CHECK-NEXT: fcmp [[ABS]], [[INFINITY]] -; CHECK-NEXT: cset w0, eq +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI0_0 +; CHECK-NEXT: ldr h1, [x8, :lo12:.LCPI0_0] +; CHECK-NEXT: fabs h0, h0 +; CHECK-NEXT: fcmp h0, h1 +; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: ret %abs = tail call half @llvm.fabs.f16(half %x) %cmpinf = fcmp oeq half %abs, 0xH7C00 %ret = zext i1 %cmpinf to i32 @@ -22,11 +25,13 @@ define i32 @replace_isinf_call_f16(half %x) { ; Check if INFINITY for float is materialized define i32 @replace_isinf_call_f32(float %x) { ; CHECK-LABEL: replace_isinf_call_f32: -; CHECK: mov [[INFSCALARREG:w[0-9]+]], #2139095040 -; CHECK-NEXT: fabs [[ABS:s[0-9]+]], s0 -; CHECK-NEXT: fmov [[INFREG:s[0-9]+]], [[INFSCALARREG]] -; CHECK-NEXT: fcmp [[ABS]], [[INFREG]] -; CHECK-NEXT: cset w0, eq +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #2139095040 +; CHECK-NEXT: fabs s0, s0 +; CHECK-NEXT: fmov s1, w8 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: ret %abs = tail call float @llvm.fabs.f32(float %x) %cmpinf = fcmp oeq float %abs, 0x7FF0000000000000 %ret = zext i1 %cmpinf to i32 @@ -36,11 +41,13 @@ define i32 @replace_isinf_call_f32(float %x) { ; Check if INFINITY for double is materialized define i32 @replace_isinf_call_f64(double %x) { ; CHECK-LABEL: replace_isinf_call_f64: -; CHECK: mov [[INFSCALARREG:x[0-9]+]], #9218868437227405312 -; CHECK-NEXT: fabs [[ABS:d[0-9]+]], d0 -; CHECK-NEXT: fmov [[INFREG:d[0-9]+]], [[INFSCALARREG]] -; CHECK-NEXT: fcmp [[ABS]], [[INFREG]] -; CHECK-NEXT: cset w0, eq +; CHECK: // %bb.0: +; CHECK-NEXT: mov x8, #9218868437227405312 +; CHECK-NEXT: fabs d0, d0 +; CHECK-NEXT: fmov d1, x8 +; CHECK-NEXT: fcmp d0, d1 +; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: ret %abs = tail call double @llvm.fabs.f64(double %x) %cmpinf = fcmp oeq double %abs, 0x7FF0000000000000 %ret = zext i1 %cmpinf to i32 @@ -50,11 +57,24 @@ define i32 @replace_isinf_call_f64(double %x) { ; For long double it still requires loading the constant. define i32 @replace_isinf_call_f128(fp128 %x) { ; CHECK-LABEL: replace_isinf_call_f128: -; CHECK: adrp [[ADDR:x[0-9]+]], [[CSTLABEL:.LCP.*]] -; CHECK: ldr q1, {{[[]}}[[ADDR]], :lo12:[[CSTLABEL]]{{[]]}} -; CHECK: bl __eqtf2 -; CHECK: cmp w0, #0 -; CHECK: cset w0, eq +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #32 +; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: .cfi_offset w30, -16 +; CHECK-NEXT: str q0, [sp] +; CHECK-NEXT: ldrb w8, [sp, #15] +; CHECK-NEXT: and w8, w8, #0x7f +; CHECK-NEXT: strb w8, [sp, #15] +; CHECK-NEXT: adrp x8, .LCPI3_0 +; CHECK-NEXT: ldr q0, [sp] +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0] +; CHECK-NEXT: bl __eqtf2 +; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload +; CHECK-NEXT: cmp w0, #0 +; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: add sp, sp, #32 +; CHECK-NEXT: ret %abs = tail call fp128 @llvm.fabs.f128(fp128 %x) %cmpinf = fcmp oeq fp128 %abs, 0xL00000000000000007FFF000000000000 %ret = zext i1 %cmpinf to i32 diff --git a/llvm/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll b/llvm/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll index 79fefdb2769a4..728b65c058f4c 100644 --- a/llvm/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll +++ b/llvm/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll @@ -1,19 +1,21 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=aarch64-apple-ios -fast-isel -verify-machineinstrs | FileCheck %s ; Check that the kill flag is cleared between CSE'd instructions on their ; imp-def'd registers. ; The verifier would complain otherwise. -define i64 @csed-impdef-killflag(i64 %a) { -; CHECK-LABEL: csed-impdef-killflag -; CHECK-DAG: mov [[REG1:w[0-9]+]], #1 -; CHECK-DAG: mov [[REG2:x[0-9]+]], #2 -; CHECK-DAG: mov [[REG3:x[0-9]+]], #3 -; CHECK-DAG: cmp x0, #0 -; CHECK: csel w[[SELECT_WREG_1:[0-9]+]], wzr, [[REG1]], ne -; CHECK-DAG: csel [[SELECT_XREG_2:x[0-9]+]], [[REG2]], [[REG3]], ne -; CHECK: ubfx [[SELECT_XREG_1:x[0-9]+]], x[[SELECT_WREG_1]], #0, #32 -; CHECK-NEXT: add x0, [[SELECT_XREG_2]], [[SELECT_XREG_1]] -; CHECK-NEXT: ret +define i64 @csed_impdef_killflag(i64 %a) { +; CHECK-LABEL: csed_impdef_killflag: +; CHECK: ; %bb.0: +; CHECK-NEXT: mov w8, #1 +; CHECK-NEXT: cmp x0, #0 +; CHECK-NEXT: mov x9, #2 +; CHECK-NEXT: mov x10, #3 +; CHECK-NEXT: csel w8, wzr, w8, ne +; CHECK-NEXT: csel x9, x9, x10, ne +; CHECK-NEXT: ubfx x8, x8, #0, #32 +; CHECK-NEXT: add x0, x9, x8 +; CHECK-NEXT: ret %1 = icmp ne i64 %a, 0 %2 = select i1 %1, i32 0, i32 1 diff --git a/llvm/test/CodeGen/AArch64/madd-lohi.ll b/llvm/test/CodeGen/AArch64/madd-lohi.ll index 550a8cb24b774..4e320cd967a54 100644 --- a/llvm/test/CodeGen/AArch64/madd-lohi.ll +++ b/llvm/test/CodeGen/AArch64/madd-lohi.ll @@ -1,18 +1,24 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=arm64-apple-ios7.0 %s -o - | FileCheck %s ; RUN: llc -mtriple=aarch64_be-linux-gnu %s -o - | FileCheck --check-prefix=CHECK-BE %s define i128 @test_128bitmul(i128 %lhs, i128 %rhs) { ; CHECK-LABEL: test_128bitmul: -; CHECK-DAG: umulh [[CARRY:x[0-9]+]], x0, x2 -; CHECK-DAG: madd [[PART1:x[0-9]+]], x0, x3, [[CARRY]] -; CHECK: madd x1, x1, x2, [[PART1]] -; CHECK: mul x0, x0, x2 - +; CHECK: ; %bb.0: +; CHECK-NEXT: umulh x8, x0, x2 +; CHECK-NEXT: madd x8, x0, x3, x8 +; CHECK-NEXT: madd x1, x1, x2, x8 +; CHECK-NEXT: mul x0, x0, x2 +; CHECK-NEXT: ret +; ; CHECK-BE-LABEL: test_128bitmul: -; CHECK-BE-DAG: umulh [[CARRY:x[0-9]+]], x1, x3 -; CHECK-BE-DAG: madd [[PART1:x[0-9]+]], x1, x2, [[CARRY]] -; CHECK-BE: madd x0, x0, x3, [[PART1]] -; CHECK-BE: mul x1, x1, x3 +; CHECK-BE: // %bb.0: +; CHECK-BE-NEXT: umulh x8, x1, x3 +; CHECK-BE-NEXT: madd x8, x1, x2, x8 +; CHECK-BE-NEXT: madd x0, x0, x3, x8 +; CHECK-BE-NEXT: mul x1, x1, x3 +; CHECK-BE-NEXT: ret + %prod = mul i128 %lhs, %rhs ret i128 %prod diff --git a/llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll b/llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll index 22d5ba7c0fcd4..1736bfb4d3b23 100644 --- a/llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll +++ b/llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=finalize-isel -o - %s | FileCheck --check-prefix=MIR %s @@ -12,12 +13,13 @@ ; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]]) define i32 @test_memcpy(i32* nocapture %p, i32* nocapture readonly %q) { ; CHECK-LABEL: test_memcpy: -; CHECK-DAG: ldp [[Q0:w[0-9]+]], [[Q1:w[0-9]+]], [x1] -; CHECK-DAG: ldr [[PVAL:q[0-9]+]], [x0, #16] -; CHECK-DAG: add w8, [[Q0]], [[Q1]] -; CHECK: str [[PVAL]], [x0] -; CHECK: mov w0, w8 -; CHECK: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldp w8, w9, [x1] +; CHECK-NEXT: ldr q0, [x0, #16] +; CHECK-NEXT: add w8, w8, w9 +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: mov w0, w8 +; CHECK-NEXT: ret %p0 = bitcast i32* %p to i8* %add.ptr = getelementptr inbounds i32, i32* %p, i64 4 %p1 = bitcast i32* %add.ptr to i8* @@ -34,12 +36,13 @@ define i32 @test_memcpy(i32* nocapture %p, i32* nocapture readonly %q) { ; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]]) define i32 @test_memcpy_inline(i32* nocapture %p, i32* nocapture readonly %q) { ; CHECK-LABEL: test_memcpy_inline: -; CHECK-DAG: ldp [[Q0:w[0-9]+]], [[Q1:w[0-9]+]], [x1] -; CHECK-DAG: ldr [[PVAL:q[0-9]+]], [x0, #16] -; CHECK-DAG: add w8, [[Q0]], [[Q1]] -; CHECK: str [[PVAL]], [x0] -; CHECK: mov w0, w8 -; CHECK: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldp w8, w9, [x1] +; CHECK-NEXT: ldr q0, [x0, #16] +; CHECK-NEXT: add w8, w8, w9 +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: mov w0, w8 +; CHECK-NEXT: ret %p0 = bitcast i32* %p to i8* %add.ptr = getelementptr inbounds i32, i32* %p, i64 4 %p1 = bitcast i32* %add.ptr to i8* @@ -56,12 +59,13 @@ define i32 @test_memcpy_inline(i32* nocapture %p, i32* nocapture readonly %q) { ; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]]) define i32 @test_memmove(i32* nocapture %p, i32* nocapture readonly %q) { ; CHECK-LABEL: test_memmove: -; CHECK-DAG: ldp [[Q0:w[0-9]+]], [[Q1:w[0-9]+]], [x1] -; CHECK-DAG: ldr [[PVAL:q[0-9]+]], [x0, #16] -; CHECK-DAG: add w8, [[Q0]], [[Q1]] -; CHECK: str [[PVAL]], [x0] -; CHECK: mov w0, w8 -; CHECK: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldp w8, w9, [x1] +; CHECK-NEXT: ldr q0, [x0, #16] +; CHECK-NEXT: add w8, w8, w9 +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: mov w0, w8 +; CHECK-NEXT: ret %p0 = bitcast i32* %p to i8* %add.ptr = getelementptr inbounds i32, i32* %p, i64 4 %p1 = bitcast i32* %add.ptr to i8* @@ -79,12 +83,13 @@ define i32 @test_memmove(i32* nocapture %p, i32* nocapture readonly %q) { ; MIR-NEXT: STRXui %2, %0, 0 :: (store (s64) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]]) define i32 @test_memset(i32* nocapture %p, i32* nocapture readonly %q) { ; CHECK-LABEL: test_memset: -; CHECK-DAG: ldp [[Q0:w[0-9]+]], [[Q1:w[0-9]+]], [x1] -; CHECK-DAG: mov [[PVAL:x[0-9]+]], #-6148914691236517206 -; CHECK: stp [[PVAL]], [[PVAL]], [x0] -; CHECK: add w8, [[Q0]], [[Q1]] -; CHECK: mov w0, w8 -; CHECK: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldp w8, w9, [x1] +; CHECK-NEXT: mov x10, #-6148914691236517206 +; CHECK-NEXT: stp x10, x10, [x0] +; CHECK-NEXT: add w8, w8, w9 +; CHECK-NEXT: mov w0, w8 +; CHECK-NEXT: ret %p0 = bitcast i32* %p to i8* tail call void @llvm.memset.p0i8.i64(i8* noundef nonnull align 4 dereferenceable(16) %p0, i8 170, i64 16, i1 false), !alias.scope !2, !noalias !4 %v0 = load i32, i32* %q, align 4, !alias.scope !4, !noalias !2 @@ -99,12 +104,13 @@ define i32 @test_memset(i32* nocapture %p, i32* nocapture readonly %q) { ; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 1, !alias.scope ![[SET0]], !noalias ![[SET1]]) define i32 @test_mempcpy(i32* nocapture %p, i32* nocapture readonly %q) { ; CHECK-LABEL: test_mempcpy: -; CHECK-DAG: ldp [[Q0:w[0-9]+]], [[Q1:w[0-9]+]], [x1] -; CHECK-DAG: ldr [[PVAL:q[0-9]+]], [x0, #16] -; CHECK-DAG: add w8, [[Q0]], [[Q1]] -; CHECK: str [[PVAL]], [x0] -; CHECK: mov w0, w8 -; CHECK: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldp w8, w9, [x1] +; CHECK-NEXT: ldr q0, [x0, #16] +; CHECK-NEXT: add w8, w8, w9 +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: mov w0, w8 +; CHECK-NEXT: ret %p0 = bitcast i32* %p to i8* %add.ptr = getelementptr inbounds i32, i32* %p, i64 4 %p1 = bitcast i32* %add.ptr to i8* diff --git a/llvm/test/CodeGen/AArch64/movw-consts.ll b/llvm/test/CodeGen/AArch64/movw-consts.ll index 4228f1a25d6ee..66c011aaa69c8 100644 --- a/llvm/test/CodeGen/AArch64/movw-consts.ll +++ b/llvm/test/CodeGen/AArch64/movw-consts.ll @@ -1,51 +1,68 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s define i64 @test0() { ; CHECK-LABEL: test0: +; CHECK: ; %bb.0: +; CHECK-NEXT: mov x0, xzr +; CHECK-NEXT: ret ; Not produced by move wide instructions, but good to make sure we can return 0 anyway: -; CHECK: mov x0, xzr ret i64 0 } define i64 @test1() { ; CHECK-LABEL: test1: -; CHECK: mov w0, #1 +; CHECK: ; %bb.0: +; CHECK-NEXT: mov w0, #1 +; CHECK-NEXT: ret ret i64 1 } define i64 @test2() { ; CHECK-LABEL: test2: -; CHECK: mov w0, #65535 +; CHECK: ; %bb.0: +; CHECK-NEXT: mov w0, #65535 +; CHECK-NEXT: ret ret i64 65535 } define i64 @test3() { ; CHECK-LABEL: test3: -; CHECK: mov w0, #65536 +; CHECK: ; %bb.0: +; CHECK-NEXT: mov w0, #65536 +; CHECK-NEXT: ret ret i64 65536 } define i64 @test4() { ; CHECK-LABEL: test4: -; CHECK: mov w0, #-65536 +; CHECK: ; %bb.0: +; CHECK-NEXT: mov w0, #-65536 +; CHECK-NEXT: ret ret i64 4294901760 } define i64 @test5() { ; CHECK-LABEL: test5: -; CHECK: mov x0, #4294967296 +; CHECK: ; %bb.0: +; CHECK-NEXT: mov x0, #4294967296 +; CHECK-NEXT: ret ret i64 4294967296 } define i64 @test6() { ; CHECK-LABEL: test6: -; CHECK: mov x0, #281470681743360 +; CHECK: ; %bb.0: +; CHECK-NEXT: mov x0, #281470681743360 +; CHECK-NEXT: ret ret i64 281470681743360 } define i64 @test7() { ; CHECK-LABEL: test7: -; CHECK: mov x0, #281474976710656 +; CHECK: ; %bb.0: +; CHECK-NEXT: mov x0, #281474976710656 +; CHECK-NEXT: ret ret i64 281474976710656 } @@ -53,19 +70,25 @@ define i64 @test7() { ; couldn't. Useful even for i64 define i64 @test8() { ; CHECK-LABEL: test8: -; CHECK: mov w0, #-60876 +; CHECK: ; %bb.0: +; CHECK-NEXT: mov w0, #-60876 +; CHECK-NEXT: ret ret i64 4294906420 } define i64 @test9() { ; CHECK-LABEL: test9: -; CHECK: mov x0, #-1 +; CHECK: ; %bb.0: +; CHECK-NEXT: mov x0, #-1 +; CHECK-NEXT: ret ret i64 -1 } define i64 @test10() { ; CHECK-LABEL: test10: -; CHECK: mov x0, #-3989504001 +; CHECK: ; %bb.0: +; CHECK-NEXT: mov x0, #-3989504001 +; CHECK-NEXT: ret ret i64 18446744069720047615 } @@ -75,50 +98,75 @@ define i64 @test10() { define void @test11() { ; CHECK-LABEL: test11: -; CHECK: str wzr +; CHECK: ; %bb.0: +; CHECK-NEXT: adrp x8, _var32@PAGE +; CHECK-NEXT: str wzr, [x8, _var32@PAGEOFF] +; CHECK-NEXT: ret store i32 0, i32* @var32 ret void } define void @test12() { ; CHECK-LABEL: test12: -; CHECK: mov {{w[0-9]+}}, #1 +; CHECK: ; %bb.0: +; CHECK-NEXT: adrp x8, _var32@PAGE +; CHECK-NEXT: mov w9, #1 +; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF] +; CHECK-NEXT: ret store i32 1, i32* @var32 ret void } define void @test13() { ; CHECK-LABEL: test13: -; CHECK: mov {{w[0-9]+}}, #65535 +; CHECK: ; %bb.0: +; CHECK-NEXT: adrp x8, _var32@PAGE +; CHECK-NEXT: mov w9, #65535 +; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF] +; CHECK-NEXT: ret store i32 65535, i32* @var32 ret void } define void @test14() { ; CHECK-LABEL: test14: -; CHECK: mov {{w[0-9]+}}, #65536 +; CHECK: ; %bb.0: +; CHECK-NEXT: adrp x8, _var32@PAGE +; CHECK-NEXT: mov w9, #65536 +; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF] +; CHECK-NEXT: ret store i32 65536, i32* @var32 ret void } define void @test15() { ; CHECK-LABEL: test15: -; CHECK: mov {{w[0-9]+}}, #-65536 +; CHECK: ; %bb.0: +; CHECK-NEXT: adrp x8, _var32@PAGE +; CHECK-NEXT: mov w9, #-65536 +; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF] +; CHECK-NEXT: ret store i32 4294901760, i32* @var32 ret void } define void @test16() { ; CHECK-LABEL: test16: -; CHECK: mov {{w[0-9]+}}, #-1 +; CHECK: ; %bb.0: +; CHECK-NEXT: adrp x8, _var32@PAGE +; CHECK-NEXT: mov w9, #-1 +; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF] +; CHECK-NEXT: ret store i32 -1, i32* @var32 ret void } define i64 @test17() { ; CHECK-LABEL: test17: +; CHECK: ; %bb.0: +; CHECK-NEXT: mov x0, #-3 +; CHECK-NEXT: ret ; Mustn't MOVN w0 here. -; CHECK: mov x0, #-3 ret i64 -3 } diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll index e0539ce54bfdf..30309dbbfe3cc 100644 --- a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll +++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll @@ -268,7 +268,7 @@ define @sub_i32_ptrue_all_d( %a) #0 { define @subr_i8( %a) { ; CHECK-LABEL: subr_i8: ; CHECK: // %bb.0: -; CHECK-NEXT: subr z0.b, z0.b, #127 +; CHECK-NEXT: subr z0.b, z0.b, #127 // =0x7f ; CHECK-NEXT: ret %pg = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) %elt = insertelement undef, i8 127, i32 0 @@ -282,7 +282,7 @@ define @subr_i8( %a) { define @subr_i16( %a) { ; CHECK-LABEL: subr_i16: ; CHECK: // %bb.0: -; CHECK-NEXT: subr z0.h, z0.h, #127 +; CHECK-NEXT: subr z0.h, z0.h, #127 // =0x7f ; CHECK-NEXT: ret %pg = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) %elt = insertelement undef, i16 127, i32 0 @@ -312,7 +312,7 @@ define @subr_i16_out_of_range( %a) { define @subr_i32( %a) { ; CHECK-LABEL: subr_i32: ; CHECK: // %bb.0: -; CHECK-NEXT: subr z0.s, z0.s, #127 +; CHECK-NEXT: subr z0.s, z0.s, #127 // =0x7f ; CHECK-NEXT: ret %pg = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) %elt = insertelement undef, i32 127, i32 0 @@ -342,7 +342,7 @@ define @subr_i32_out_of_range( %a) { define @subr_i64( %a) { ; CHECK-LABEL: subr_i64: ; CHECK: // %bb.0: -; CHECK-NEXT: subr z0.d, z0.d, #127 +; CHECK-NEXT: subr z0.d, z0.d, #127 // =0x7f ; CHECK-NEXT: ret %pg = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) %elt = insertelement undef, i64 127, i64 0 @@ -372,8 +372,9 @@ define @subr_i64_out_of_range( %a) { ; As subr_i32 but where pg is i8 based and thus compatible for i32. define @subr_i32_ptrue_all_b( %a) #0 { ; CHECK-LABEL: subr_i32_ptrue_all_b: -; CHECK: subr z0.s, z0.s, #1 -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: subr z0.s, z0.s, #1 // =0x1 +; CHECK-NEXT: ret %pg.b = tail call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) %pg.s = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg.b) %b = tail call @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) @@ -386,8 +387,9 @@ define @subr_i32_ptrue_all_b( %a) #0 { ; As subr_i32 but where pg is i16 based and thus compatible for i32. define @subr_i32_ptrue_all_h( %a) #0 { ; CHECK-LABEL: subr_i32_ptrue_all_h: -; CHECK: subr z0.s, z0.s, #1 -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: subr z0.s, z0.s, #1 // =0x1 +; CHECK-NEXT: ret %pg.h = tail call @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) %pg.b = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %pg.h) %pg.s = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg.b) @@ -402,10 +404,11 @@ define @subr_i32_ptrue_all_h( %a) #0 { ; thus inactive lanes are important and the immediate form cannot be used. define @subr_i32_ptrue_all_d( %a) #0 { ; CHECK-LABEL: subr_i32_ptrue_all_d: -; CHECK-DAG: ptrue [[PG:p[0-9]+]].d -; CHECK-DAG: mov [[DUP:z[0-9]+]].s, #1 -; CHECK-DAG: subr z0.s, [[PG]]/m, z0.s, [[DUP]].s -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: mov z1.s, #1 // =0x1 +; CHECK-NEXT: subr z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret %pg.d = tail call @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) %pg.b = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %pg.d) %pg.s = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg.b)