diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td index 78da8e3f7b260..f79f00f883aef 100644 --- a/llvm/lib/Target/AMDGPU/BUFInstructions.td +++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td @@ -360,6 +360,8 @@ class MUBUF_Real : let mayStore = ps.mayStore; let IsAtomicRet = ps.IsAtomicRet; let IsAtomicNoRet = ps.IsAtomicNoRet; + let VALU = ps.VALU; + let LGKM_CNT = ps.LGKM_CNT; bits<12> offset; bits<5> cpol; @@ -504,6 +506,7 @@ class MUBUF_Load_Pseudo .ret; + let VALU = isLds; } class MUBUF_Offset_Load_Pat : Pat < @@ -615,6 +619,7 @@ class MUBUF_Pseudo_Store_Lds (outs), (ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, CPol:$cpol, SWZ:$swz), " $srsrc, $soffset$offset lds$cpol$swz"> { + let LGKM_CNT = 1; let mayLoad = 0; let mayStore = 1; let maybeAtomic = 1; @@ -623,6 +628,7 @@ class MUBUF_Pseudo_Store_Lds let has_vaddr = 0; let has_tfe = 0; let lds = 1; + let VALU = 1; let Uses = [EXEC, M0]; let AsmMatchConverter = "cvtMubufLds"; diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td index 17a885d15abbd..fbebe8952ad5a 100644 --- a/llvm/lib/Target/AMDGPU/FLATInstructions.td +++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td @@ -99,6 +99,7 @@ class FLAT_Real op, FLAT_Pseudo ps> : let IsAtomicNoRet = ps.IsAtomicNoRet; let VM_CNT = ps.VM_CNT; let LGKM_CNT = ps.LGKM_CNT; + let VALU = ps.VALU; // encoding fields bits<8> vaddr; @@ -258,6 +259,7 @@ class FLAT_Global_Load_LDS_Pseudo : FLAT_Ps let mayStore = 1; let has_saddr = 1; let enabled_saddr = EnableSaddr; + let VALU = 1; let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", ""); let Uses = [M0, EXEC]; let SchedRW = [WriteVMEM, WriteLDS]; @@ -418,6 +420,7 @@ class FLAT_Scratch_Load_LDS_Pseudo