Skip to content

Commit ad21f26

Browse files
vedranmileticvedranmiletic
committed
[AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics
AMDGPU backend errors with "unsupported call to function" upon encountering a call to llvm.log{,10}.{f16,f32} intrinsics. This patch adds custom lowering to avoid that error on both R600 and SI. Reviewers: arsenm, jvesely Subscribers: tstellar Differential Revision: https://reviews.llvm.org/D29942 llvm-svn: 319025
1 parent 4c2c9c3 commit ad21f26

File tree

6 files changed

+352
-0
lines changed

6 files changed

+352
-0
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

+30
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,10 @@
1313
//
1414
//===----------------------------------------------------------------------===//
1515

16+
#define AMDGPU_LOG2E_F 1.44269504088896340735992468100189214f
17+
#define AMDGPU_LN2_F 0.693147180559945309417232121458176568f
18+
#define AMDGPU_LN10_F 2.30258509299404568401799145468436421f
19+
1620
#include "AMDGPUISelLowering.h"
1721
#include "AMDGPU.h"
1822
#include "AMDGPUCallLowering.h"
@@ -317,6 +321,14 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
317321
setOperationAction(ISD::FROUND, MVT::f32, Custom);
318322
setOperationAction(ISD::FROUND, MVT::f64, Custom);
319323

324+
setOperationAction(ISD::FLOG, MVT::f32, Custom);
325+
setOperationAction(ISD::FLOG10, MVT::f32, Custom);
326+
327+
if (Subtarget->has16BitInsts()) {
328+
setOperationAction(ISD::FLOG, MVT::f16, Custom);
329+
setOperationAction(ISD::FLOG10, MVT::f16, Custom);
330+
}
331+
320332
setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
321333
setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
322334

@@ -487,6 +499,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
487499
setOperationAction(ISD::FEXP2, VT, Expand);
488500
setOperationAction(ISD::FLOG2, VT, Expand);
489501
setOperationAction(ISD::FREM, VT, Expand);
502+
setOperationAction(ISD::FLOG, VT, Expand);
503+
setOperationAction(ISD::FLOG10, VT, Expand);
490504
setOperationAction(ISD::FPOW, VT, Expand);
491505
setOperationAction(ISD::FFLOOR, VT, Expand);
492506
setOperationAction(ISD::FTRUNC, VT, Expand);
@@ -1112,6 +1126,10 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
11121126
case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
11131127
case ISD::FROUND: return LowerFROUND(Op, DAG);
11141128
case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
1129+
case ISD::FLOG:
1130+
return LowerFLOG(Op, DAG, 1 / AMDGPU_LOG2E_F);
1131+
case ISD::FLOG10:
1132+
return LowerFLOG(Op, DAG, AMDGPU_LN2_F / AMDGPU_LN10_F);
11151133
case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
11161134
case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
11171135
case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG);
@@ -2160,6 +2178,18 @@ SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
21602178
return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
21612179
}
21622180

2181+
SDValue AMDGPUTargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG,
2182+
double Log2BaseInverted) const {
2183+
EVT VT = Op.getValueType();
2184+
2185+
SDLoc SL(Op);
2186+
SDValue Operand = Op.getOperand(0);
2187+
SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand);
2188+
SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT);
2189+
2190+
return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand);
2191+
}
2192+
21632193
static bool isCtlzOpc(unsigned Opc) {
21642194
return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
21652195
}

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

+2
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,8 @@ class AMDGPUTargetLowering : public TargetLowering {
5757
SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
5858
SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
5959
SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
60+
SDValue LowerFLOG(SDValue Op, SelectionDAG &Dag,
61+
double Log2BaseInverted) const;
6062

6163
SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
6264

‎llvm/test/CodeGen/AMDGPU/llvm.log.f16.ll

+71
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,71 @@
1+
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SIVI -check-prefix=FUNC %s
2+
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=SIVI -check-prefix=VIGFX9 -check-prefix=FUNC %s
3+
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=VIGFX9 -check-prefix=FUNC %s
4+
5+
declare half @llvm.log.f16(half %a)
6+
declare <2 x half> @llvm.log.v2f16(<2 x half> %a)
7+
8+
; FUNC-LABEL: {{^}}log_f16
9+
; SI: buffer_load_ushort v[[A_F16_0:[0-9]+]]
10+
; VI: flat_load_ushort v[[A_F16_0:[0-9]+]]
11+
; GFX9: global_load_ushort v[[A_F16_0:[0-9]+]]
12+
; SI: v_mov_b32_e32 v[[A_F32_1:[0-9]+]]
13+
; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
14+
; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
15+
; SI: v_mul_f32_e32 v[[R_F32_1:[0-9]+]], 0x3f317218, v[[R_F32_0]]
16+
; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_1]]
17+
; VIGFX9: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
18+
; VIGFX9: v_mul_f16_e32 v[[R_F16_0]], 0x398c, v[[R_F16_0]]
19+
; SI: buffer_store_short v[[R_F16_0]], v{{\[[0-9]+:[0-9]+\]}}
20+
; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
21+
; GFX9: global_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
22+
define void @log_f16(
23+
half addrspace(1)* %r,
24+
half addrspace(1)* %a) {
25+
entry:
26+
%a.val = load half, half addrspace(1)* %a
27+
%r.val = call half @llvm.log.f16(half %a.val)
28+
store half %r.val, half addrspace(1)* %r
29+
ret void
30+
}
31+
32+
; FUNC-LABEL: {{^}}log_v2f16
33+
; SI: buffer_load_dword v[[A_F16_0:[0-9]+]]
34+
; VI: flat_load_dword v[[A_F16_0:[0-9]+]]
35+
; GFX9: global_load_dword v[[A_F16_0:[0-9]+]]
36+
; SI: v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x3f317218
37+
; VIGFX9: v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x398c
38+
; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_0]]
39+
; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_F16_0]]
40+
; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
41+
; SI: v_log_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
42+
; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
43+
; SI: v_mul_f32_e32 v[[R_F32_6:[0-9]+]], v[[R_F32_1]], v[[A_F32_2]]
44+
; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_6]]
45+
; SI: v_mul_f32_e32 v[[R_F32_5:[0-9]+]], v[[R_F32_0]], v[[A_F32_2]]
46+
; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_5]]
47+
; GFX9: v_log_f16_e32 v[[R_F16_2:[0-9]+]], v[[A_F16_0]]
48+
; VIGFX9: v_log_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
49+
; VI: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
50+
; VI: v_mul_f16_sdwa v[[R_F16_2:[0-9]+]], v[[R_F16_1]], v[[A_F32_2]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
51+
; GFX9: v_mul_f16_e32 v[[R_F32_3:[0-9]+]], v[[R_F16_2]], v[[A_F32_2]]
52+
; VIGFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], v[[R_F16_0]], v[[A_F32_2]]
53+
; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_0]]
54+
; SI-NOT: v_and_b32_e32
55+
; SI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]]
56+
; VI-NOT: v_and_b32_e32
57+
; VI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_0]], v[[R_F16_2]]
58+
; GFX9: v_and_b32_e32 v[[R_F32_4:[0-9]+]], 0xffff, v[[R_F32_3]]
59+
; GFX9: v_lshl_or_b32 v[[R_F32_5:[0-9]+]], v[[R_F32_2]], 16, v[[R_F32_4]]
60+
; SI: buffer_store_dword v[[R_F32_5]]
61+
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
62+
; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
63+
define void @log_v2f16(
64+
<2 x half> addrspace(1)* %r,
65+
<2 x half> addrspace(1)* %a) {
66+
entry:
67+
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
68+
%r.val = call <2 x half> @llvm.log.v2f16(<2 x half> %a.val)
69+
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
70+
ret void
71+
}

‎llvm/test/CodeGen/AMDGPU/llvm.log.ll

+89
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
1+
; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
2+
; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 --check-prefix=FUNC %s
3+
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
4+
; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
5+
6+
; FUNC-LABEL: {{^}}test:
7+
; EG: LOG_IEEE
8+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
9+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
10+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
11+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
12+
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
13+
; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3f317218, v{{[0-9]+}}
14+
define void @test(float addrspace(1)* %out, float %in) {
15+
entry:
16+
%res = call float @llvm.log.f32(float %in)
17+
store float %res, float addrspace(1)* %out
18+
ret void
19+
}
20+
21+
; FUNC-LABEL: {{^}}testv2:
22+
; EG: LOG_IEEE
23+
; EG: LOG_IEEE
24+
; FIXME: We should be able to merge these packets together on Cayman so we
25+
; have a maximum of 4 instructions.
26+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
27+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
28+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
29+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
30+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
31+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
32+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
33+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
34+
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
35+
; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218
36+
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
37+
; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218
38+
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
39+
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
40+
define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
41+
entry:
42+
%res = call <2 x float> @llvm.log.v2f32(<2 x float> %in)
43+
store <2 x float> %res, <2 x float> addrspace(1)* %out
44+
ret void
45+
}
46+
47+
; FUNC-LABEL: {{^}}testv4:
48+
; EG: LOG_IEEE
49+
; EG: LOG_IEEE
50+
; EG: LOG_IEEE
51+
; EG: LOG_IEEE
52+
; FIXME: We should be able to merge these packets together on Cayman so we
53+
; have a maximum of 4 instructions.
54+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
55+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
56+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
57+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
58+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
59+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
60+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
61+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
62+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
63+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
64+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
65+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
66+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
67+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
68+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
69+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
70+
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
71+
; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218
72+
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
73+
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
74+
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
75+
; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218
76+
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
77+
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
78+
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
79+
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
80+
define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
81+
entry:
82+
%res = call <4 x float> @llvm.log.v4f32(<4 x float> %in)
83+
store <4 x float> %res, <4 x float> addrspace(1)* %out
84+
ret void
85+
}
86+
87+
declare float @llvm.log.f32(float) readnone
88+
declare <2 x float> @llvm.log.v2f32(<2 x float>) readnone
89+
declare <4 x float> @llvm.log.v4f32(<4 x float>) readnone

‎llvm/test/CodeGen/AMDGPU/llvm.log10.f16.ll

+71
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,71 @@
1+
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SIVI -check-prefix=FUNC %s
2+
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=SIVI -check-prefix=VIGFX9 -check-prefix=FUNC %s
3+
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=VIGFX9 -check-prefix=FUNC %s
4+
5+
declare half @llvm.log10.f16(half %a)
6+
declare <2 x half> @llvm.log10.v2f16(<2 x half> %a)
7+
8+
; GCN-LABEL: {{^}}log10_f16
9+
; SI: buffer_load_ushort v[[A_F16_0:[0-9]+]]
10+
; VI: flat_load_ushort v[[A_F16_0:[0-9]+]]
11+
; GFX9: global_load_ushort v[[A_F16_0:[0-9]+]]
12+
; SI: v_mov_b32_e32 v[[A_F32_1:[0-9]+]]
13+
; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
14+
; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
15+
; SI: v_mul_f32_e32 v[[R_F32_1:[0-9]+]], 0x3e9a209a, v[[R_F32_0]]
16+
; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_1]]
17+
; VIGFX9: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
18+
; VIGFX9: v_mul_f16_e32 v[[R_F16_0]], 0x34d1, v[[R_F16_0]]
19+
; SI: buffer_store_short v[[R_F16_0]], v{{\[[0-9]+:[0-9]+\]}}
20+
; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
21+
; GFX9: global_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
22+
define void @log10_f16(
23+
half addrspace(1)* %r,
24+
half addrspace(1)* %a) {
25+
entry:
26+
%a.val = load half, half addrspace(1)* %a
27+
%r.val = call half @llvm.log10.f16(half %a.val)
28+
store half %r.val, half addrspace(1)* %r
29+
ret void
30+
}
31+
32+
; GCN-LABEL: {{^}}log10_v2f16
33+
; SI: buffer_load_dword v[[A_F16_0:[0-9]+]]
34+
; VI: flat_load_dword v[[A_F16_0:[0-9]+]]
35+
; GFX9: global_load_dword v[[A_F16_0:[0-9]+]]
36+
; SI: v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x3e9a209a
37+
; VIGFX9: v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x34d1
38+
; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_0]]
39+
; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_F16_0]]
40+
; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
41+
; SI: v_log_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
42+
; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
43+
; SI: v_mul_f32_e32 v[[R_F32_6:[0-9]+]], v[[R_F32_1]], v[[A_F32_2]]
44+
; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_6]]
45+
; SI: v_mul_f32_e32 v[[R_F32_5:[0-9]+]], v[[R_F32_0]], v[[A_F32_2]]
46+
; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_5]]
47+
; GFX9: v_log_f16_e32 v[[R_F16_2:[0-9]+]], v[[A_F16_0]]
48+
; VIGFX9: v_log_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
49+
; VI: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
50+
; VI: v_mul_f16_sdwa v[[R_F16_2:[0-9]+]], v[[R_F16_1]], v[[A_F32_2]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
51+
; GFX9: v_mul_f16_e32 v[[R_F32_3:[0-9]+]], v[[R_F16_2]], v[[A_F32_2]]
52+
; VIGFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], v[[R_F16_0]], v[[A_F32_2]]
53+
; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_0]]
54+
; SI-NOT: v_and_b32_e32
55+
; SI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]]
56+
; VI-NOT: v_and_b32_e32
57+
; VI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_0]], v[[R_F16_2]]
58+
; GFX9: v_and_b32_e32 v[[R_F32_4:[0-9]+]], 0xffff, v[[R_F32_3]]
59+
; GFX9: v_lshl_or_b32 v[[R_F32_5:[0-9]+]], v[[R_F32_2]], 16, v[[R_F32_4]]
60+
; SI: buffer_store_dword v[[R_F32_5]]
61+
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
62+
; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
63+
define void @log10_v2f16(
64+
<2 x half> addrspace(1)* %r,
65+
<2 x half> addrspace(1)* %a) {
66+
entry:
67+
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
68+
%r.val = call <2 x half> @llvm.log10.v2f16(<2 x half> %a.val)
69+
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
70+
ret void
71+
}

‎llvm/test/CodeGen/AMDGPU/llvm.log10.ll

+89
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
1+
; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
2+
; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 -check-prefix=FUNC %s
3+
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
4+
; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
5+
6+
; FUNC-LABEL: {{^}}test:
7+
; EG: LOG_IEEE
8+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
9+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
10+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
11+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
12+
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
13+
; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3e9a209a, v{{[0-9]+}}
14+
define void @test(float addrspace(1)* %out, float %in) {
15+
entry:
16+
%res = call float @llvm.log10.f32(float %in)
17+
store float %res, float addrspace(1)* %out
18+
ret void
19+
}
20+
21+
; FUNC-LABEL: {{^}}testv2:
22+
; EG: LOG_IEEE
23+
; EG: LOG_IEEE
24+
; FIXME: We should be able to merge these packets together on Cayman so we
25+
; have a maximum of 4 instructions.
26+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
27+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
28+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
29+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
30+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
31+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
32+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
33+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
34+
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
35+
; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
36+
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
37+
; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
38+
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
39+
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
40+
define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
41+
entry:
42+
%res = call <2 x float> @llvm.log10.v2f32(<2 x float> %in)
43+
store <2 x float> %res, <2 x float> addrspace(1)* %out
44+
ret void
45+
}
46+
47+
; FUNC-LABEL: {{^}}testv4:
48+
; EG: LOG_IEEE
49+
; EG: LOG_IEEE
50+
; EG: LOG_IEEE
51+
; EG: LOG_IEEE
52+
; FIXME: We should be able to merge these packets together on Cayman so we
53+
; have a maximum of 4 instructions.
54+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
55+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
56+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
57+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
58+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
59+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
60+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
61+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
62+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
63+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
64+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
65+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
66+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
67+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
68+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
69+
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
70+
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
71+
; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
72+
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
73+
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
74+
; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
75+
; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
76+
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
77+
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
78+
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
79+
; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
80+
define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
81+
entry:
82+
%res = call <4 x float> @llvm.log10.v4f32(<4 x float> %in)
83+
store <4 x float> %res, <4 x float> addrspace(1)* %out
84+
ret void
85+
}
86+
87+
declare float @llvm.log10.f32(float) readnone
88+
declare <2 x float> @llvm.log10.v2f32(<2 x float>) readnone
89+
declare <4 x float> @llvm.log10.v4f32(<4 x float>) readnone

0 commit comments

Comments
 (0)