From ad73ce318ef901545fa82d57a609c71af787e1e1 Mon Sep 17 00:00:00 2001 From: Zongwei Lan Date: Thu, 26 May 2022 11:22:41 -0700 Subject: [PATCH] [Target] use getSubtarget<> instead of static_cast<>(getSubtarget()) Differential Revision: https://reviews.llvm.org/D125391 --- llvm/include/llvm/CodeGen/SelectionDAG.h | 3 ++ llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 2 +- .../Target/AArch64/AArch64FalkorHWPFFix.cpp | 2 +- llvm/lib/Target/AArch64/AArch64FastISel.cpp | 3 +- .../Target/AArch64/AArch64ISelLowering.cpp | 28 +++++++------------ .../AArch64/AArch64LoadStoreOptimizer.cpp | 2 +- .../GISel/AArch64InstructionSelector.cpp | 3 +- llvm/lib/Target/ARM/ARMBlockPlacement.cpp | 2 +- llvm/lib/Target/ARM/ARMConstantIslandPass.cpp | 2 +- llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 2 +- llvm/lib/Target/ARM/ARMFastISel.cpp | 5 ++-- llvm/lib/Target/ARM/ARMFrameLowering.cpp | 5 ++-- llvm/lib/Target/ARM/ARMISelLowering.cpp | 8 ++---- llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 4 +-- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 2 +- .../ARM/MVETPAndVPTOptimisationsPass.cpp | 3 +- llvm/lib/Target/ARM/MVEVPTBlockPass.cpp | 3 +- llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp | 3 +- llvm/lib/Target/ARM/Thumb2SizeReduction.cpp | 2 +- .../Target/CSKY/CSKYConstantIslandPass.cpp | 2 +- .../Target/Hexagon/HexagonISelDAGToDAGHVX.cpp | 2 +- .../Target/Hexagon/HexagonISelLowering.cpp | 7 ++--- llvm/lib/Target/Hexagon/HexagonPatternsHVX.td | 2 +- .../lib/Target/M68k/M68kCollapseMOVEMPass.cpp | 2 +- llvm/lib/Target/M68k/M68kExpandPseudo.cpp | 2 +- llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp | 2 +- .../Target/Mips/MicroMipsSizeReduction.cpp | 2 +- llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp | 2 +- llvm/lib/Target/Mips/MipsBranchExpansion.cpp | 2 +- llvm/lib/Target/Mips/MipsCallLowering.cpp | 3 +- .../Target/Mips/MipsConstantIslandPass.cpp | 2 +- llvm/lib/Target/Mips/MipsExpandPseudo.cpp | 2 +- llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp | 2 +- llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 3 +- llvm/lib/Target/Mips/MipsMachineFunction.cpp | 2 +- llvm/lib/Target/Mips/MipsOptimizePICCall.cpp | 2 +- .../Target/Mips/MipsPreLegalizerCombiner.cpp | 3 +- llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 5 ++-- llvm/lib/Target/Mips/MipsSEFrameLowering.cpp | 2 +- llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 2 +- llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 2 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 9 ++---- llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp | 3 +- llvm/lib/Target/X86/X86CallingConv.cpp | 2 +- llvm/lib/Target/X86/X86ExpandPseudo.cpp | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 6 ++-- 46 files changed, 68 insertions(+), 93 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index 6d5f6c8b50c3e..82eda0a917783 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -452,6 +452,9 @@ class SelectionDAG { const DataLayout &getDataLayout() const { return MF->getDataLayout(); } const TargetMachine &getTarget() const { return TM; } const TargetSubtargetInfo &getSubtarget() const { return MF->getSubtarget(); } + template const STC &getSubtarget() const { + return MF->getSubtarget(); + } const TargetLowering &getTargetLoweringInfo() const { return *TLI; } const TargetLibraryInfo &getLibInfo() const { return *LibInfo; } const SelectionDAGTargetInfo &getSelectionDAGInfo() const { return *TSI; } diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp index eadc792be3d08..58e3cfd1d00a1 100644 --- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp +++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -132,7 +132,7 @@ class AArch64AsmPrinter : public AsmPrinter { bool runOnMachineFunction(MachineFunction &MF) override { AArch64FI = MF.getInfo(); - STI = static_cast(&MF.getSubtarget()); + STI = &MF.getSubtarget(); SetupMachineFunction(MF); diff --git a/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp b/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp index 793663ef97d7e..6de3741254669 100644 --- a/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp +++ b/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp @@ -813,7 +813,7 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineFunction &Fn) { } bool FalkorHWPFFix::runOnMachineFunction(MachineFunction &Fn) { - auto &ST = static_cast(Fn.getSubtarget()); + auto &ST = Fn.getSubtarget(); if (ST.getProcFamily() != AArch64Subtarget::Falkor) return false; diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index dc5e6807945d7..49fffa01a974d 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -283,8 +283,7 @@ class AArch64FastISel final : public FastISel { explicit AArch64FastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) : FastISel(FuncInfo, LibInfo, /*SkipTargetIndependentISel=*/true) { - Subtarget = - &static_cast(FuncInfo.MF->getSubtarget()); + Subtarget = &FuncInfo.MF->getSubtarget(); Context = &FuncInfo.Fn->getContext(); } diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 3aaadc767dbdc..e31a58da08313 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -2566,8 +2566,7 @@ static SDValue emitStrictFPComparison(SDValue LHS, SDValue RHS, const SDLoc &dl, EVT VT = LHS.getValueType(); assert(VT != MVT::f128); - const bool FullFP16 = - static_cast(DAG.getSubtarget()).hasFullFP16(); + const bool FullFP16 = DAG.getSubtarget().hasFullFP16(); if (VT == MVT::f16 && !FullFP16) { LHS = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {MVT::f32, MVT::Other}, @@ -2585,8 +2584,7 @@ static SDValue emitStrictFPComparison(SDValue LHS, SDValue RHS, const SDLoc &dl, static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) { EVT VT = LHS.getValueType(); - const bool FullFP16 = - static_cast(DAG.getSubtarget()).hasFullFP16(); + const bool FullFP16 = DAG.getSubtarget().hasFullFP16(); if (VT.isFloatingPoint()) { assert(VT != MVT::f128); @@ -2694,8 +2692,7 @@ static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS, AArch64CC::CondCode OutCC, const SDLoc &DL, SelectionDAG &DAG) { unsigned Opcode = 0; - const bool FullFP16 = - static_cast(DAG.getSubtarget()).hasFullFP16(); + const bool FullFP16 = DAG.getSubtarget().hasFullFP16(); if (LHS.getValueType().isFloatingPoint()) { assert(LHS.getValueType() != MVT::f128); @@ -11865,8 +11862,7 @@ SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op, return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType()); } - const bool FullFP16 = - static_cast(DAG.getSubtarget()).hasFullFP16(); + const bool FullFP16 = DAG.getSubtarget().hasFullFP16(); // Make v4f16 (only) fcmp operations utilise vector instructions // v8f16 support will be a litle more complicated @@ -12000,7 +11996,7 @@ SDValue AArch64TargetLowering::LowerVECREDUCE(SDValue Op, SDValue AArch64TargetLowering::LowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const { - auto &Subtarget = static_cast(DAG.getSubtarget()); + auto &Subtarget = DAG.getSubtarget(); if (!Subtarget.hasLSE() && !Subtarget.outlineAtomics()) return SDValue(); @@ -12017,7 +12013,7 @@ SDValue AArch64TargetLowering::LowerATOMIC_LOAD_SUB(SDValue Op, SDValue AArch64TargetLowering::LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const { - auto &Subtarget = static_cast(DAG.getSubtarget()); + auto &Subtarget = DAG.getSubtarget(); if (!Subtarget.hasLSE() && !Subtarget.outlineAtomics()) return SDValue(); @@ -14797,8 +14793,7 @@ performExtractVectorEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, ConstantSDNode *ConstantN1 = dyn_cast(N1); EVT VT = N->getValueType(0); - const bool FullFP16 = - static_cast(DAG.getSubtarget()).hasFullFP16(); + const bool FullFP16 = DAG.getSubtarget().hasFullFP16(); bool IsStrict = N0->isStrictFPOpcode(); // Rewrite for pairwise fadd pattern @@ -16009,8 +16004,7 @@ static bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) { // If we're compiling for a specific vector-length, we can check if the // pattern's VL equals that of the scalable vector at runtime. if (N.getOpcode() == AArch64ISD::PTRUE) { - const auto &Subtarget = - static_cast(DAG.getSubtarget()); + const auto &Subtarget = DAG.getSubtarget(); unsigned MinSVESize = Subtarget.getMinSVEVectorSizeInBits(); unsigned MaxSVESize = Subtarget.getMaxSVEVectorSizeInBits(); if (MaxSVESize && MinSVESize == MaxSVESize) { @@ -17231,8 +17225,7 @@ static bool findMoreOptimalIndexType(const MaskedGatherScatterSDNode *N, Stride > std::numeric_limits::max()) return Changed; - const auto &Subtarget = - static_cast(DAG.getSubtarget()); + const auto &Subtarget = DAG.getSubtarget(); unsigned MaxVScale = Subtarget.getMaxSVEVectorSizeInBits() / AArch64::SVEBitsPerBlock; int64_t LastElementOffset = @@ -20219,8 +20212,7 @@ static SDValue getPredicateForFixedLengthVector(SelectionDAG &DAG, SDLoc &DL, // For vectors that are exactly getMaxSVEVectorSizeInBits big, we can use // AArch64SVEPredPattern::all, which can enable the use of unpredicated // variants of instructions when available. - const auto &Subtarget = - static_cast(DAG.getSubtarget()); + const auto &Subtarget = DAG.getSubtarget(); unsigned MinSVESize = Subtarget.getMinSVEVectorSizeInBits(); unsigned MaxSVESize = Subtarget.getMaxSVEVectorSizeInBits(); if (MaxSVESize && MinSVESize == MaxSVESize && diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp index 02795f8310fc2..502b6321d5bb0 100644 --- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -2308,7 +2308,7 @@ bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) { if (skipFunction(Fn.getFunction())) return false; - Subtarget = &static_cast(Fn.getSubtarget()); + Subtarget = &Fn.getSubtarget(); TII = static_cast(Subtarget->getInstrInfo()); TRI = Subtarget->getRegisterInfo(); AA = &getAnalysis().getAAResults(); diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp index 156c3a8c06e91..539a1b85a4e37 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -2335,8 +2335,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { MachineFunction &MF = *MBB.getParent(); MachineRegisterInfo &MRI = MF.getRegInfo(); - const AArch64Subtarget *Subtarget = - &static_cast(MF.getSubtarget()); + const AArch64Subtarget *Subtarget = &MF.getSubtarget(); if (Subtarget->requiresStrictAlign()) { // We don't support this feature yet. LLVM_DEBUG(dbgs() << "AArch64 GISel does not support strict-align yet\n"); diff --git a/llvm/lib/Target/ARM/ARMBlockPlacement.cpp b/llvm/lib/Target/ARM/ARMBlockPlacement.cpp index e05d88218ba90..b2d291bbe7ffd 100644 --- a/llvm/lib/Target/ARM/ARMBlockPlacement.cpp +++ b/llvm/lib/Target/ARM/ARMBlockPlacement.cpp @@ -213,7 +213,7 @@ bool ARMBlockPlacement::processPostOrderLoops(MachineLoop *ML) { bool ARMBlockPlacement::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction())) return false; - const ARMSubtarget &ST = static_cast(MF.getSubtarget()); + const ARMSubtarget &ST = MF.getSubtarget(); if (!ST.hasLOB()) return false; LLVM_DEBUG(dbgs() << DEBUG_PREFIX << "Running on " << MF.getName() << "\n"); diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp index a2a4f1f3bdfde..d77c3afd05e57 100644 --- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -396,7 +396,7 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) { << MCP->getConstants().size() << " CP entries, aligned to " << MCP->getConstantPoolAlign().value() << " bytes *****\n"); - STI = &static_cast(MF->getSubtarget()); + STI = &MF->getSubtarget(); TII = STI->getInstrInfo(); isPositionIndependentOrROPI = STI->getTargetLowering()->isPositionIndependent() || STI->isROPI(); diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 2f083561bbd40..61fe27095e4f6 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -3132,7 +3132,7 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { } bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { - STI = &static_cast(MF.getSubtarget()); + STI = &MF.getSubtarget(); TII = STI->getInstrInfo(); TRI = STI->getRegisterInfo(); AFI = MF.getInfo(); diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index 5d94b99d4c5d9..1f9a4ad687f14 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -122,8 +122,7 @@ class ARMFastISel final : public FastISel { explicit ARMFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) : FastISel(funcInfo, libInfo), - Subtarget( - &static_cast(funcInfo.MF->getSubtarget())), + Subtarget(&funcInfo.MF->getSubtarget()), M(const_cast(*funcInfo.Fn->getParent())), TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) { @@ -156,7 +155,7 @@ class ARMFastISel final : public FastISel { const LoadInst *LI) override; bool fastLowerArguments() override; - #include "ARMGenFastISel.inc" +#include "ARMGenFastISel.inc" // Instruction selection routines. diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index b2765b2370ff7..f3d95f057e275 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -392,8 +392,7 @@ static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI, const DebugLoc &DL, const unsigned Reg, const Align Alignment, const bool MustBeSingleInstruction) { - const ARMSubtarget &AST = - static_cast(MF.getSubtarget()); + const ARMSubtarget &AST = MF.getSubtarget(); const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops(); const unsigned AlignMask = Alignment.value() - 1U; const unsigned NrBitsToZero = Log2(Alignment); @@ -1768,7 +1767,7 @@ checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) { return; // We are planning to use NEON instructions vst1 / vld1. - if (!static_cast(MF.getSubtarget()).hasNEON()) + if (!MF.getSubtarget().hasNEON()) return; // Don't bother if the default stack alignment is sufficiently high. diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index d3e1b92c3b957..eb1a0c55ca9b7 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -5807,8 +5807,7 @@ static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) { return DAG.UnrollVectorOp(Op.getNode()); } - const bool HasFullFP16 = - static_cast(DAG.getSubtarget()).hasFullFP16(); + const bool HasFullFP16 = DAG.getSubtarget().hasFullFP16(); EVT NewTy; const EVT OpTy = Op.getOperand(0).getValueType(); @@ -5918,8 +5917,7 @@ static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) { Op.getOperand(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"); - const bool HasFullFP16 = - static_cast(DAG.getSubtarget()).hasFullFP16(); + const bool HasFullFP16 = DAG.getSubtarget().hasFullFP16(); EVT DestVecType; if (VT == MVT::v4f32) @@ -9882,7 +9880,7 @@ ARMTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor, if (N->getOpcode() != ISD::SDIV) return SDValue(); - const auto &ST = static_cast(DAG.getSubtarget()); + const auto &ST = DAG.getSubtarget(); const bool MinSize = ST.hasMinSize(); const bool HasDivide = ST.isThumb() ? ST.hasDivideInThumbMode() : ST.hasDivideInARMMode(); diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index fff286b25413b..fb9d6863aca74 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -2110,7 +2110,7 @@ bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) { return false; MF = &Fn; - STI = &static_cast(Fn.getSubtarget()); + STI = &Fn.getSubtarget(); TL = STI->getTargetLowering(); AFI = Fn.getInfo(); TII = STI->getInstrInfo(); @@ -2201,7 +2201,7 @@ bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) { return false; TD = &Fn.getDataLayout(); - STI = &static_cast(Fn.getSubtarget()); + STI = &Fn.getSubtarget(); TII = STI->getInstrInfo(); TRI = STI->getRegisterInfo(); MRI = &Fn.getRegInfo(); diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp index 83ef6554ceb2d..aa739db44da2c 100644 --- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp +++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -1299,7 +1299,7 @@ bool LowOverheadLoop::ValidateMVEInst(MachineInstr *MI) { } bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &mf) { - const ARMSubtarget &ST = static_cast(mf.getSubtarget()); + const ARMSubtarget &ST = mf.getSubtarget(); if (!ST.hasLOB()) return false; diff --git a/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp b/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp index 92c324d58c254..6bad9d61238e7 100644 --- a/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp +++ b/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp @@ -1052,8 +1052,7 @@ bool MVETPAndVPTOptimisations::HintDoLoopStartReg(MachineBasicBlock &MBB) { } bool MVETPAndVPTOptimisations::runOnMachineFunction(MachineFunction &Fn) { - const ARMSubtarget &STI = - static_cast(Fn.getSubtarget()); + const ARMSubtarget &STI = Fn.getSubtarget(); if (!STI.isThumb2() || !STI.hasLOB()) return false; diff --git a/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp b/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp index c7f451cba14ff..d6d43b9143d61 100644 --- a/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp +++ b/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp @@ -312,8 +312,7 @@ bool MVEVPTBlock::InsertVPTBlocks(MachineBasicBlock &Block) { } bool MVEVPTBlock::runOnMachineFunction(MachineFunction &Fn) { - const ARMSubtarget &STI = - static_cast(Fn.getSubtarget()); + const ARMSubtarget &STI = Fn.getSubtarget(); if (!STI.isThumb2() || !STI.hasMVEIntegerOps()) return false; diff --git a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp index c979a26303abb..155555152ced1 100644 --- a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp +++ b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp @@ -284,8 +284,7 @@ bool Thumb2ITBlock::InsertITInstructions(MachineBasicBlock &MBB) { } bool Thumb2ITBlock::runOnMachineFunction(MachineFunction &Fn) { - const ARMSubtarget &STI = - static_cast(Fn.getSubtarget()); + const ARMSubtarget &STI = Fn.getSubtarget(); if (!STI.isThumb2()) return false; AFI = Fn.getInfo(); diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp index 1cc5422523f17..cdbcc9527e156 100644 --- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -1130,7 +1130,7 @@ bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) { if (PredicateFtor && !PredicateFtor(MF.getFunction())) return false; - STI = &static_cast(MF.getSubtarget()); + STI = &MF.getSubtarget(); if (STI->isThumb1Only() || STI->prefers32BitThumb()) return false; diff --git a/llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp b/llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp index 0aad16c15353d..5d7241258543b 100644 --- a/llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp +++ b/llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp @@ -287,7 +287,7 @@ LLVM_DUMP_METHOD void CSKYConstantIslands::dumpBBs() { bool CSKYConstantIslands::runOnMachineFunction(MachineFunction &Mf) { MF = &Mf; MCP = Mf.getConstantPool(); - STI = &static_cast(Mf.getSubtarget()); + STI = &Mf.getSubtarget(); LLVM_DEBUG(dbgs() << "***** CSKYConstantIslands: " << MCP->getConstants().size() << " CP entries, aligned to " diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp index 0a6dd727eb82d..0848d30e7403e 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp @@ -801,7 +801,7 @@ static const HexagonTargetLowering &getHexagonLowering(SelectionDAG &G) { return static_cast(G.getTargetLoweringInfo()); } static const HexagonSubtarget &getHexagonSubtarget(SelectionDAG &G) { - return static_cast(G.getSubtarget()); + return G.getSubtarget(); } namespace llvm { diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 0cbda5786897e..11dd8e2c2b674 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -1396,10 +1396,9 @@ HexagonTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag); InFlag = Chain.getValue(1); - unsigned Flags = - static_cast(DAG.getSubtarget()).useLongCalls() - ? HexagonII::MO_GDPLT | HexagonII::HMOTF_ConstExtended - : HexagonII::MO_GDPLT; + unsigned Flags = DAG.getSubtarget().useLongCalls() + ? HexagonII::MO_GDPLT | HexagonII::HMOTF_ConstExtended + : HexagonII::MO_GDPLT; return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT, Hexagon::R0, Flags); diff --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td index 6769548d6cbc2..6fb1313667a95 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td +++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td @@ -37,7 +37,7 @@ def SDTHexagonVINSERTW0: SDTypeProfile<1, 2, def HexagonVINSERTW0: SDNode<"HexagonISD::VINSERTW0", SDTHexagonVINSERTW0>; def HwLen2: SDNodeXForm(CurDAG->getSubtarget()); + const auto &ST = CurDAG->getSubtarget(); return CurDAG->getTargetConstant(ST.getVectorLength()/2, SDLoc(N), MVT::i32); }]>; diff --git a/llvm/lib/Target/M68k/M68kCollapseMOVEMPass.cpp b/llvm/lib/Target/M68k/M68kCollapseMOVEMPass.cpp index 7f0c0dd92dbb7..cbd69f24666ee 100644 --- a/llvm/lib/Target/M68k/M68kCollapseMOVEMPass.cpp +++ b/llvm/lib/Target/M68k/M68kCollapseMOVEMPass.cpp @@ -231,7 +231,7 @@ class M68kCollapseMOVEM : public MachineFunctionPass { } bool runOnMachineFunction(MachineFunction &MF) override { - STI = &static_cast(MF.getSubtarget()); + STI = &MF.getSubtarget(); TII = STI->getInstrInfo(); TRI = STI->getRegisterInfo(); MFI = MF.getInfo(); diff --git a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp index acfa30f28c2bb..51a148f5aa04a 100644 --- a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp +++ b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp @@ -302,7 +302,7 @@ bool M68kExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { } bool M68kExpandPseudo::runOnMachineFunction(MachineFunction &MF) { - STI = &static_cast(MF.getSubtarget()); + STI = &MF.getSubtarget(); TII = STI->getInstrInfo(); TRI = STI->getRegisterInfo(); MFI = MF.getInfo(); diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp index 9ef97b96ea9a9..b75fbc3c7f220 100644 --- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp +++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp @@ -312,7 +312,7 @@ class M68kDAGToDAGISel : public SelectionDAGISel { } // namespace bool M68kDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { - Subtarget = &static_cast(MF.getSubtarget()); + Subtarget = &MF.getSubtarget(); return SelectionDAGISel::runOnMachineFunction(MF); } diff --git a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp index 55d3c59cbf034..b0de8dacf6913 100644 --- a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp +++ b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp @@ -774,7 +774,7 @@ bool MicroMipsSizeReduce::ReplaceInstruction(MachineInstr *MI, bool MicroMipsSizeReduce::runOnMachineFunction(MachineFunction &MF) { - Subtarget = &static_cast(MF.getSubtarget()); + Subtarget = &MF.getSubtarget(); // TODO: Add support for the subtarget microMIPS32R6. if (!Subtarget->inMicroMipsMode() || !Subtarget->hasMips32r2() || diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp index 50147c019bfd5..ce04124a7b00b 100644 --- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp @@ -35,7 +35,7 @@ using namespace llvm; #define DEBUG_TYPE "mips-isel" bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { - Subtarget = &static_cast(MF.getSubtarget()); + Subtarget = &MF.getSubtarget(); if (!Subtarget->inMips16Mode()) return false; return MipsDAGToDAGISel::runOnMachineFunction(MF); diff --git a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp index 797547f998617..a4fa0792a998d 100644 --- a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp +++ b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp @@ -879,7 +879,7 @@ bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { const TargetMachine &TM = MF.getTarget(); IsPIC = TM.isPositionIndependent(); ABI = static_cast(TM).getABI(); - STI = &static_cast(MF.getSubtarget()); + STI = &MF.getSubtarget(); TII = static_cast(STI->getInstrInfo()); if (IsPIC && ABI.IsO32() && diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp index 409c24d86e650..3c1c2bcd7a1b9 100644 --- a/llvm/lib/Target/Mips/MipsCallLowering.cpp +++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp @@ -541,8 +541,7 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, } MIRBuilder.insertInstr(MIB); if (MIB->getOpcode() == Mips::JALRPseudo) { - const MipsSubtarget &STI = - static_cast(MIRBuilder.getMF().getSubtarget()); + const MipsSubtarget &STI = MIRBuilder.getMF().getSubtarget(); MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), *STI.getRegBankInfo()); } diff --git a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp index 73691e0db3d41..0341af0caac46 100644 --- a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp +++ b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -436,7 +436,7 @@ bool MipsConstantIslands::runOnMachineFunction(MachineFunction &mf) { // FIXME: MF = &mf; MCP = mf.getConstantPool(); - STI = &static_cast(mf.getSubtarget()); + STI = &mf.getSubtarget(); LLVM_DEBUG(dbgs() << "constant island machine function " << "\n"); if (!STI->inMips16Mode() || !MipsSubtarget::useConstantIslands()) { diff --git a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp index 31180d5a23ef0..d242083f958b8 100644 --- a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp +++ b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp @@ -892,7 +892,7 @@ bool MipsExpandPseudo::expandMBB(MachineBasicBlock &MBB) { } bool MipsExpandPseudo::runOnMachineFunction(MachineFunction &MF) { - STI = &static_cast(MF.getSubtarget()); + STI = &MF.getSubtarget(); TII = STI->getInstrInfo(); bool Modified = false; diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp index d88696525e9e5..c4bb3d90b4d54 100644 --- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -54,7 +54,7 @@ void MipsDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { } bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { - Subtarget = &static_cast(MF.getSubtarget()); + Subtarget = &MF.getSubtarget(); bool Ret = SelectionDAGISel::runOnMachineFunction(MF); processFunctionAfterISel(MF); diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp index 98f98b5463c44..35b0fe218d8f4 100644 --- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp +++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -503,8 +503,7 @@ static bool MSA2OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode, bool MipsLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const { MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; - const MipsSubtarget &ST = - static_cast(MI.getMF()->getSubtarget()); + const MipsSubtarget &ST = MI.getMF()->getSubtarget(); const MipsInstrInfo &TII = *ST.getInstrInfo(); const MipsRegisterInfo &TRI = *ST.getRegisterInfo(); const RegisterBankInfo &RBI = *ST.getRegBankInfo(); diff --git a/llvm/lib/Target/Mips/MipsMachineFunction.cpp b/llvm/lib/Target/Mips/MipsMachineFunction.cpp index 411a26e42713e..ba1716a7c0b3e 100644 --- a/llvm/lib/Target/Mips/MipsMachineFunction.cpp +++ b/llvm/lib/Target/Mips/MipsMachineFunction.cpp @@ -29,7 +29,7 @@ bool MipsFunctionInfo::globalBaseRegSet() const { } static const TargetRegisterClass &getGlobalBaseRegClass(MachineFunction &MF) { - auto &STI = static_cast(MF.getSubtarget()); + auto &STI = MF.getSubtarget(); auto &TM = static_cast(MF.getTarget()); if (STI.inMips16Mode()) diff --git a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp index 1b5c46c1edba0..204c42ae5e5f5 100644 --- a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp +++ b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp @@ -194,7 +194,7 @@ void MBBInfo::postVisit() { // OptimizePICCall methods. bool OptimizePICCall::runOnMachineFunction(MachineFunction &F) { - if (static_cast(F.getSubtarget()).inMips16Mode()) + if (F.getSubtarget().inMips16Mode()) return false; // Do a pre-order traversal of the dominator tree. diff --git a/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp b/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp index e2074e24c44d8..cb6d53ec0a124 100644 --- a/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp +++ b/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp @@ -51,8 +51,7 @@ bool MipsPreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer, // Don't attempt to combine non power of 2 loads or unaligned loads when // subtarget doesn't support them. auto MMO = *MI.memoperands_begin(); - const MipsSubtarget &STI = - static_cast(MI.getMF()->getSubtarget()); + const MipsSubtarget &STI = MI.getMF()->getSubtarget(); if (!isPowerOf2_64(MMO->getSize())) return false; bool isUnaligned = MMO->getAlign() < MMO->getSize(); diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp index 2cb59e6960313..2544d9d9b76d9 100644 --- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -153,8 +153,7 @@ static bool isGprbTwoInstrUnalignedLoadOrStore(const MachineInstr *MI) { if (MI->getOpcode() == TargetOpcode::G_LOAD || MI->getOpcode() == TargetOpcode::G_STORE) { auto MMO = *MI->memoperands_begin(); - const MipsSubtarget &STI = - static_cast(MI->getMF()->getSubtarget()); + const MipsSubtarget &STI = MI->getMF()->getSubtarget(); if (MMO->getSize() == 4 && (!STI.systemSupportsUnalignedAccess() && MMO->getAlign() < MMO->getSize())) return true; @@ -398,7 +397,7 @@ void MipsRegisterBankInfo::TypeInfoForMF::cleanupIfNewFunction( static const MipsRegisterBankInfo::ValueMapping * getMSAMapping(const MachineFunction &MF) { - assert(static_cast(MF.getSubtarget()).hasMSA() && + assert(MF.getSubtarget().hasMSA() && "MSA mapping not available on target without MSA."); return &Mips::ValueMappings[Mips::MSAIdx]; } diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp index 7ee2ddf3605ff..7729d9cf92dae 100644 --- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -97,7 +97,7 @@ class ExpandPseudo { ExpandPseudo::ExpandPseudo(MachineFunction &MF_) : MF(MF_), MRI(MF.getRegInfo()), - Subtarget(static_cast(MF.getSubtarget())), + Subtarget(MF.getSubtarget()), TII(*static_cast(Subtarget.getInstrInfo())), RegInfo(*Subtarget.getRegisterInfo()) {} diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 9a3a851b4a8b5..1124111c1a6ed 100644 --- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -38,7 +38,7 @@ using namespace llvm; #define DEBUG_TYPE "mips-isel" bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { - Subtarget = &static_cast(MF.getSubtarget()); + Subtarget = &MF.getSubtarget(); if (Subtarget->inMips16Mode()) return false; return MipsDAGToDAGISel::runOnMachineFunction(MF); diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp index dd4290a605a9c..dfa84bc735e2c 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp @@ -42,7 +42,7 @@ NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm, } bool NVPTXDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { - Subtarget = &static_cast(MF.getSubtarget()); + Subtarget = &MF.getSubtarget(); return SelectionDAGISel::runOnMachineFunction(MF); } diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index f9da62a27af58..6a31bd763ccd9 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1883,8 +1883,7 @@ bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, /// For the latter, the input operands are swapped (see PPCInstrAltivec.td). bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) { - const PPCSubtarget& Subtarget = - static_cast(DAG.getSubtarget()); + const PPCSubtarget &Subtarget = DAG.getSubtarget(); if (!Subtarget.hasP8Vector()) return false; @@ -6922,8 +6921,7 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX( if (useSoftFloat()) report_fatal_error("Soft float support is unimplemented on AIX."); - const PPCSubtarget &Subtarget = - static_cast(DAG.getSubtarget()); + const PPCSubtarget &Subtarget = DAG.getSubtarget(); const bool IsPPC64 = Subtarget.isPPC64(); const unsigned PtrByteSize = IsPPC64 ? 8 : 4; @@ -7228,8 +7226,7 @@ SDValue PPCTargetLowering::LowerCall_AIX( if (CFlags.IsPatchPoint) report_fatal_error("This call type is unimplemented on AIX."); - const PPCSubtarget& Subtarget = - static_cast(DAG.getSubtarget()); + const PPCSubtarget &Subtarget = DAG.getSubtarget(); MachineFunction &MF = DAG.getMachineFunction(); SmallVector ArgLocs; diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp index e34f522ab5505..123cff7f0f159 100644 --- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp +++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp @@ -1052,8 +1052,7 @@ void SystemZAsmPrinter::emitPPA1(MCSymbol *FnEndSym) { } void SystemZAsmPrinter::emitFunctionEntryLabel() { - const SystemZSubtarget &Subtarget = - static_cast(MF->getSubtarget()); + const SystemZSubtarget &Subtarget = MF->getSubtarget(); if (Subtarget.getTargetTriple().isOSzOS()) { MCContext &OutContext = OutStreamer->getContext(); diff --git a/llvm/lib/Target/X86/X86CallingConv.cpp b/llvm/lib/Target/X86/X86CallingConv.cpp index c80a5d5bb332b..ded93fdc011cf 100644 --- a/llvm/lib/Target/X86/X86CallingConv.cpp +++ b/llvm/lib/Target/X86/X86CallingConv.cpp @@ -299,7 +299,7 @@ static bool CC_X86_Intr(unsigned &ValNo, MVT &ValVT, MVT &LocVT, ISD::ArgFlagsTy &ArgFlags, CCState &State) { const MachineFunction &MF = State.getMachineFunction(); size_t ArgCount = State.getMachineFunction().getFunction().arg_size(); - bool Is64Bit = static_cast(MF.getSubtarget()).is64Bit(); + bool Is64Bit = MF.getSubtarget().is64Bit(); unsigned SlotSize = Is64Bit ? 8 : 4; unsigned Offset; if (ArgCount == 1 && ValNo == 0) { diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp index d98c2a4112422..aebeec5a6d274 100644 --- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp +++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp @@ -730,7 +730,7 @@ bool X86ExpandPseudo::ExpandPseudosWhichAffectControlFlow(MachineFunction &MF) { } bool X86ExpandPseudo::runOnMachineFunction(MachineFunction &MF) { - STI = &static_cast(MF.getSubtarget()); + STI = &MF.getSubtarget(); TII = STI->getInstrInfo(); TRI = STI->getRegisterInfo(); X86FI = MF.getInfo(); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 92f4e012ef8ff..6b38e14704c74 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -26078,8 +26078,7 @@ static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn, // Return EntryEBP + ParentFrameOffset for x64. This adjusts from RSP after // prologue to RBP in the parent function. - const X86Subtarget &Subtarget = - static_cast(DAG.getSubtarget()); + const X86Subtarget &Subtarget = DAG.getSubtarget(); if (Subtarget.is64Bit()) return DAG.getNode(ISD::ADD, dl, PtrVT, EntryEBP, ParentFrameOffset); @@ -39122,8 +39121,7 @@ static SDValue combineCommutableSHUFP(SDValue N, MVT VT, const SDLoc &DL, SDValue N0 = V.getOperand(0); SDValue N1 = V.getOperand(1); unsigned Imm = V.getConstantOperandVal(2); - const X86Subtarget &Subtarget = - static_cast(DAG.getSubtarget()); + const X86Subtarget &Subtarget = DAG.getSubtarget(); if (!X86::mayFoldLoad(peekThroughOneUseBitcasts(N0), Subtarget) || X86::mayFoldLoad(peekThroughOneUseBitcasts(N1), Subtarget)) return SDValue();