diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index c91e7b7c64fdf..2ab27f5225ea2 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3154,6 +3154,10 @@ defm LDURBB
              [(set GPR32:$Rt,
                     (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
 
+// bf16 load pattern
+def : Pat <(bf16 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
+           (LDURHi GPR64sp:$Rn, simm9:$offset)>;
+
 // Match all load 64 bits width whose type is compatible with FPR64
 let Predicates = [IsLE] in {
   def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
diff --git a/llvm/test/CodeGen/AArch64/bf16.ll b/llvm/test/CodeGen/AArch64/bf16.ll
index ad05f07b9b8be..14ce317e7e383 100644
--- a/llvm/test/CodeGen/AArch64/bf16.ll
+++ b/llvm/test/CodeGen/AArch64/bf16.ll
@@ -11,6 +11,24 @@ define bfloat @test_load(ptr %p) nounwind {
   ret bfloat %tmp1
 }
 
+define bfloat @test_load_offset1(ptr %p) nounwind {
+; CHECK-LABEL: test_load_offset1:
+; CHECK-NEXT: ldur h0, [x0, #1]
+; CHECK-NEXT: ret
+  %g = getelementptr inbounds i8, ptr %p, i64 1
+  %tmp1 = load bfloat, ptr %g, align 2
+  ret bfloat %tmp1
+}
+
+define bfloat @test_load_offset2(ptr %p) nounwind {
+; CHECK-LABEL: test_load_offset2:
+; CHECK-NEXT: ldr h0, [x0, #2]
+; CHECK-NEXT: ret
+  %g = getelementptr inbounds i8, ptr %p, i64 2
+  %tmp1 = load bfloat, ptr %g, align 2
+  ret bfloat %tmp1
+}
+
 define <4 x bfloat> @test_vec_load(ptr %p) nounwind {
 ; CHECK-LABEL: test_vec_load:
 ; CHECK-NEXT: ldr d0, [x0]