diff --git a/llvm/test/CodeGen/LoongArch/1ri.mir b/llvm/test/CodeGen/LoongArch/1ri.mir new file mode 100644 index 0000000000000..d267e3800b76f --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/1ri.mir @@ -0,0 +1,96 @@ +# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefix=CHECK-ENC +# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=asm -o - \ +# RUN: | FileCheck %s -check-prefix=CHECK-ASM + +# ------------------------------------------------------------------------------------------------- +# Encoding format: 1RI20 +# ------------------------------------------------------------------------------------------------- +# ---------------------+-----------------------------------------------------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ---------------------+-----------------------------------------------------------+--------------- +# opcode | imm20 | rd +# ---------------------+-----------------------------------------------------------+--------------- + +--- +# CHECK-LABEL: test_LU12I_W: +# CHECK-ENC: 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 +# CHECK-ASM: lu12i.w a0, 49 +name: test_LU12I_W +body: | + bb.0: + $r4 = LU12I_W 49 +... +--- +# CHECK-LABEL: test_LU32I_D: +# CHECK-ENC: 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 +# CHECK-ASM: lu32i.d a0, 196 +name: test_LU32I_D +body: | + bb.0: + $r4 = LU32I_D 196 +... +--- +# CHECK-LABEL: test_PCADDI: +# CHECK-ENC: 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 1 0 0 +# CHECK-ASM: pcaddi a0, 187 +name: test_PCADDI +body: | + bb.0: + $r4 = PCADDI 187 +... +--- +# CHECK-LABEL: test_PCALAU12I: +# CHECK-ENC: 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 +# CHECK-ASM: pcalau12i a0, 89 +name: test_PCALAU12I +body: | + bb.0: + $r4 = PCALAU12I 89 +... +--- +# CHECK-LABEL: test_PCADDU12I: +# CHECK-ENC: 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: pcaddu12i a0, 37 +name: test_PCADDU12I +body: | + bb.0: + $r4 = PCADDU12I 37 +... +--- +# CHECK-LABEL: test_PCADDU18I: +# CHECK-ENC: 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 +# CHECK-ASM: pcaddu18i a0, 26 +name: test_PCADDU18I +body: | + bb.0: + $r4 = PCADDU18I 26 +... + +# ------------------------------------------------------------------------------------------------- +# Encoding format: 1RI21 +# ------------------------------------------------------------------------------------------------- +# ------------------+-----------------------------------------------+--------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ------------------+-----------------------------------------------+--------------+--------------- +# opcode | imm21{15-0} | rj | imm21{20-16} +# ------------------+-----------------------------------------------+--------------+--------------- + +--- +# CHECK-LABEL: test_BEQZ: +# CHECK-ENC: 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 +# CHECK-ASM: beqz a0, 23 +name: test_BEQZ +body: | + bb.0: + BEQZ $r4, 23 +... +--- +# CHECK-LABEL: test_BNEZ: +# CHECK-ENC: 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 +# CHECK-ASM: bnez a0, 21 +name: test_BNEZ +body: | + bb.0: + BNEZ $r4, 21 diff --git a/llvm/test/CodeGen/LoongArch/2r.mir b/llvm/test/CodeGen/LoongArch/2r.mir new file mode 100644 index 0000000000000..93bb5418a88e6 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/2r.mir @@ -0,0 +1,230 @@ +# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefix=CHECK-ENC +# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=asm -o - \ +# RUN: | FileCheck %s -check-prefix=CHECK-ASM + +# ------------------------------------------------------------------------------------------------- +# Encoding format: 2R +# ------------------------------------------------------------------------------------------------- +# ------------------------------------------------------------------+--------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ------------------------------------------------------------------+--------------+--------------- +# opcode | rj | rd +# ------------------------------------------------------------------+--------------+--------------- + +--- +# CHECK-LABEL: test_CLO_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: clo.w a0, a1 +name: test_CLO_W +body: | + bb.0: + $r4 = CLO_W $r5 +... +--- +# CHECK-LABEL: test_CLZ_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: clz.w a0, a1 +name: test_CLZ_W +body: | + bb.0: + $r4 = CLZ_W $r5 +... +--- +# CHECK-LABEL: test_CTO_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: cto.w a0, a1 +name: test_CTO_W +body: | + bb.0: + $r4 = CTO_W $r5 +... +--- +# CHECK-LABEL: test_CTZ_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ctz.w a0, a1 +name: test_CTZ_W +body: | + bb.0: + $r4 = CTZ_W $r5 +... +--- +# CHECK-LABEL: test_CLO_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: clo.d a0, a1 +name: test_CLO_D +body: | + bb.0: + $r4 = CLO_D $r5 +... +--- +# CHECK-LABEL: test_CLZ_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: clz.d a0, a1 +name: test_CLZ_D +body: | + bb.0: + $r4 = CLZ_D $r5 +... +--- +# CHECK-LABEL: test_CTO_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: cto.d a0, a1 +name: test_CTO_D +body: | + bb.0: + $r4 = CTO_D $r5 +... +--- +# CHECK-LABEL: test_CTZ_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ctz.d a0, a1 +name: test_CTZ_D +body: | + bb.0: + $r4 = CTZ_D $r5 +... +--- +# CHECK-LABEL: test_REVB_2H: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: revb.2h a0, a1 +name: test_REVB_2H +body: | + bb.0: + $r4 = REVB_2H $r5 +... +--- +# CHECK-LABEL: test_REVB_4H: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: revb.4h a0, a1 +name: test_REVB_4H +body: | + bb.0: + $r4 = REVB_4H $r5 +... +--- +# CHECK-LABEL: test_REVB_2W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: revb.2w a0, a1 +name: test_REVB_2W +body: | + bb.0: + $r4 = REVB_2W $r5 +... +--- +# CHECK-LABEL: test_REVB_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: revb.d a0, a1 +name: test_REVB_D +body: | + bb.0: + $r4 = REVB_D $r5 +... +--- +# CHECK-LABEL: test_REVH_2W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: revh.2w a0, a1 +name: test_REVH_2W +body: | + bb.0: + $r4 = REVH_2W $r5 +... +--- +# CHECK-LABEL: test_REVH_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: revh.d a0, a1 +name: test_REVH_D +body: | + bb.0: + $r4 = REVH_D $r5 +... +--- +# CHECK-LABEL: test_BITREV_4B: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: bitrev.4b a0, a1 +name: test_BITREV_4B +body: | + bb.0: + $r4 = BITREV_4B $r5 +... +--- +# CHECK-LABEL: test_BITREV_8B: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: bitrev.8b a0, a1 +name: test_BITREV_8B +body: | + bb.0: + $r4 = BITREV_8B $r5 +... +--- +# CHECK-LABEL: test_BITREV_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: bitrev.w a0, a1 +name: test_BITREV_W +body: | + bb.0: + $r4 = BITREV_W $r5 +... +--- +# CHECK-LABEL: test_BITREV_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: bitrev.d a0, a1 +name: test_BITREV_D +body: | + bb.0: + $r4 = BITREV_D $r5 +... +--- +# CHECK-LABEL: test_EXT_W_H: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ext.w.h a0, a1 +name: test_EXT_W_H +body: | + bb.0: + $r4 = EXT_W_H $r5 +... +--- +# CHECK-LABEL: test_EXT_W_B: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ext.w.b a0, a1 +name: test_EXT_W_B +body: | + bb.0: + $r4 = EXT_W_B $r5 +... +--- +# CHECK-LABEL: test_CPUCFG: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: cpucfg a0, a1 +name: test_CPUCFG +body: | + bb.0: + $r4 = CPUCFG $r5 +... +--- +# CHECK-LABEL: test_RDTIMEL_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: rdtimel.w a0, a1 +name: test_RDTIMEL_W +body: | + bb.0: + $r4, $r5 = RDTIMEL_W +... +--- +# CHECK-LABEL: test_RDTIMEH_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: rdtimeh.w a0, a1 +name: test_RDTIMEH_W +body: | + bb.0: + $r4, $r5 = RDTIMEH_W +... +--- +# CHECK-LABEL: test_RDTIME_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: rdtime.d a0, a1 +name: test_RDTIME_D +body: | + bb.0: + $r4, $r5 = RDTIME_D diff --git a/llvm/test/CodeGen/LoongArch/2ri.mir b/llvm/test/CodeGen/LoongArch/2ri.mir new file mode 100644 index 0000000000000..cef682ba5039e --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/2ri.mir @@ -0,0 +1,432 @@ +# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefix=CHECK-ENC +# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=asm -o - \ +# RUN: | FileCheck %s -check-prefix=CHECK-ASM + +# ------------------------------------------------------------------------------------------------- +# Encoding format: 2RI5 +# ------------------------------------------------------------------------------------------------- +# ---------------------------------------------------+--------------+--------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ---------------------------------------------------+--------------+--------------+--------------- +# opcode | imm5 | rj | rd +# ---------------------------------------------------+--------------+--------------+--------------- + +--- +# CHECK-LABEL: test_SLLI_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: slli.w a0, a1, 0 +name: test_SLLI_W +body: | + bb.0: + $r4 = SLLI_W $r5, 0 +... +--- +# CHECK-LABEL: test_SRLI_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: srli.w a0, a1, 30 +name: test_SRLI_W +body: | + bb.0: + $r4 = SRLI_W $r5, 30 +... +--- +# CHECK-LABEL: test_SRAI_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: srai.w a0, a1, 24 +name: test_SRAI_W +body: | + bb.0: + $r4 = SRAI_W $r5, 24 +... +--- +# CHECK-LABEL: test_ROTRI_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: rotri.w a0, a1, 23 +name: test_ROTRI_W +body: | + bb.0: + $r4 = ROTRI_W $r5, 23 +... + +# ------------------------------------------------------------------------------------------------- +# Encoding format: 2RI6 +# ------------------------------------------------------------------------------------------------- +# ------------------------------------------------+-----------------+--------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ------------------------------------------------+-----------------+--------------+--------------- +# opcode | imm6 | rj | rd +# ------------------------------------------------+-----------------+--------------+--------------- + +--- +# CHECK-LABEL: test_SLLI_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: slli.d a0, a1, 39 +name: test_SLLI_D +body: | + bb.0: + $r4 = SLLI_D $r5, 39 +... +--- +# CHECK-LABEL: test_SRLI_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: srli.d a0, a1, 38 +name: test_SRLI_D +body: | + bb.0: + $r4 = SRLI_D $r5, 38 +... +--- +# CHECK-LABEL: test_SRAI_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: srai.d a0, a1, 27 +name: test_SRAI_D +body: | + bb.0: + $r4 = SRAI_D $r5, 27 +... +--- +# CHECK-LABEL: test_ROTRI_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: rotri.d a0, a1, 7 +name: test_ROTRI_D +body: | + bb.0: + $r4 = ROTRI_D $r5, 7 +... + +# ------------------------------------------------------------------------------------------------- +# Encoding format: 2RI12 +# ------------------------------------------------------------------------------------------------- +# ------------------------------+-----------------------------------+--------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ------------------------------+-----------------------------------+--------------+--------------- +# opcode | imm12 | rj | rd +# ------------------------------+-----------------------------------+--------------+--------------- + +--- +# CHECK-LABEL: test_SLTI: +# CHECK-ENC: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: slti a0, a1, 235 +name: test_SLTI +body: | + bb.0: + $r4 = SLTI $r5, 235 +... +--- +# CHECK-LABEL: test_SLTUI: +# CHECK-ENC: 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: sltui a0, a1, 162 +name: test_SLTUI +body: | + bb.0: + $r4 = SLTUI $r5, 162 +... +--- +# CHECK-LABEL: test_ADDI_W: +# CHECK-ENC: 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: addi.w a0, a1, 246 +name: test_ADDI_W +body: | + bb.0: + $r4 = ADDI_W $r5, 246 +... +--- +# CHECK-LABEL: test_ADDI_D: +# CHECK-ENC: 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: addi.d a0, a1, 75 +name: test_ADDI_D +body: | + bb.0: + $r4 = ADDI_D $r5, 75 +... +--- +# CHECK-LABEL: test_LU52I_D: +# CHECK-ENC: 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: lu52i.d a0, a1, 195 +name: test_LU52I_D +body: | + bb.0: + $r4 = LU52I_D $r5, 195 +... +--- +# CHECK-LABEL: test_ANDI: +# CHECK-ENC: 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: andi a0, a1, 106 +name: test_ANDI +body: | + bb.0: + $r4 = ANDI $r5, 106 +... +--- +# CHECK-LABEL: test_ORI: +# CHECK-ENC: 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ori a0, a1, 47 +name: test_ORI +body: | + bb.0: + $r4 = ORI $r5, 47 +... +--- +# CHECK-LABEL: test_XORI: +# CHECK-ENC: 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: xori a0, a1, 99 +name: test_XORI +body: | + bb.0: + $r4 = XORI $r5, 99 +... +--- +# CHECK-LABEL: test_LD_B: +# CHECK-ENC: 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ld.b a0, a1, 21 +name: test_LD_B +body: | + bb.0: + $r4 = LD_B $r5, 21 +... +--- +# CHECK-LABEL: test_LD_H: +# CHECK-ENC: 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ld.h a0, a1, 80 +name: test_LD_H +body: | + bb.0: + $r4 = LD_H $r5, 80 +... +--- +# CHECK-LABEL: test_LD_W: +# CHECK-ENC: 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ld.w a0, a1, 92 +name: test_LD_W +body: | + bb.0: + $r4 = LD_W $r5, 92 +... +--- +# CHECK-LABEL: test_LD_BU: +# CHECK-ENC: 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ld.bu a0, a1, 150 +name: test_LD_BU +body: | + bb.0: + $r4 = LD_BU $r5, 150 +... +--- +# CHECK-LABEL: test_LD_HU: +# CHECK-ENC: 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ld.hu a0, a1, 198 +name: test_LD_HU +body: | + bb.0: + $r4 = LD_HU $r5, 198 +... +--- +# CHECK-LABEL: test_LD_WU: +# CHECK-ENC: 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ld.wu a0, a1, 31 +name: test_LD_WU +body: | + bb.0: + $r4 = LD_WU $r5, 31 +... +--- +# CHECK-LABEL: test_ST_B: +# CHECK-ENC: 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: st.b a0, a1, 95 +name: test_ST_B +body: | + bb.0: + ST_B $r4, $r5, 95 +... +--- +# CHECK-LABEL: test_ST_H: +# CHECK-ENC: 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: st.h a0, a1, 122 +name: test_ST_H +body: | + bb.0: + ST_H $r4, $r5, 122 +... +--- +# CHECK-LABEL: test_ST_W: +# CHECK-ENC: 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: st.w a0, a1, 175 +name: test_ST_W +body: | + bb.0: + ST_W $r4, $r5, 175 +... +--- +# CHECK-LABEL: test_ST_D: +# CHECK-ENC: 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: st.d a0, a1, 60 +name: test_ST_D +body: | + bb.0: + ST_D $r4, $r5, 60 +... + +# ------------------------------------------------------------------------------------------------- +# Encoding format: 2RI14 +# ------------------------------------------------------------------------------------------------- +# ------------------------+-----------------------------------------+--------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ------------------------+-----------------------------------------+--------------+--------------- +# opcode | imm14 | rj | rd +# ------------------------+-----------------------------------------+--------------+--------------- + +--- +# CHECK-LABEL: test_LDPTR_W: +# CHECK-ENC: 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldptr.w a0, a1, 66 +name: test_LDPTR_W +body: | + bb.0: + $r4 = LDPTR_W $r5, 66 +... +--- +# CHECK-LABEL: test_LDPTR_D: +# CHECK-ENC: 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldptr.d a0, a1, 56 +name: test_LDPTR_D +body: | + bb.0: + $r4 = LDPTR_D $r5, 56 +... +--- +# CHECK-LABEL: test_STPTR_W: +# CHECK-ENC: 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: stptr.w a0, a1, 87 +name: test_STPTR_W +body: | + bb.0: + STPTR_W $r4, $r5, 87 +... +--- +# CHECK-LABEL: test_STPTR_D: +# CHECK-ENC: 0 0 1 0 0 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: stptr.d a0, a1, 145 +name: test_STPTR_D +body: | + bb.0: + STPTR_D $r4, $r5, 145 +... +--- +# CHECK-LABEL: test_LL_W: +# CHECK-ENC: 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ll.w a0, a1, 243 +name: test_LL_W +body: | + bb.0: + $r4 = LL_W $r5, 243 +... +--- +# CHECK-LABEL: test_LL_D: +# CHECK-ENC: 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ll.d a0, a1, 74 +name: test_LL_D +body: | + bb.0: + $r4 = LL_D $r5, 74 +... +--- +# CHECK-LABEL: test_SC_W: +# CHECK-ENC: 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: sc.w a0, a1, 96 +name: test_SC_W +body: | + bb.0: + $r4 = SC_W $r4, $r5, 96 +... +--- +# CHECK-LABEL: test_SC_D: +# CHECK-ENC: 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: sc.d a0, a1, 105 +name: test_SC_D +body: | + bb.0: + $r4 = SC_D $r4, $r5, 105 +... + +# ------------------------------------------------------------------------------------------------- +# Encoding format: 2RI16 +# ------------------------------------------------------------------------------------------------- +# ------------------+-----------------------------------------------+--------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ------------------+-----------------------------------------------+--------------+--------------- +# opcode | imm16 | rj | rd +# ------------------+-----------------------------------------------+--------------+--------------- + +--- +# CHECK-LABEL: test_ADDU16I_D: +# CHECK-ENC: 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: addu16i.d a0, a1, 23 +name: test_ADDU16I_D +body: | + bb.0: + $r4 = ADDU16I_D $r5, 23 +... +--- +# CHECK-LABEL: test_JIRL: +# CHECK-ENC: 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: jirl a0, a1, 49 +name: test_JIRL +body: | + bb.0: + $r4 = JIRL $r5, 49 +... +--- +# CHECK-LABEL: test_BEQ: +# CHECK-ENC: 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 +# CHECK-ASM: beq a0, a1, 196 +name: test_BEQ +body: | + bb.0: + BEQ $r4, $r5, 196 +... +--- +# CHECK-LABEL: test_BNE: +# CHECK-ENC: 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 +# CHECK-ASM: bne a0, a1, 19 +name: test_BNE +body: | + bb.0: + BNE $r4, $r5, 19 +... +--- +# CHECK-LABEL: test_BLT: +# CHECK-ENC: 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 0 0 0 0 1 0 1 +# CHECK-ASM: blt a0, a1, 123 +name: test_BLT +body: | + bb.0: + BLT $r4, $r5, 123 +... +--- +# CHECK-LABEL: test_BGE: +# CHECK-ENC: 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 1 +# CHECK-ASM: bge a0, a1, 12 +name: test_BGE +body: | + bb.0: + BGE $r4, $r5, 12 +... +--- +# CHECK-LABEL: test_BLTU: +# CHECK-ENC: 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 1 +# CHECK-ASM: bltu a0, a1, 17 +name: test_BLTU +body: | + bb.0: + BLTU $r4, $r5, 17 +... +--- +# CHECK-LABEL: test_BGEU: +# CHECK-ENC: 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 +# CHECK-ASM: bgeu a0, a1, 88 +name: test_BGEU +body: | + bb.0: + BGEU $r4, $r5, 88 diff --git a/llvm/test/CodeGen/LoongArch/3r.mir b/llvm/test/CodeGen/LoongArch/3r.mir new file mode 100644 index 0000000000000..fc9012b3b1992 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/3r.mir @@ -0,0 +1,995 @@ +# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefix=CHECK-ENC +# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=asm -o - \ +# RUN: | FileCheck %s -check-prefix=CHECK-ASM + +# ------------------------------------------------------------------------------------------------- +# Encoding format: 3R +# ------------------------------------------------------------------------------------------------- +# ---------------------------------------------------+--------------+--------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ---------------------------------------------------+--------------+--------------+--------------- +# opcode | rk | rj | rd +# ---------------------------------------------------+--------------+--------------+--------------- + +--- +# CHECK-LABEL: test_ADD_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: add.w a0, a1, a0 +name: test_ADD_W +body: | + bb.0: + $r4 = ADD_W $r5, $r4 +... +--- +# CHECK-LABEL: test_ADD_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: add.d a0, a1, a0 +name: test_ADD_D +body: | + bb.0: + $r4 = ADD_D $r5, $r4 +... +--- +# CHECK-LABEL: test_SUB_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: sub.w a0, a1, a0 +name: test_SUB_W +body: | + bb.0: + $r4 = SUB_W $r5, $r4 +... +--- +# CHECK-LABEL: test_SUB_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: sub.d a0, a1, a0 +name: test_SUB_D +body: | + bb.0: + $r4 = SUB_D $r5, $r4 +... +--- +# CHECK-LABEL: test_SLT: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: slt a0, a1, a0 +name: test_SLT +body: | + bb.0: + $r4 = SLT $r5, $r4 +... +--- +# CHECK-LABEL: test_SLTU: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: sltu a0, a1, a0 +name: test_SLTU +body: | + bb.0: + $r4 = SLTU $r5, $r4 +... +--- +# CHECK-LABEL: test_MASKEQZ: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: maskeqz a0, a1, a0 +name: test_MASKEQZ +body: | + bb.0: + $r4 = MASKEQZ $r5, $r4 +... +--- +# CHECK-LABEL: test_MASKNEZ: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: masknez a0, a1, a0 +name: test_MASKNEZ +body: | + bb.0: + $r4 = MASKNEZ $r5, $r4 +... +--- +# CHECK-LABEL: test_NOR: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: nor a0, a1, a0 +name: test_NOR +body: | + bb.0: + $r4 = NOR $r5, $r4 +... +--- +# CHECK-LABEL: test_AND: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: and a0, a1, a0 +name: test_AND +body: | + bb.0: + $r4 = AND $r5, $r4 +... +--- +# CHECK-LABEL: test_OR: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: or a0, a1, a0 +name: test_OR +body: | + bb.0: + $r4 = OR $r5, $r4 +... +--- +# CHECK-LABEL: test_XOR: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: xor a0, a1, a0 +name: test_XOR +body: | + bb.0: + $r4 = XOR $r5, $r4 +... +--- +# CHECK-LABEL: test_ORN: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: orn a0, a1, a0 +name: test_ORN +body: | + bb.0: + $r4 = ORN $r5, $r4 +... +--- +# CHECK-LABEL: test_ANDN: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: andn a0, a1, a0 +name: test_ANDN +body: | + bb.0: + $r4 = ANDN $r5, $r4 +... +--- +# CHECK-LABEL: test_SLL_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: sll.w a0, a1, a0 +name: test_SLL_W +body: | + bb.0: + $r4 = SLL_W $r5, $r4 +... +--- +# CHECK-LABEL: test_SRL_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: srl.w a0, a1, a0 +name: test_SRL_W +body: | + bb.0: + $r4 = SRL_W $r5, $r4 +... +--- +# CHECK-LABEL: test_SRA_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: sra.w a0, a1, a0 +name: test_SRA_W +body: | + bb.0: + $r4 = SRA_W $r5, $r4 +... +--- +# CHECK-LABEL: test_SLL_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: sll.d a0, a1, a0 +name: test_SLL_D +body: | + bb.0: + $r4 = SLL_D $r5, $r4 +... +--- +# CHECK-LABEL: test_SRL_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: srl.d a0, a1, a0 +name: test_SRL_D +body: | + bb.0: + $r4 = SRL_D $r5, $r4 +... +--- +# CHECK-LABEL: test_SRA_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: sra.d a0, a1, a0 +name: test_SRA_D +body: | + bb.0: + $r4 = SRA_D $r5, $r4 +... +--- +# CHECK-LABEL: test_ROTR_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: rotr.w a0, a1, a0 +name: test_ROTR_W +body: | + bb.0: + $r4 = ROTR_W $r5, $r4 +... +--- +# CHECK-LABEL: test_ROTR_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: rotr.d a0, a1, a0 +name: test_ROTR_D +body: | + bb.0: + $r4 = ROTR_D $r5, $r4 +... +--- +# CHECK-LABEL: test_MUL_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: mul.w a0, a1, a0 +name: test_MUL_W +body: | + bb.0: + $r4 = MUL_W $r5, $r4 +... +--- +# CHECK-LABEL: test_MULH_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: mulh.w a0, a1, a0 +name: test_MULH_W +body: | + bb.0: + $r4 = MULH_W $r5, $r4 +... +--- +# CHECK-LABEL: test_MULH_WU: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: mulh.wu a0, a1, a0 +name: test_MULH_WU +body: | + bb.0: + $r4 = MULH_WU $r5, $r4 +... +--- +# CHECK-LABEL: test_MUL_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: mul.d a0, a1, a0 +name: test_MUL_D +body: | + bb.0: + $r4 = MUL_D $r5, $r4 +... +--- +# CHECK-LABEL: test_MULH_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: mulh.d a0, a1, a0 +name: test_MULH_D +body: | + bb.0: + $r4 = MULH_D $r5, $r4 +... +--- +# CHECK-LABEL: test_MULH_DU: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: mulh.du a0, a1, a0 +name: test_MULH_DU +body: | + bb.0: + $r4 = MULH_DU $r5, $r4 +... +--- +# CHECK-LABEL: test_MULW_D_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: mulw.d.w a0, a1, a0 +name: test_MULW_D_W +body: | + bb.0: + $r4 = MULW_D_W $r5, $r4 +... +--- +# CHECK-LABEL: test_MULW_D_WU: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: mulw.d.wu a0, a1, a0 +name: test_MULW_D_WU +body: | + bb.0: + $r4 = MULW_D_WU $r5, $r4 +... +--- +# CHECK-LABEL: test_DIV_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: div.w a0, a1, a0 +name: test_DIV_W +body: | + bb.0: + $r4 = DIV_W $r5, $r4 +... +--- +# CHECK-LABEL: test_MOD_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: mod.w a0, a1, a0 +name: test_MOD_W +body: | + bb.0: + $r4 = MOD_W $r5, $r4 +... +--- +# CHECK-LABEL: test_DIV_WU: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: div.wu a0, a1, a0 +name: test_DIV_WU +body: | + bb.0: + $r4 = DIV_WU $r5, $r4 +... +--- +# CHECK-LABEL: test_MOD_WU: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: mod.wu a0, a1, a0 +name: test_MOD_WU +body: | + bb.0: + $r4 = MOD_WU $r5, $r4 +... +--- +# CHECK-LABEL: test_DIV_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: div.d a0, a1, a0 +name: test_DIV_D +body: | + bb.0: + $r4 = DIV_D $r5, $r4 +... +--- +# CHECK-LABEL: test_MOD_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: mod.d a0, a1, a0 +name: test_MOD_D +body: | + bb.0: + $r4 = MOD_D $r5, $r4 +... +--- +# CHECK-LABEL: test_DIV_DU: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: div.du a0, a1, a0 +name: test_DIV_DU +body: | + bb.0: + $r4 = DIV_DU $r5, $r4 +... +--- +# CHECK-LABEL: test_MOD_DU: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: mod.du a0, a1, a0 +name: test_MOD_DU +body: | + bb.0: + $r4 = MOD_DU $r5, $r4 +... +--- +# CHECK-LABEL: test_CRC_W_B_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: crc.w.b.w a0, a1, a0 +name: test_CRC_W_B_W +body: | + bb.0: + $r4 = CRC_W_B_W $r5, $r4 +... +--- +# CHECK-LABEL: test_CRC_W_H_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: crc.w.h.w a0, a1, a0 +name: test_CRC_W_H_W +body: | + bb.0: + $r4 = CRC_W_H_W $r5, $r4 +... +--- +# CHECK-LABEL: test_CRC_W_W_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: crc.w.w.w a0, a1, a0 +name: test_CRC_W_W_W +body: | + bb.0: + $r4 = CRC_W_W_W $r5, $r4 +... +--- +# CHECK-LABEL: test_CRC_W_D_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: crc.w.d.w a0, a1, a0 +name: test_CRC_W_D_W +body: | + bb.0: + $r4 = CRC_W_D_W $r5, $r4 +... +--- +# CHECK-LABEL: test_CRCC_W_B_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: crcc.w.b.w a0, a1, a0 +name: test_CRCC_W_B_W +body: | + bb.0: + $r4 = CRCC_W_B_W $r5, $r4 +... +--- +# CHECK-LABEL: test_CRCC_W_H_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: crcc.w.h.w a0, a1, a0 +name: test_CRCC_W_H_W +body: | + bb.0: + $r4 = CRCC_W_H_W $r5, $r4 +... +--- +# CHECK-LABEL: test_CRCC_W_W_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: crcc.w.w.w a0, a1, a0 +name: test_CRCC_W_W_W +body: | + bb.0: + $r4 = CRCC_W_W_W $r5, $r4 +... +--- +# CHECK-LABEL: test_CRCC_W_D_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: crcc.w.d.w a0, a1, a0 +name: test_CRCC_W_D_W +body: | + bb.0: + $r4 = CRCC_W_D_W $r5, $r4 +... +--- +# CHECK-LABEL: test_AMSWAP_DB_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amswap_db.w a0, a1, a2 +name: test_AMSWAP_DB_W +body: | + bb.0: + $r4 = AMSWAP_DB_W $r5, $r6 +... +--- +# CHECK-LABEL: test_AMSWAP_DB_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amswap_db.d a0, a1, a2 +name: test_AMSWAP_DB_D +body: | + bb.0: + $r4 = AMSWAP_DB_D $r5, $r6 +... +--- +# CHECK-LABEL: test_AMADD_DB_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amadd_db.w a0, a1, a2 +name: test_AMADD_DB_W +body: | + bb.0: + $r4 = AMADD_DB_W $r5, $r6 +... +--- +# CHECK-LABEL: test_AMADD_DB_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amadd_db.d a0, a1, a2 +name: test_AMADD_DB_D +body: | + bb.0: + $r4 = AMADD_DB_D $r5, $r6 +... +--- +# CHECK-LABEL: test_AMAND_DB_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amand_db.w a0, a1, a2 +name: test_AMAND_DB_W +body: | + bb.0: + $r4 = AMAND_DB_W $r5, $r6 +... +--- +# CHECK-LABEL: test_AMAND_DB_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amand_db.d a0, a1, a2 +name: test_AMAND_DB_D +body: | + bb.0: + $r4 = AMAND_DB_D $r5, $r6 +... +--- +# CHECK-LABEL: test_AMOR_DB_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amor_db.w a0, a1, a2 +name: test_AMOR_DB_W +body: | + bb.0: + $r4 = AMOR_DB_W $r5, $r6 +... +--- +# CHECK-LABEL: test_AMOR_DB_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amor_db.d a0, a1, a2 +name: test_AMOR_DB_D +body: | + bb.0: + $r4 = AMOR_DB_D $r5, $r6 +... +--- +# CHECK-LABEL: test_AMXOR_DB_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amxor_db.w a0, a1, a2 +name: test_AMXOR_DB_W +body: | + bb.0: + $r4 = AMXOR_DB_W $r5, $r6 +... +--- +# CHECK-LABEL: test_AMXOR_DB_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amxor_db.d a0, a1, a2 +name: test_AMXOR_DB_D +body: | + bb.0: + $r4 = AMXOR_DB_D $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMAX_DB_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammax_db.w a0, a1, a2 +name: test_AMMAX_DB_W +body: | + bb.0: + $r4 = AMMAX_DB_W $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMAX_DB_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammax_db.d a0, a1, a2 +name: test_AMMAX_DB_D +body: | + bb.0: + $r4 = AMMAX_DB_D $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMIN_DB_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammin_db.w a0, a1, a2 +name: test_AMMIN_DB_W +body: | + bb.0: + $r4 = AMMIN_DB_W $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMIN_DB_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammin_db.d a0, a1, a2 +name: test_AMMIN_DB_D +body: | + bb.0: + $r4 = AMMIN_DB_D $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMAX_DB_WU: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammax_db.wu a0, a1, a2 +name: test_AMMAX_DB_WU +body: | + bb.0: + $r4 = AMMAX_DB_WU $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMAX_DB_DU: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammax_db.du a0, a1, a2 +name: test_AMMAX_DB_DU +body: | + bb.0: + $r4 = AMMAX_DB_DU $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMIN_DB_WU: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammin_db.wu a0, a1, a2 +name: test_AMMIN_DB_WU +body: | + bb.0: + $r4 = AMMIN_DB_WU $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMIN_DB_DU: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammin_db.du a0, a1, a2 +name: test_AMMIN_DB_DU +body: | + bb.0: + $r4 = AMMIN_DB_DU $r5, $r6 +... +--- +# CHECK-LABEL: test_AMSWAP_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amswap.w a0, a1, a2 +name: test_AMSWAP_W +body: | + bb.0: + $r4 = AMSWAP_W $r5, $r6 +... +--- +# CHECK-LABEL: test_AMSWAP_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amswap.d a0, a1, a2 +name: test_AMSWAP_D +body: | + bb.0: + $r4 = AMSWAP_D $r5, $r6 +... +--- +# CHECK-LABEL: test_AMADD_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amadd.w a0, a1, a2 +name: test_AMADD_W +body: | + bb.0: + $r4 = AMADD_W $r5, $r6 +... +--- +# CHECK-LABEL: test_AMADD_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amadd.d a0, a1, a2 +name: test_AMADD_D +body: | + bb.0: + $r4 = AMADD_D $r5, $r6 +... +--- +# CHECK-LABEL: test_AMAND_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amand.w a0, a1, a2 +name: test_AMAND_W +body: | + bb.0: + $r4 = AMAND_W $r5, $r6 +... +--- +# CHECK-LABEL: test_AMAND_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amand.d a0, a1, a2 +name: test_AMAND_D +body: | + bb.0: + $r4 = AMAND_D $r5, $r6 +... +--- +# CHECK-LABEL: test_AMOR_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amor.w a0, a1, a2 +name: test_AMOR_W +body: | + bb.0: + $r4 = AMOR_W $r5, $r6 +... +--- +# CHECK-LABEL: test_AMOR_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amor.d a0, a1, a2 +name: test_AMOR_D +body: | + bb.0: + $r4 = AMOR_D $r5, $r6 +... +--- +# CHECK-LABEL: test_AMXOR_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amxor.w a0, a1, a2 +name: test_AMXOR_W +body: | + bb.0: + $r4 = AMXOR_W $r5, $r6 +... +--- +# CHECK-LABEL: test_AMXOR_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: amxor.d a0, a1, a2 +name: test_AMXOR_D +body: | + bb.0: + $r4 = AMXOR_D $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMAX_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammax.w a0, a1, a2 +name: test_AMMAX_W +body: | + bb.0: + $r4 = AMMAX_W $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMAX_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammax.d a0, a1, a2 +name: test_AMMAX_D +body: | + bb.0: + $r4 = AMMAX_D $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMIN_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammin.w a0, a1, a2 +name: test_AMMIN_W +body: | + bb.0: + $r4 = AMMIN_W $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMIN_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammin.d a0, a1, a2 +name: test_AMMIN_D +body: | + bb.0: + $r4 = AMMIN_D $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMAX_WU: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammax.wu a0, a1, a2 +name: test_AMMAX_WU +body: | + bb.0: + $r4 = AMMAX_WU $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMAX_DU: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammax.du a0, a1, a2 +name: test_AMMAX_DU +body: | + bb.0: + $r4 = AMMAX_DU $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMIN_WU: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammin.wu a0, a1, a2 +name: test_AMMIN_WU +body: | + bb.0: + $r4 = AMMIN_WU $r5, $r6 +... +--- +# CHECK-LABEL: test_AMMIN_DU: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ammin.du a0, a1, a2 +name: test_AMMIN_DU +body: | + bb.0: + $r4 = AMMIN_DU $r5, $r6 +... +--- +# CHECK-LABEL: test_LDX_B: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldx.b a0, a1, a2 +name: test_LDX_B +body: | + bb.0: + $r4 = LDX_B $r5, $r6 +... +--- +# CHECK-LABEL: test_LDX_H: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldx.h a0, a1, a2 +name: test_LDX_H +body: | + bb.0: + $r4 = LDX_H $r5, $r6 +... +--- +# CHECK-LABEL: test_LDX_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldx.w a0, a1, a2 +name: test_LDX_W +body: | + bb.0: + $r4 = LDX_W $r5, $r6 +... +--- +# CHECK-LABEL: test_LDX_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldx.d a0, a1, a2 +name: test_LDX_D +body: | + bb.0: + $r4 = LDX_D $r5, $r6 +... +--- +# CHECK-LABEL: test_LDX_BU: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldx.bu a0, a1, a2 +name: test_LDX_BU +body: | + bb.0: + $r4 = LDX_BU $r5, $r6 +... +--- +# CHECK-LABEL: test_LDX_HU: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldx.hu a0, a1, a2 +name: test_LDX_HU +body: | + bb.0: + $r4 = LDX_HU $r5, $r6 +... +--- +# CHECK-LABEL: test_LDX_WU: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldx.wu a0, a1, a2 +name: test_LDX_WU +body: | + bb.0: + $r4 = LDX_WU $r5, $r6 +... +--- +# CHECK-LABEL: test_LDGT_B: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldgt.b a0, a1, a2 +name: test_LDGT_B +body: | + bb.0: + $r4 = LDGT_B $r5, $r6 +... +--- +# CHECK-LABEL: test_LDGT_H: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldgt.h a0, a1, a2 +name: test_LDGT_H +body: | + bb.0: + $r4 = LDGT_H $r5, $r6 +... +--- +# CHECK-LABEL: test_LDGT_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldgt.w a0, a1, a2 +name: test_LDGT_W +body: | + bb.0: + $r4 = LDGT_W $r5, $r6 +... +--- +# CHECK-LABEL: test_LDGT_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldgt.d a0, a1, a2 +name: test_LDGT_D +body: | + bb.0: + $r4 = LDGT_D $r5, $r6 +... +--- +# CHECK-LABEL: test_LDLE_B: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldle.b a0, a1, a2 +name: test_LDLE_B +body: | + bb.0: + $r4 = LDLE_B $r5, $r6 +... +--- +# CHECK-LABEL: test_LDLE_H: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldle.h a0, a1, a2 +name: test_LDLE_H +body: | + bb.0: + $r4 = LDLE_H $r5, $r6 +... +--- +# CHECK-LABEL: test_LDLE_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldle.w a0, a1, a2 +name: test_LDLE_W +body: | + bb.0: + $r4 = LDLE_W $r5, $r6 +... +--- +# CHECK-LABEL: test_LDLE_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: ldle.d a0, a1, a2 +name: test_LDLE_D +body: | + bb.0: + $r4 = LDLE_D $r5, $r6 +... +--- +# CHECK-LABEL: test_STX_B: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: stx.b a0, a1, a2 +name: test_STX_B +body: | + bb.0: + STX_B $r4, $r5, $r6 +... +--- +# CHECK-LABEL: test_STX_H: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: stx.h a0, a1, a2 +name: test_STX_H +body: | + bb.0: + STX_H $r4, $r5, $r6 +... +--- +# CHECK-LABEL: test_STX_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: stx.w a0, a1, a2 +name: test_STX_W +body: | + bb.0: + STX_W $r4, $r5, $r6 +... +--- +# CHECK-LABEL: test_STX_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: stx.d a0, a1, a2 +name: test_STX_D +body: | + bb.0: + STX_D $r4, $r5, $r6 +... +--- +# CHECK-LABEL: test_STGT_B: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: stgt.b a0, a1, a2 +name: test_STGT_B +body: | + bb.0: + STGT_B $r4, $r5, $r6 +... +--- +# CHECK-LABEL: test_STGT_H: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: stgt.h a0, a1, a2 +name: test_STGT_H +body: | + bb.0: + STGT_H $r4, $r5, $r6 +... +--- +# CHECK-LABEL: test_STGT_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: stgt.w a0, a1, a2 +name: test_STGT_W +body: | + bb.0: + STGT_W $r4, $r5, $r6 +... +--- +# CHECK-LABEL: test_STGT_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: stgt.d a0, a1, a2 +name: test_STGT_D +body: | + bb.0: + STGT_D $r4, $r5, $r6 +... +--- +# CHECK-LABEL: test_STLE_B: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: stle.b a0, a1, a2 +name: test_STLE_B +body: | + bb.0: + STLE_B $r4, $r5, $r6 +... +--- +# CHECK-LABEL: test_STLE_H: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: stle.h a0, a1, a2 +name: test_STLE_H +body: | + bb.0: + STLE_H $r4, $r5, $r6 +... +--- +# CHECK-LABEL: test_STLE_W: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: stle.w a0, a1, a2 +name: test_STLE_W +body: | + bb.0: + STLE_W $r4, $r5, $r6 +... +--- +# CHECK-LABEL: test_STLE_D: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: stle.d a0, a1, a2 +name: test_STLE_D +body: | + bb.0: + STLE_D $r4, $r5, $r6 diff --git a/llvm/test/CodeGen/LoongArch/3ri.mir b/llvm/test/CodeGen/LoongArch/3ri.mir new file mode 100644 index 0000000000000..4cf71ff1f8861 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/3ri.mir @@ -0,0 +1,69 @@ +# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefix=CHECK-ENC +# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=asm -o - \ +# RUN: | FileCheck %s -check-prefix=CHECK-ASM + +# ------------------------------------------------------------------------------------------------- +# Encoding format: 3RI2 +# ------------------------------------------------------------------------------------------------- +# ---------------------------------------------+-----+--------------+--------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ---------------------------------------------+-----+--------------+--------------+--------------- +# opcode |imm2 | rk | rj | rd +# ---------------------------------------------+-----+--------------+--------------+--------------- + +--- +# CHECK-LABEL: test_ALSL_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: alsl.w a0, a1, a2, 3 +name: test_ALSL_W +body: | + bb.0: + $r4 = ALSL_W $r5, $r6, 3 +... +--- +# CHECK-LABEL: test_ALSL_WU: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: alsl.wu a0, a1, a2, 1 +name: test_ALSL_WU +body: | + bb.0: + $r4 = ALSL_WU $r5, $r6, 1 +... +--- +# CHECK-LABEL: test_ALSL_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: alsl.d a0, a1, a2, 3 +name: test_ALSL_D +body: | + bb.0: + $r4 = ALSL_D $r5, $r6, 3 +... +--- +# CHECK-LABEL: test_BYTEPICK_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: bytepick.w a0, a1, a2, 0 +name: test_BYTEPICK_W +body: | + bb.0: + $r4 = BYTEPICK_W $r5, $r6, 0 +... + +# ------------------------------------------------------------------------------------------------- +# Encoding format: 3RI3 +# ------------------------------------------------------------------------------------------------- +# ------------------------------------------+--------+--------------+--------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ------------------------------------------+--------+--------------+--------------+--------------- +# opcode | imm3 | rk | rj | rd +# ------------------------------------------+--------+--------------+--------------+--------------- + +--- +# CHECK-LABEL: test_BYTEPICK_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: bytepick.d a0, a1, a2, 4 +name: test_BYTEPICK_D +body: | + bb.0: + $r4 = BYTEPICK_D $r5, $r6, 4 diff --git a/llvm/test/CodeGen/LoongArch/lit.local.cfg b/llvm/test/CodeGen/LoongArch/lit.local.cfg index 2b5a4893e686f..a54f5aeca4abb 100644 --- a/llvm/test/CodeGen/LoongArch/lit.local.cfg +++ b/llvm/test/CodeGen/LoongArch/lit.local.cfg @@ -1,2 +1,13 @@ +import os + +config.suffixes = ['.ll', '.mir', '.test', '.txt'] + +extract_section_path = os.path.join(config.llvm_src_root, + 'utils', 'extract-section.py') + +config.substitutions.append(('extract-section', + "'%s' %s %s" % (config.python_executable, + extract_section_path, '--bits-endian little'))) + if not 'LoongArch' in config.root.targets: config.unsupported = True diff --git a/llvm/test/CodeGen/LoongArch/misc.mir b/llvm/test/CodeGen/LoongArch/misc.mir new file mode 100644 index 0000000000000..3bece0766a2e3 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/misc.mir @@ -0,0 +1,200 @@ +# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefix=CHECK-ENC +# RUN: llc %s -mtriple=loongarch64 -start-after=prologepilog -O0 -filetype=asm -o - \ +# RUN: | FileCheck %s -check-prefix=CHECK-ASM + +# ------------------------------------------------------------------------------------------------- +# Encoding format: I15 +# ------------------------------------------------------------------------------------------------- +# ---------------------------------------------------+--------------------------------------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ---------------------------------------------------+--------------------------------------------- +# opcode | imm15 +# ---------------------------------------------------+--------------------------------------------- + +--- +# CHECK-LABEL: test_DBAR: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +# CHECK-ASM: dbar 0 +name: test_DBAR +body: | + bb.0: + DBAR 0 +... +--- +# CHECK-LABEL: test_IBAR: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +# CHECK-ASM: ibar 0 +name: test_IBAR +body: | + bb.0: + IBAR 0 +... +--- +# CHECK-LABEL: test_SYSCALL: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 +# CHECK-ASM: syscall 100 +name: test_SYSCALL +body: | + bb.0: + SYSCALL 100 +... +--- +# CHECK-LABEL: test_BREAK: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 +# CHECK-ASM: break 199 +name: test_BREAK +body: | + bb.0: + BREAK 199 +... + +# ------------------------------------------------------------------------------------------------- +# Encoding format: I26 +# ------------------------------------------------------------------------------------------------- +# ------------------+-----------------------------------------------+------------------------------ +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ------------------+-----------------------------------------------+------------------------------ +# opcode | imm26{15-0} | imm26{25-16} +# ------------------+-----------------------------------------------+------------------------------ + +--- +# CHECK-LABEL: test_B: +# CHECK-ENC: 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 +# CHECK-ASM: b 20 +name: test_B +body: | + bb.0: + B 20 +... +--- +# CHECK-LABEL: test_BL: +# CHECK-ENC: 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 +# CHECK-ASM: bl 34 +name: test_BL +body: | + bb.0: + BL 34 +... + +# -------------------------------------------------------------------------------------------------------- +# Encoding format: BSTR_W +# -------------------------------------------------------------------------------------------------------- +# ---------------------------------+--------------+---------+--------------+--------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ---------------------------------+--------------+---------+--------------+--------------+--------------- +# opcode{11-1} | msb |opcode{0}| lsb | rj | rd +# ---------------------------------+--------------+---------+--------------+--------------+--------------- + +--- +# CHECK-LABEL: test_BSTRINS_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: bstrins.w a0, a1, 7, 2 +name: test_BSTRINS_W +body: | + bb.0: + $r4 = BSTRINS_W $r5, 7, 2 +... +--- +# CHECK-LABEL: test_BSTRPICK_W: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: bstrpick.w a0, a1, 10, 4 +name: test_BSTRPICK_W +body: | + bb.0: + $r4 = BSTRPICK_W $r5, 10, 4 +... + +# ------------------------------------------------------------------------------------------------- +# Encoding format: BSTR_D +# ------------------------------------------------------------------------------------------------- +# ------------------------------+-----------------+-----------------+--------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ------------------------------+-----------------+-----------------+--------------+--------------- +# opcode | msb | lsb | rj | rd +# ------------------------------+-----------------+-----------------+--------------+--------------- + +--- +# CHECK-LABEL: test_BSTRINS_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: bstrins.d a0, a1, 7, 2 +name: test_BSTRINS_D +body: | + bb.0: + $r4 = BSTRINS_D $r5, 7, 2 +... +--- +# CHECK-LABEL: test_BSTRPICK_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0 +# CHECK-ASM: bstrpick.d a0, a1, 39, 22 +name: test_BSTRPICK_D +body: | + bb.0: + $r4 = BSTRPICK_D $r5, 39, 22 +... + +# ------------------------------------------------------------------------------------------------- +# Encoding format: ASRT +# ------------------------------------------------------------------------------------------------- +# ---------------------------------------------------+--------------+--------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ---------------------------------------------------+--------------+--------------+--------------- +# opcode | rk | rj | 0x0 +# ---------------------------------------------------+--------------+--------------+--------------- + +--- +# CHECK-LABEL: test_ASRTLE_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 +# CHECK-ASM: asrtle.d a0, a1 +name: test_ASRTLE_D +body: | + bb.0: + ASRTLE_D $r4, $r5 +... +--- +# CHECK-LABEL: test_ASRTGT_D: +# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 +# CHECK-ASM: asrtgt.d a0, a1 +name: test_ASRTGT_D +body: | + bb.0: + ASRTGT_D $r4, $r5 +... + +# ------------------------------------------------------------------------------------------------- +# Encoding format: PRELD +# ------------------------------------------------------------------------------------------------- +# ------------------------------+-----------------------------------+--------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ------------------------------+-----------------------------------+--------------+--------------- +# opcode | imm12 | rj | imm5 +# ------------------------------+-----------------------------------+--------------+--------------- + +--- +# CHECK-LABEL: test_PRELD: +# CHECK-ENC: 0 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 1 1 1 1 +# CHECK-ASM: preld 15, a0, 21 +name: test_PRELD +body: | + bb.0: + PRELD 15, $r4, 21 +... + +# ------------------------------------------------------------------------------------------------- +# Encoding format: PRELDX +# ------------------------------------------------------------------------------------------------- +# ---------------------------------------------------+--------------+--------------+--------------- +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +# ---------------------------------------------------+--------------+--------------+--------------- +# opcode | rk | rj | imm5 +# ---------------------------------------------------+--------------+--------------+--------------- + +--- +# CHECK-LABEL: test_PRELDX: +# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 +# CHECK-ASM: preldx 11, a0, a1 +name: test_PRELDX +body: | + bb.0: + PRELDX 11, $r4, $r5