diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir b/llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
deleted file mode 100644
index 34cec60d85691..0000000000000
--- a/llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
+++ /dev/null
@@ -1,106 +0,0 @@
-# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
-# RUN: | FileCheck -check-prefixes=OUTLINED,RV32I-MO %s
-# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
-# RUN: | FileCheck -check-prefixes=OUTLINED,RV64I-MO %s
-
-# CFIs are invisible (they can be outlined, but won't actually impact the outlining result) if there
-# is no need to unwind. CFIs will be stripped when we build outlined functions.
-
---- |
-  define void @func1(i32 %a, i32 %b) { ret void }
-
-  define void @func2(i32 %a, i32 %b) { ret void }
-
-  define void @func3(i32 %a, i32 %b) { ret void }
-...
----
-name:            func1
-tracksRegLiveness: true
-body:             |
-  bb.0:
-    liveins: $x10, $x11
-    ; RV32I-MO-LABEL: name: func1
-    ; RV32I-MO: liveins: $x10, $x11
-    ; RV32I-MO-NEXT: {{  $}}
-    ; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
-    ; RV32I-MO-NEXT: PseudoRET
-    ; RV64I-MO-LABEL: name: func1
-    ; RV64I-MO: liveins: $x10, $x11
-    ; RV64I-MO-NEXT: {{  $}}
-    ; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
-    ; RV64I-MO-NEXT: PseudoRET
-    $x10 = ORI $x10, 1023
-    CFI_INSTRUCTION offset $x1, 0
-    $x11 = ORI $x11, 1023
-    CFI_INSTRUCTION offset $x1, -4
-    $x12 = ADDI $x10, 17
-    CFI_INSTRUCTION offset $x1, -8
-    $x11 = AND $x12, $x11
-    CFI_INSTRUCTION offset $x1, -12
-    $x10 = SUB $x10, $x11
-    PseudoRET
-...
----
-name:            func2
-tracksRegLiveness: true
-body:             |
-  bb.0:
-    liveins: $x10, $x11
-    ; RV32I-MO-LABEL: name: func2
-    ; RV32I-MO: liveins: $x10, $x11
-    ; RV32I-MO-NEXT: {{  $}}
-    ; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
-    ; RV32I-MO-NEXT: PseudoRET
-    ; RV64I-MO-LABEL: name: func2
-    ; RV64I-MO: liveins: $x10, $x11
-    ; RV64I-MO-NEXT: {{  $}}
-    ; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
-    ; RV64I-MO-NEXT: PseudoRET
-    $x10 = ORI $x10, 1023
-    CFI_INSTRUCTION offset $x1, 0
-    $x11 = ORI $x11, 1023
-    CFI_INSTRUCTION offset $x1, -8
-    $x12 = ADDI $x10, 17
-    CFI_INSTRUCTION offset $x1, -4
-    $x11 = AND $x12, $x11
-    CFI_INSTRUCTION offset $x1, -12
-    $x10 = SUB $x10, $x11
-    PseudoRET
-...
----
-name:            func3
-tracksRegLiveness: true
-body:             |
-  bb.0:
-    liveins: $x10, $x11
-    ; RV32I-MO-LABEL: name: func3
-    ; RV32I-MO: liveins: $x10, $x11
-    ; RV32I-MO-NEXT: {{  $}}
-    ; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
-    ; RV32I-MO-NEXT: PseudoRET
-    ; RV64I-MO-LABEL: name: func3
-    ; RV64I-MO: liveins: $x10, $x11
-    ; RV64I-MO-NEXT: {{  $}}
-    ; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
-    ; RV64I-MO-NEXT: PseudoRET
-    $x10 = ORI $x10, 1023
-    CFI_INSTRUCTION offset $x1, -12
-    $x11 = ORI $x11, 1023
-    CFI_INSTRUCTION offset $x1, -8
-    $x12 = ADDI $x10, 17
-    CFI_INSTRUCTION offset $x1, -4
-    $x11 = AND $x12, $x11
-    CFI_INSTRUCTION offset $x1, 0
-    $x10 = SUB $x10, $x11
-    PseudoRET
-
-
-# OUTLINED-LABEL: name: OUTLINED_FUNCTION_0
-# OUTLINED: liveins: $x11, $x10, $x5
-# OUTLINED-NEXT: {{  $}}
-# OUTLINED-NEXT: $x10 = ORI $x10, 1023
-# OUTLINED-NEXT: $x11 = ORI $x11, 1023
-# OUTLINED-NEXT: $x12 = ADDI $x10, 17
-# OUTLINED-NEXT: $x11 = AND $x12, $x11
-# OUTLINED-NEXT: $x10 = SUB $x10, $x11
-# OUTLINED-NEXT: $x0 = JALR $x5, 0
diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-position.mir b/llvm/test/CodeGen/RISCV/machine-outliner-position.mir
deleted file mode 100644
index e6c101758a937..0000000000000
--- a/llvm/test/CodeGen/RISCV/machine-outliner-position.mir
+++ /dev/null
@@ -1,99 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
-# RUN: | FileCheck -check-prefixes=RV32I-MO %s
-# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
-# RUN: | FileCheck -check-prefixes=RV64I-MO %s
-
-# Position instructions are illegal to outline. The first instruction won't be outlined
-# because position instructions break the sequence.
-
---- |
-  define void @func1(i32 %a, i32 %b) { ret void }
-
-  define void @func2(i32 %a, i32 %b) { ret void }
-
-  define void @func3(i32 %a, i32 %b) { ret void }
-...
----
-name:            func1
-tracksRegLiveness: true
-body:             |
-  bb.0:
-    liveins: $x10, $x11
-    ; RV32I-MO-LABEL: name: func1
-    ; RV32I-MO: liveins: $x10, $x11
-    ; RV32I-MO-NEXT: {{  $}}
-    ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
-    ; RV32I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0>
-    ; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
-    ; RV32I-MO-NEXT: PseudoRET
-    ; RV64I-MO-LABEL: name: func1
-    ; RV64I-MO: liveins: $x10, $x11
-    ; RV64I-MO-NEXT: {{  $}}
-    ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
-    ; RV64I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0>
-    ; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
-    ; RV64I-MO-NEXT: PseudoRET
-    $x10 = ORI $x10, 1023
-    EH_LABEL <mcsymbol .Ltmp0>
-    $x11 = ORI $x11, 1023
-    $x12 = ADDI $x10, 17
-    $x11 = AND $x12, $x11
-    $x10 = SUB $x10, $x11
-    PseudoRET
-...
----
-name:            func2
-tracksRegLiveness: true
-body:             |
-  bb.0:
-    liveins: $x10, $x11
-    ; RV32I-MO-LABEL: name: func2
-    ; RV32I-MO: liveins: $x10, $x11
-    ; RV32I-MO-NEXT: {{  $}}
-    ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
-    ; RV32I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1>
-    ; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
-    ; RV32I-MO-NEXT: PseudoRET
-    ; RV64I-MO-LABEL: name: func2
-    ; RV64I-MO: liveins: $x10, $x11
-    ; RV64I-MO-NEXT: {{  $}}
-    ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
-    ; RV64I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1>
-    ; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
-    ; RV64I-MO-NEXT: PseudoRET
-    $x10 = ORI $x10, 1023
-    GC_LABEL <mcsymbol .Ltmp1>
-    $x11 = ORI $x11, 1023
-    $x12 = ADDI $x10, 17
-    $x11 = AND $x12, $x11
-    $x10 = SUB $x10, $x11
-    PseudoRET
-...
----
-name:            func3
-tracksRegLiveness: true
-body:             |
-  bb.0:
-    liveins: $x10, $x11
-    ; RV32I-MO-LABEL: name: func3
-    ; RV32I-MO: liveins: $x10, $x11
-    ; RV32I-MO-NEXT: {{  $}}
-    ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
-    ; RV32I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2>
-    ; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
-    ; RV32I-MO-NEXT: PseudoRET
-    ; RV64I-MO-LABEL: name: func3
-    ; RV64I-MO: liveins: $x10, $x11
-    ; RV64I-MO-NEXT: {{  $}}
-    ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
-    ; RV64I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2>
-    ; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
-    ; RV64I-MO-NEXT: PseudoRET
-    $x10 = ORI $x10, 1023
-    ANNOTATION_LABEL <mcsymbol .Ltmp2>
-    $x11 = ORI $x11, 1023
-    $x12 = ADDI $x10, 17
-    $x11 = AND $x12, $x11
-    $x10 = SUB $x10, $x11
-    PseudoRET
diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-throw.ll b/llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
deleted file mode 100644
index b0ac9c9da23a5..0000000000000
--- a/llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
+++ /dev/null
@@ -1,58 +0,0 @@
-; RUN: llc -verify-machineinstrs -enable-machine-outliner -mattr=+m -mtriple=riscv64 < %s | FileCheck %s
-
-; Ensure that we won't outline CFIs when they are needed in unwinding.
-
-define i32 @func1(i32 %x) #0 {
-; CHECK-LABEL: func1:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    call t0, OUTLINED_FUNCTION_0
-; CHECK-NEXT:    call __cxa_allocate_exception@plt
-; CHECK-NEXT:    sw s0, 0(a0)
-; CHECK-NEXT:    lui a1, %hi(_ZTIi)
-; CHECK-NEXT:    addi a1, a1, %lo(_ZTIi)
-; CHECK-NEXT:    li a2, 0
-; CHECK-NEXT:    call __cxa_throw@plt
-entry:
-  %mul = mul i32 %x, %x
-  %add = add i32 %mul, 1
-  %exception = tail call i8* @__cxa_allocate_exception(i64 4)
-  %0 = bitcast i8* %exception to i32*
-  store i32 %add, i32* %0
-  tail call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null)
-  unreachable
-}
-
-define i32 @func2(i32 %x) #0 {
-; CHECK-LABEL: func2:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    call t0, OUTLINED_FUNCTION_0
-; CHECK-NEXT:    call __cxa_allocate_exception@plt
-; CHECK-NEXT:    sw s0, 0(a0)
-; CHECK-NEXT:    lui a1, %hi(_ZTIi)
-; CHECK-NEXT:    addi a1, a1, %lo(_ZTIi)
-; CHECK-NEXT:    li a2, 0
-; CHECK-NEXT:    call __cxa_throw@plt
-entry:
-  %mul = mul i32 %x, %x
-  %add = add i32 %mul, 1
-  %exception = tail call i8* @__cxa_allocate_exception(i64 4)
-  %0 = bitcast i8* %exception to i32*
-  store i32 %add, i32* %0
-  tail call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null)
-  unreachable
-}
-
-; CHECK-LABEL: OUTLINED_FUNCTION_0:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    sd ra, 8(sp)
-; CHECK-NEXT:    sd s0, 0(sp)
-; CHECK-NEXT:    mulw a0, a0, a0
-; CHECK-NEXT:    addiw s0, a0, 1
-; CHECK-NEXT:    li a0, 4
-
-@_ZTIi = external constant i8*
-declare i8* @__cxa_allocate_exception(i64)
-declare void @__cxa_throw(i8*, i8*, i8*)
-
-attributes #0 = { minsize noreturn }