diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index 01323abfd475d..4ce9243ae32a2 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -640,7 +640,7 @@ def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; let isCommutable = 1 in -defm ADD8 : XOForm_1rx<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), +defm ADD8 : XOForm_1rx<31, 266, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), "add", "$rT, $rA, $rB", IIC_IntSimple, [(set i64:$rT, (add i64:$rA, i64:$rB))]>; // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the @@ -719,7 +719,7 @@ defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), "subfc", "$rT, $rA, $rB", IIC_IntGeneral, [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, PPC970_DGroup_Cracked; -defm SUBF8 : XOForm_1rx<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), +defm SUBF8 : XOForm_1rx<31, 40, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), "subf", "$rT, $rA, $rB", IIC_IntGeneral, [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), @@ -963,7 +963,7 @@ defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, isPPC64, Requires<[HasExtDiv]>; let isCommutable = 1 in -defm MULLD : XOForm_1rx<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), +defm MULLD : XOForm_1rx<31, 233, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), "mulld", "$rT, $rA, $rB", IIC_IntMulHD, [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; let Interpretation64Bit = 1, isCodeGenOnly = 1 in diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td index 91b507ea6c4cc..f7e4c0708d7de 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td @@ -889,7 +889,7 @@ class XForm_16b opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, } class XForm_htm0 opcode, bits<10> xo, dag OOL, dag IOL, - string asmstr, InstrItinClass itin, list pattern> + string asmstr, InstrItinClass itin> : I { bit R; @@ -903,7 +903,7 @@ class XForm_htm0 opcode, bits<10> xo, dag OOL, dag IOL, } class XForm_htm1 opcode, bits<10> xo, dag OOL, dag IOL, - string asmstr, InstrItinClass itin, list pattern> + string asmstr, InstrItinClass itin> : I { bit A; @@ -916,7 +916,7 @@ class XForm_htm1 opcode, bits<10> xo, dag OOL, dag IOL, } class XForm_htm2 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, - InstrItinClass itin, list pattern> + InstrItinClass itin> : I { bit L; @@ -930,7 +930,7 @@ class XForm_htm2 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, } class XForm_htm3 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, - InstrItinClass itin, list pattern> + InstrItinClass itin> : I { bits<3> BF; diff --git a/llvm/lib/Target/PowerPC/PPCInstrHTM.td b/llvm/lib/Target/PowerPC/PPCInstrHTM.td index e59a08774dc58..ec1c397ff57f8 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrHTM.td +++ b/llvm/lib/Target/PowerPC/PPCInstrHTM.td @@ -29,10 +29,10 @@ let Predicates = [HasHTM] in { let Defs = [CR0] in { def TBEGIN : XForm_htm0 <31, 654, - (outs), (ins u1imm:$R), "tbegin. $R", IIC_SprMTSPR, []>; + (outs), (ins u1imm:$R), "tbegin. $R", IIC_SprMTSPR>; def TEND : XForm_htm1 <31, 686, - (outs), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR, []>; + (outs), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR>; def TABORT : XForm_base_r3xo <31, 910, (outs), (ins gprc:$A), "tabort. $A", IIC_SprMTSPR, @@ -62,7 +62,7 @@ def TABORTDCI : XForm_base_r3xo <31, 878, isRecordForm; def TSR : XForm_htm2 <31, 750, - (outs), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR, []>, + (outs), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR>, isRecordForm; def TRECLAIM : XForm_base_r3xo <31, 942, @@ -84,7 +84,7 @@ def TRECHKPT : XForm_base_r3xo <31, 1006, } def TCHECK : XForm_htm3 <31, 718, - (outs crrc:$BF), (ins), "tcheck $BF", IIC_SprMTSPR, []>; + (outs crrc:$BF), (ins), "tcheck $BF", IIC_SprMTSPR>; // Builtins // All HTM instructions, with the exception of tcheck, set CR0 with the diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index c87beef5c99cd..03434ec000189 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -1271,7 +1271,7 @@ multiclass XOForm_1r opcode, bits<9> xo, bit oe, dag OOL, dag IOL, // Multiclass for instructions which have a record overflow form as well // as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.) -multiclass XOForm_1rx opcode, bits<9> xo, bit oe, dag OOL, dag IOL, +multiclass XOForm_1rx opcode, bits<9> xo, dag OOL, dag IOL, string asmbase, string asmstr, InstrItinClass itin, list pattern> { let BaseName = asmbase in { @@ -3171,7 +3171,7 @@ def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$rT), let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. // XO-Form instructions. Arithmetic instructions that can set overflow bit let isCommutable = 1 in -defm ADD4 : XOForm_1rx<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), +defm ADD4 : XOForm_1rx<31, 266, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), "add", "$rT, $rA, $rB", IIC_IntSimple, [(set i32:$rT, (add i32:$rA, i32:$rB))]>; let isCodeGenOnly = 1 in @@ -3205,11 +3205,11 @@ defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU, [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; -defm MULLW : XOForm_1rx<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), +defm MULLW : XOForm_1rx<31, 235, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), "mullw", "$rT, $rA, $rB", IIC_IntMulHW, [(set i32:$rT, (mul i32:$rA, i32:$rB))]>; } // isCommutable -defm SUBF : XOForm_1rx<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), +defm SUBF : XOForm_1rx<31, 40, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), "subf", "$rT, $rA, $rB", IIC_IntGeneral, [(set i32:$rT, (sub i32:$rB, i32:$rA))]>; defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td index 8738426bf3f68..0b5c9bc2b7225 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -621,7 +621,7 @@ class 8LS_DForm_R_XTp5_SI34_MEM opcode, dag OOL, dag IOL, string asmstr, let Inst{48-63} = D_RA{15-0}; // D } -multiclass 8LS_DForm_R_XTp5_SI34_MEM_p pref, bits<6> opcode, dag OOL, +multiclass 8LS_DForm_R_XTp5_SI34_MEM_p opcode, dag OOL, dag IOL, dag PCRel_IOL, string asmstr, InstrItinClass itin> { def NAME : 8LS_DForm_R_XTp5_SI34_MEM; } let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs] in { defm PSTXVP : - 8LS_DForm_R_XTp5_SI34_MEM_p<1, 62, (outs), (ins vsrprc:$XTp, memri34:$D_RA), + 8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, memri34:$D_RA), (ins vsrprc:$XTp, memri34_pcrel:$D_RA), "pstxvp $XTp, $D_RA", IIC_LdStLFD>; }