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[SystemZ] set 'guessInstructionProperties = 0' and set flags as needed.
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This has proven a healthy exercise, as many cases of incorrect instruction
flags were corrected in the process. As part of this, IntrWriteMem was added
to several SystemZ instrinsics.

Furthermore, a bug was exposed in TwoAddress with this change (as incorrect
hasSideEffects flags were removed and instructions could now be sunk), and
the test case for that bugfix (r319646) is included here as
test/CodeGen/SystemZ/twoaddr-sink.ll.

One temporary test regression (one extra copy) which will hopefully go away
in upcoming patches for similar cases:
test/CodeGen/SystemZ/vec-trunc-to-i1.ll

Review: Ulrich Weigand.
https://reviews.llvm.org/D40437

llvm-svn: 319756
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@JonPsson
JonPsson committed Dec 5, 2017
1 parent 7c40f93 commit b5b91cd
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Showing 11 changed files with 168 additions and 150 deletions.
16 changes: 6 additions & 10 deletions llvm/include/llvm/IR/IntrinsicsSystemZ.td
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Original file line number Diff line number Diff line change
Expand Up @@ -198,14 +198,14 @@ multiclass SystemZQuaternaryIntCCBHF {

let TargetPrefix = "s390" in {
def int_s390_tbegin : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrNoDuplicate]>;
[IntrNoDuplicate, IntrWriteMem]>;

def int_s390_tbegin_nofloat : Intrinsic<[llvm_i32_ty],
[llvm_ptr_ty, llvm_i32_ty],
[IntrNoDuplicate]>;
[IntrNoDuplicate, IntrWriteMem]>;

def int_s390_tbeginc : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
[IntrNoDuplicate]>;
[IntrNoDuplicate, IntrWriteMem]>;

def int_s390_tabort : Intrinsic<[], [llvm_i64_ty],
[IntrNoReturn, Throws]>;
Expand All @@ -217,7 +217,7 @@ let TargetPrefix = "s390" in {
Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;

def int_s390_ntstg : Intrinsic<[], [llvm_i64_ty, llvm_ptr64_ty],
[IntrArgMemOnly]>;
[IntrArgMemOnly, IntrWriteMem]>;

def int_s390_ppa_txassist : GCCBuiltin<"__builtin_tx_assist">,
Intrinsic<[], [llvm_i32_ty]>;
Expand Down Expand Up @@ -260,9 +260,7 @@ let TargetPrefix = "s390" in {

def int_s390_vstl : GCCBuiltin<"__builtin_s390_vstl">,
Intrinsic<[], [llvm_v16i8_ty, llvm_i32_ty, llvm_ptr_ty],
// In fact write-only but there's no property
// for that.
[IntrArgMemOnly]>;
[IntrArgMemOnly, IntrWriteMem]>;

defm int_s390_vupl : SystemZUnaryExtBHWF<"vupl">;
defm int_s390_vupll : SystemZUnaryExtBHF<"vupll">;
Expand Down Expand Up @@ -413,9 +411,7 @@ let TargetPrefix = "s390" in {

def int_s390_vstrl : GCCBuiltin<"__builtin_s390_vstrl">,
Intrinsic<[], [llvm_v16i8_ty, llvm_i32_ty, llvm_ptr_ty],
// In fact write-only but there's no property
// for that.
[IntrArgMemOnly]>;
[IntrArgMemOnly, IntrWriteMem]>;
}

//===----------------------------------------------------------------------===//
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/SystemZ/SystemZ.td
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Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@ include "SystemZInstrHFP.td"
include "SystemZInstrDFP.td"
include "SystemZInstrSystem.td"

def SystemZInstrInfo : InstrInfo {}
def SystemZInstrInfo : InstrInfo { let guessInstructionProperties = 0; }

//===----------------------------------------------------------------------===//
// Assembly parser
Expand Down
34 changes: 19 additions & 15 deletions llvm/lib/Target/SystemZ/SystemZInstrFP.td
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Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,9 @@
//
//===----------------------------------------------------------------------===//

// TODO: Most floating-point instructions (except for simple moves and the
// like) can raise exceptions -- should they have hasSideEffects=1 ?

//===----------------------------------------------------------------------===//
// Select instructions
//===----------------------------------------------------------------------===//
Expand All @@ -29,22 +32,20 @@ defm CondStoreF64 : CondStores<FP64, nonvolatile_store,
//===----------------------------------------------------------------------===//

// Load zero.
let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1 in {
let isAsCheapAsAMove = 1, isMoveImm = 1 in {
def LZER : InherentRRE<"lzer", 0xB374, FP32, fpimm0>;
def LZDR : InherentRRE<"lzdr", 0xB375, FP64, fpimm0>;
def LZXR : InherentRRE<"lzxr", 0xB376, FP128, fpimm0>;
}

// Moves between two floating-point registers.
let hasSideEffects = 0 in {
def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>;
def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>;
def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>;
def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>;

// For z13 we prefer LDR over LER to avoid partial register dependencies.
let isCodeGenOnly = 1 in
def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>;
}
// For z13 we prefer LDR over LER to avoid partial register dependencies.
let isCodeGenOnly = 1 in
def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>;

// Moves between two floating-point registers that also set the condition
// codes.
Expand Down Expand Up @@ -130,7 +131,7 @@ defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>;
// Load instructions
//===----------------------------------------------------------------------===//

let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in {
defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>;
defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>;

Expand All @@ -150,7 +151,7 @@ let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
// Store instructions
//===----------------------------------------------------------------------===//

let SimpleBDXStore = 1 in {
let SimpleBDXStore = 1, mayStore = 1 in {
defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>;
defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>;

Expand Down Expand Up @@ -525,11 +526,14 @@ let Defs = [CC], CCValues = 0xC in {
//===----------------------------------------------------------------------===//

let hasSideEffects = 1 in {
def EFPC : InherentRRE<"efpc", 0xB38C, GR32, int_s390_efpc>;
def STFPC : StoreInherentS<"stfpc", 0xB29C, storei<int_s390_efpc>, 4>;
let mayLoad = 1, mayStore = 1 in {
// TODO: EFPC and SFPC do not touch memory at all
def EFPC : InherentRRE<"efpc", 0xB38C, GR32, int_s390_efpc>;
def STFPC : StoreInherentS<"stfpc", 0xB29C, storei<int_s390_efpc>, 4>;

def SFPC : SideEffectUnaryRRE<"sfpc", 0xB384, GR32, int_s390_sfpc>;
def LFPC : SideEffectUnaryS<"lfpc", 0xB29D, loadu<int_s390_sfpc>, 4>;
def SFPC : SideEffectUnaryRRE<"sfpc", 0xB384, GR32, int_s390_sfpc>;
def LFPC : SideEffectUnaryS<"lfpc", 0xB29D, loadu<int_s390_sfpc>, 4>;
}

def SFASR : SideEffectUnaryRRE<"sfasr", 0xB385, GR32, null_frag>;
def LFAS : SideEffectUnaryS<"lfas", 0xB2BD, null_frag, 4>;
Expand Down
14 changes: 11 additions & 3 deletions llvm/lib/Target/SystemZ/SystemZInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,10 @@ class InstSystemZ<int size, dag outs, dag ins, string asmstr,
let Pattern = pattern;
let AsmString = asmstr;

let hasSideEffects = 0;
let mayLoad = 0;
let mayStore = 0;

// Some instructions come in pairs, one having a 12-bit displacement
// and the other having a 20-bit displacement. Both instructions in
// the pair have the same DispKey and their DispSizes are "12" and "20"
Expand Down Expand Up @@ -2100,11 +2104,14 @@ class CondBranchRXY<string mnemonic, bits<16> opcode>
: InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr20only:$XBD2),
!subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
let CCMaskFirst = 1;
let mayLoad = 1;
}

class AsmCondBranchRXY<string mnemonic, bits<16> opcode>
: InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
mnemonic#"\t$M1, $XBD2", []>;
mnemonic#"\t$M1, $XBD2", []> {
let mayLoad = 1;
}

class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
SDPatternOperator operator = null_frag>
Expand All @@ -2113,6 +2120,7 @@ class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
[(operator (load bdxaddr20only:$XBD2))]> {
let isAsmParserOnly = V.alternate;
let M1 = V.ccmask;
let mayLoad = 1;
}

class CmpBranchRIEa<string mnemonic, bits<16> opcode,
Expand Down Expand Up @@ -2784,7 +2792,6 @@ multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>;
}


class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls, bits<5> bytes,
AddressingMode mode = bdxaddr12only>
Expand Down Expand Up @@ -4688,7 +4695,8 @@ class SelectWrapper<ValueType vt, RegisterOperand cls>
// Stores $new to $addr if $cc is true ("" case) or false (Inv case).
multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
SDPatternOperator load, AddressingMode mode> {
let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
let Defs = [CC], Uses = [CC], usesCustomInserter = 1,
mayLoad = 1, mayStore = 1 in {
def "" : Pseudo<(outs),
(ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
[(store (z_select_ccmask cls:$new, (load mode:$addr),
Expand Down
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