diff --git a/llvm/include/llvm/ADT/SparseSet.h b/llvm/include/llvm/ADT/SparseSet.h index 4a999e6b4c69a..c9895d7475404 100644 --- a/llvm/include/llvm/ADT/SparseSet.h +++ b/llvm/include/llvm/ADT/SparseSet.h @@ -203,7 +203,6 @@ class SparseSet { /// iterator findIndex(unsigned Idx) { assert(Idx < Universe && "Key out of range"); - assert(Sparse != nullptr && "Invalid sparse type"); const unsigned Stride = std::numeric_limits::max() + 1u; for (unsigned i = Sparse[Idx], e = size(); i < e; i += Stride) { const unsigned FoundIdx = ValIndexOf(Dense[i]); diff --git a/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h b/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h index 7a8ee691c034f..0d6d8a31317bf 100644 --- a/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h +++ b/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h @@ -100,7 +100,7 @@ template class ValuePool { auto P = std::make_shared(*this, std::move(ValueKey)); EntrySet.insert(P.get()); - return PoolRef(P, &P->getValue()); + return PoolRef(std::move(P), &P->getValue()); } }; diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index 62083b64db922..620fdfc9f754d 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -1135,7 +1135,6 @@ inline SDValue::SDValue(SDNode *node, unsigned resno) } inline unsigned SDValue::getOpcode() const { - assert(Node != nullptr && "Invalid Node"); return Node->getOpcode(); } diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 71207ed68744c..0a803d8a1405b 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -1273,7 +1273,6 @@ AsmPrinter::getFunctionCFISectionType(const Function &F) const { F.needsUnwindTableEntry()) return CFISection::EH; - assert(MMI != nullptr && "Invalid machine module info"); if (MMI->hasDebugInfo() || TM.Options.ForceDwarfFrameSection) return CFISection::Debug; diff --git a/llvm/lib/CodeGen/ScheduleDAG.cpp b/llvm/lib/CodeGen/ScheduleDAG.cpp index 14ec41920e3e6..ef886ad14649a 100644 --- a/llvm/lib/CodeGen/ScheduleDAG.cpp +++ b/llvm/lib/CodeGen/ScheduleDAG.cpp @@ -724,8 +724,6 @@ void ScheduleDAGTopologicalSort::AddSUnitWithoutPredecessors(const SUnit *SU) { bool ScheduleDAGTopologicalSort::IsReachable(const SUnit *SU, const SUnit *TargetSU) { - assert(TargetSU != nullptr && "Invalid target SUnit"); - assert(SU != nullptr && "Invalid SUnit"); FixOrder(); // If insertion of the edge SU->TargetSU would create a cycle // then there is a path from TargetSU to SU. diff --git a/llvm/lib/CodeGen/ValueTypes.cpp b/llvm/lib/CodeGen/ValueTypes.cpp index d514e1642e29d..1b317bd0d7902 100644 --- a/llvm/lib/CodeGen/ValueTypes.cpp +++ b/llvm/lib/CodeGen/ValueTypes.cpp @@ -571,7 +571,6 @@ Type *EVT::getTypeForEVT(LLVMContext &Context) const { /// pointers as MVT::iPTR. If HandleUnknown is true, unknown types are returned /// as Other, otherwise they are invalid. MVT MVT::getVT(Type *Ty, bool HandleUnknown){ - assert(Ty != nullptr && "Invalid type"); switch (Ty->getTypeID()) { default: if (HandleUnknown) return MVT(MVT::Other); diff --git a/llvm/lib/IR/Mangler.cpp b/llvm/lib/IR/Mangler.cpp index 8d9880ecba58e..93d5639a00c19 100644 --- a/llvm/lib/IR/Mangler.cpp +++ b/llvm/lib/IR/Mangler.cpp @@ -119,7 +119,6 @@ static void addByteCountSuffix(raw_ostream &OS, const Function *F, void Mangler::getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const { ManglerPrefixTy PrefixTy = Default; - assert(GV != nullptr && "Invalid Global Value"); if (GV->hasPrivateLinkage()) { if (CannotUsePrivateLabel) PrefixTy = LinkerPrivate; diff --git a/llvm/lib/TableGen/Record.cpp b/llvm/lib/TableGen/Record.cpp index 07776cb3995e3..df1a4d47ff96e 100644 --- a/llvm/lib/TableGen/Record.cpp +++ b/llvm/lib/TableGen/Record.cpp @@ -318,11 +318,8 @@ RecTy *llvm::resolveTypes(RecTy *T1, RecTy *T2) { return resolveRecordTypes(RecTy1, RecTy2); } - assert(T1 != nullptr && "Invalid record type"); if (T1->typeIsConvertibleTo(T2)) return T2; - - assert(T2 != nullptr && "Invalid record type"); if (T2->typeIsConvertibleTo(T1)) return T1; diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 7458df7fb24d7..004104c860fd7 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -3603,7 +3603,6 @@ static unsigned getLoadStoreRegOpcode(Register Reg, bool HasAVX512 = STI.hasAVX512(); bool HasVLX = STI.hasVLX(); - assert(RC != nullptr && "Invalid target register class"); switch (STI.getRegisterInfo()->getSpillSize(*RC)) { default: llvm_unreachable("Unknown spill size"); diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp index 84c5559e5f00d..fc32ebc2c0e40 100644 --- a/llvm/utils/TableGen/GlobalISelEmitter.cpp +++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp @@ -3958,7 +3958,6 @@ Expected GlobalISelEmitter::addBuiltinPredicates( } } - assert(SrcGIEquivOrNull != nullptr && "Invalid SrcGIEquivOrNull value"); // No check required. We already did it by swapping the opcode. if (!SrcGIEquivOrNull->isValueUnset("IfSignExtend") && Predicate.isSignExtLoad())