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[Peephole] rewrite INSERT_SUBREG to SUBREG_TO_REG if upper bits zero
Restrict the 32-bit form of an instruction of integer as too many test cases will be clobber as the register number updated. From %reg = INSERT_SUBREG %reg, %subreg, subidx To %reg:subidx = SUBREG_TO_REG 0, %subreg, subidx Try to prefix the redundant mov instruction at D132325 as the SUBREG_TO_REG should not generate code. Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D132939
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Original file line number | Diff line number | Diff line change |
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py | ||
# RUN: llc -run-pass=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux -verify-machineinstrs %s | FileCheck %s | ||
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--- | | ||
define i64 @loop2(i32 noundef %width) { | ||
entry: | ||
%add = add i32 %width, -1 | ||
%zext = zext i32 %add to i64 | ||
%shl = shl nuw nsw i64 %zext, 1 | ||
ret i64 %shl | ||
} | ||
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||
... | ||
--- | ||
--- | ||
name: loop2 | ||
alignment: 4 | ||
tracksRegLiveness: true | ||
registers: | ||
- { id: 0, class: gpr32common, preferred-register: '' } | ||
- { id: 1, class: gpr32common, preferred-register: '' } | ||
- { id: 2, class: gpr64, preferred-register: '' } | ||
- { id: 3, class: gpr64all, preferred-register: '' } | ||
- { id: 4, class: gpr64, preferred-register: '' } | ||
liveins: | ||
- { reg: '$w0', virtual-reg: '%0' } | ||
body: | | ||
bb.0.entry: | ||
liveins: $w0 | ||
; CHECK-LABEL: name: loop2 | ||
; CHECK: liveins: $w0 | ||
; CHECK-NEXT: {{ $}} | ||
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w0 | ||
; CHECK-NEXT: [[SUBWri:%[0-9]+]]:gpr32common = SUBWri [[COPY]], 1, 0 | ||
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF | ||
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, killed [[SUBWri]], %subreg.sub_32 | ||
; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = nuw nsw UBFMXri killed [[SUBREG_TO_REG]], 63, 31 | ||
; CHECK-NEXT: $x0 = COPY [[UBFMXri]] | ||
; CHECK-NEXT: RET_ReallyLR implicit $x0 | ||
%0:gpr32common = COPY $w0 | ||
%1:gpr32common = SUBWri %0, 1, 0 | ||
%3:gpr64all = IMPLICIT_DEF | ||
%2:gpr64 = INSERT_SUBREG %3, killed %1, %subreg.sub_32 | ||
%4:gpr64 = nuw nsw UBFMXri killed %2, 63, 31 | ||
$x0 = COPY %4 | ||
RET_ReallyLR implicit $x0 |