diff --git a/llvm/include/llvm/CodeGen/LiveIntervals.h b/llvm/include/llvm/CodeGen/LiveIntervals.h index f4bc26b4466725..1a6b59a8959e20 100644 --- a/llvm/include/llvm/CodeGen/LiveIntervals.h +++ b/llvm/include/llvm/CodeGen/LiveIntervals.h @@ -114,8 +114,8 @@ class VirtRegMap; LiveInterval &getInterval(Register Reg) { if (hasInterval(Reg)) return *VirtRegIntervals[Reg.id()]; - else - return createAndComputeVirtRegInterval(Reg); + + return createAndComputeVirtRegInterval(Reg); } const LiveInterval &getInterval(Register Reg) const { @@ -142,14 +142,14 @@ class VirtRegMap; } /// Interval removal. - void removeInterval(unsigned Reg) { + void removeInterval(Register Reg) { delete VirtRegIntervals[Reg]; VirtRegIntervals[Reg] = nullptr; } /// Given a register and an instruction, adds a live segment from that /// instruction to the end of its MBB. - LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg, + LiveInterval::Segment addSegmentToEndOfBlock(Register Reg, MachineInstr &startInst); /// After removing some uses of a register, shrink its live range to just @@ -167,7 +167,7 @@ class VirtRegMap; /// the lane mask of the subregister range. /// This may leave the subrange empty which needs to be cleaned up with /// LiveInterval::removeEmptySubranges() afterwards. - void shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg); + void shrinkToUses(LiveInterval::SubRange &SR, Register Reg); /// Extend the live range \p LR to reach all points in \p Indices. The /// points in the \p Indices array must be jointly dominated by the union @@ -463,7 +463,7 @@ class VirtRegMap; bool computeDeadValues(LiveInterval &LI, SmallVectorImpl *dead); - static LiveInterval* createInterval(unsigned Reg); + static LiveInterval *createInterval(Register Reg); void printInstrs(raw_ostream &O) const; void dumpInstrs() const; @@ -474,7 +474,7 @@ class VirtRegMap; using ShrinkToUsesWorkList = SmallVector, 16>; void extendSegmentsToUses(LiveRange &Segments, - ShrinkToUsesWorkList &WorkList, unsigned Reg, + ShrinkToUsesWorkList &WorkList, Register Reg, LaneBitmask LaneMask); /// Helper function for repairIntervalsInRange(), walks backwards and @@ -484,7 +484,7 @@ class VirtRegMap; void repairOldRegInRange(MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, const SlotIndex endIdx, LiveRange &LR, - unsigned Reg, + Register Reg, LaneBitmask LaneMask = LaneBitmask::getAll()); class HMEditor; diff --git a/llvm/include/llvm/CodeGen/LiveVariables.h b/llvm/include/llvm/CodeGen/LiveVariables.h index 815f779e4f426f..9b0667bbbeb01b 100644 --- a/llvm/include/llvm/CodeGen/LiveVariables.h +++ b/llvm/include/llvm/CodeGen/LiveVariables.h @@ -105,8 +105,7 @@ class LiveVariables : public MachineFunctionPass { /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in /// MBB, it is not considered live in. - bool isLiveIn(const MachineBasicBlock &MBB, - unsigned Reg, + bool isLiveIn(const MachineBasicBlock &MBB, Register Reg, MachineRegisterInfo &MRI); void dump() const; @@ -149,25 +148,25 @@ class LiveVariables : public MachineFunctionPass { /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the /// uses. Pay special attention to the sub-register uses which may come below /// the last use of the whole register. - bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI); + bool HandlePhysRegKill(Register Reg, MachineInstr *MI); /// HandleRegMask - Call HandlePhysRegKill for all registers clobbered by Mask. void HandleRegMask(const MachineOperand&); - void HandlePhysRegUse(unsigned Reg, MachineInstr &MI); - void HandlePhysRegDef(unsigned Reg, MachineInstr *MI, + void HandlePhysRegUse(Register Reg, MachineInstr &MI); + void HandlePhysRegDef(Register Reg, MachineInstr *MI, SmallVectorImpl &Defs); void UpdatePhysRegDefs(MachineInstr &MI, SmallVectorImpl &Defs); /// FindLastRefOrPartRef - Return the last reference or partial reference of /// the specified register. - MachineInstr *FindLastRefOrPartRef(unsigned Reg); + MachineInstr *FindLastRefOrPartRef(Register Reg); /// FindLastPartialDef - Return the last partial def of the specified /// register. Also returns the sub-registers that're defined by the /// instruction. - MachineInstr *FindLastPartialDef(unsigned Reg, - SmallSet &PartDefRegs); + MachineInstr *FindLastPartialDef(Register Reg, + SmallSet &PartDefRegs); /// analyzePHINodes - Gather information about the PHI nodes in here. In /// particular, we want to map the variable information of a virtual @@ -184,21 +183,21 @@ class LiveVariables : public MachineFunctionPass { /// RegisterDefIsDead - Return true if the specified instruction defines the /// specified register, but that definition is dead. - bool RegisterDefIsDead(MachineInstr &MI, unsigned Reg) const; + bool RegisterDefIsDead(MachineInstr &MI, Register Reg) const; //===--------------------------------------------------------------------===// // API to update live variable information /// replaceKillInstruction - Update register kill info by replacing a kill /// instruction with a new one. - void replaceKillInstruction(unsigned Reg, MachineInstr &OldMI, + void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI); /// addVirtualRegisterKilled - Add information about the fact that the /// specified register is killed after being used by the specified /// instruction. If AddIfNotFound is true, add a implicit operand if it's /// not found. - void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr &MI, + void addVirtualRegisterKilled(Register IncomingReg, MachineInstr &MI, bool AddIfNotFound = false) { if (MI.addRegisterKilled(IncomingReg, TRI, AddIfNotFound)) getVarInfo(IncomingReg).Kills.push_back(&MI); @@ -208,14 +207,14 @@ class LiveVariables : public MachineFunctionPass { /// register from the live variable information. Returns true if the /// variable was marked as killed by the specified instruction, /// false otherwise. - bool removeVirtualRegisterKilled(unsigned reg, MachineInstr &MI) { - if (!getVarInfo(reg).removeKill(MI)) + bool removeVirtualRegisterKilled(Register Reg, MachineInstr &MI) { + if (!getVarInfo(Reg).removeKill(MI)) return false; bool Removed = false; for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (MO.isReg() && MO.isKill() && MO.getReg() == reg) { + if (MO.isReg() && MO.isKill() && MO.getReg() == Reg) { MO.setIsKill(false); Removed = true; break; @@ -234,7 +233,7 @@ class LiveVariables : public MachineFunctionPass { /// addVirtualRegisterDead - Add information about the fact that the specified /// register is dead after being used by the specified instruction. If /// AddIfNotFound is true, add a implicit operand if it's not found. - void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr &MI, + void addVirtualRegisterDead(Register IncomingReg, MachineInstr &MI, bool AddIfNotFound = false) { if (MI.addRegisterDead(IncomingReg, TRI, AddIfNotFound)) getVarInfo(IncomingReg).Kills.push_back(&MI); @@ -244,14 +243,14 @@ class LiveVariables : public MachineFunctionPass { /// register from the live variable information. Returns true if the /// variable was marked dead at the specified instruction, false /// otherwise. - bool removeVirtualRegisterDead(unsigned reg, MachineInstr &MI) { - if (!getVarInfo(reg).removeKill(MI)) + bool removeVirtualRegisterDead(Register Reg, MachineInstr &MI) { + if (!getVarInfo(Reg).removeKill(MI)) return false; bool Removed = false; for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (MO.isReg() && MO.isDef() && MO.getReg() == reg) { + if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) { MO.setIsDead(false); Removed = true; break; @@ -270,7 +269,7 @@ class LiveVariables : public MachineFunctionPass { /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL /// register. - VarInfo &getVarInfo(unsigned RegIdx); + VarInfo &getVarInfo(Register Reg); void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock, MachineBasicBlock *BB); @@ -278,17 +277,17 @@ class LiveVariables : public MachineFunctionPass { MachineBasicBlock *BB, SmallVectorImpl &WorkList); - void HandleVirtRegDef(unsigned reg, MachineInstr &MI); - void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, MachineInstr &MI); + void HandleVirtRegDef(Register reg, MachineInstr &MI); + void HandleVirtRegUse(Register reg, MachineBasicBlock *MBB, MachineInstr &MI); - bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) { + bool isLiveIn(Register Reg, const MachineBasicBlock &MBB) { return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI); } /// isLiveOut - Determine if Reg is live out from MBB, when not considering /// PHI nodes. This means that Reg is either killed by a successor block or /// passed through one. - bool isLiveOut(unsigned Reg, const MachineBasicBlock &MBB); + bool isLiveOut(Register Reg, const MachineBasicBlock &MBB); /// addNewBlock - Add a new basic block BB between DomBB and SuccBB. All /// variables that are live out of DomBB and live into SuccBB will be marked @@ -304,10 +303,10 @@ class LiveVariables : public MachineFunctionPass { std::vector> &LiveInSets); /// isPHIJoin - Return true if Reg is a phi join register. - bool isPHIJoin(unsigned Reg) { return PHIJoins.test(Reg); } + bool isPHIJoin(Register Reg) { return PHIJoins.test(Reg.id()); } /// setPHIJoin - Mark Reg as a phi join register. - void setPHIJoin(unsigned Reg) { PHIJoins.set(Reg); } + void setPHIJoin(Register Reg) { PHIJoins.set(Reg.id()); } }; } // End llvm namespace diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp index e8ceb6e2fe4bba..d029a1daa26a6d 100644 --- a/llvm/lib/CodeGen/LiveIntervals.cpp +++ b/llvm/lib/CodeGen/LiveIntervals.cpp @@ -159,7 +159,7 @@ void LiveIntervals::print(raw_ostream &OS, const Module* ) const { // Dump the virtregs. for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { - unsigned Reg = Register::index2VirtReg(i); + Register Reg = Register::index2VirtReg(i); if (hasInterval(Reg)) OS << getInterval(Reg) << '\n'; } @@ -183,7 +183,7 @@ LLVM_DUMP_METHOD void LiveIntervals::dumpInstrs() const { } #endif -LiveInterval* LiveIntervals::createInterval(unsigned reg) { +LiveInterval *LiveIntervals::createInterval(Register reg) { float Weight = Register::isPhysicalRegister(reg) ? huge_valf : 0.0F; return new LiveInterval(reg, Weight); } @@ -199,7 +199,7 @@ bool LiveIntervals::computeVirtRegInterval(LiveInterval &LI) { void LiveIntervals::computeVirtRegs() { for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { - unsigned Reg = Register::index2VirtReg(i); + Register Reg = Register::index2VirtReg(i); if (MRI->reg_nodbg_empty(Reg)) continue; LiveInterval &LI = createEmptyInterval(Reg); @@ -286,7 +286,7 @@ void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) { bool IsRootReserved = true; for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true); Super.isValid(); ++Super) { - unsigned Reg = *Super; + MCRegister Reg = *Super; if (!MRI->reg_empty(Reg)) LICalc->createDeadDefs(LR, Reg); // A register unit is considered reserved if all its roots and all their @@ -305,7 +305,7 @@ void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) { for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) { for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true); Super.isValid(); ++Super) { - unsigned Reg = *Super; + MCRegister Reg = *Super; if (!MRI->reg_empty(Reg)) LICalc->extendToUses(LR, Reg); } @@ -371,7 +371,7 @@ static void createSegmentsForValues(LiveRange &LR, void LiveIntervals::extendSegmentsToUses(LiveRange &Segments, ShrinkToUsesWorkList &WorkList, - unsigned Reg, LaneBitmask LaneMask) { + Register Reg, LaneBitmask LaneMask) { // Keep track of the PHIs that are in use. SmallPtrSet UsedPHIs; // Blocks that have already been added to WorkList as live-out. @@ -470,7 +470,7 @@ bool LiveIntervals::shrinkToUses(LiveInterval *li, ShrinkToUsesWorkList WorkList; // Visit all instructions reading li->reg(). - unsigned Reg = li->reg(); + Register Reg = li->reg(); for (MachineInstr &UseMI : MRI->reg_instructions(Reg)) { if (UseMI.isDebugValue() || !UseMI.readsVirtualRegister(Reg)) continue; @@ -523,7 +523,7 @@ bool LiveIntervals::computeDeadValues(LiveInterval &LI, // Is the register live before? Otherwise we may have to add a read-undef // flag for subregister defs. - unsigned VReg = LI.reg(); + Register VReg = LI.reg(); if (MRI->shouldTrackSubRegLiveness(VReg)) { if ((I == LI.begin() || std::prev(I)->end < Def) && !VNI->isPHIDef()) { MachineInstr *MI = getInstructionFromIndex(Def); @@ -557,7 +557,7 @@ bool LiveIntervals::computeDeadValues(LiveInterval &LI, return MayHaveSplitComponents; } -void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg) { +void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, Register Reg) { LLVM_DEBUG(dbgs() << "Shrink: " << SR << '\n'); assert(Register::isVirtualRegister(Reg) && "Can only shrink virtual registers"); @@ -706,7 +706,7 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) { LiveRange::const_iterator>, 4> SRs; for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { - unsigned Reg = Register::index2VirtReg(i); + Register Reg = Register::index2VirtReg(i); if (MRI->reg_nodbg_empty(Reg)) continue; const LiveInterval &LI = getInterval(Reg); @@ -881,8 +881,8 @@ float LiveIntervals::getSpillWeight(bool isDef, bool isUse, } LiveRange::Segment -LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr &startInst) { - LiveInterval& Interval = createEmptyInterval(reg); +LiveIntervals::addSegmentToEndOfBlock(Register Reg, MachineInstr &startInst) { + LiveInterval &Interval = createEmptyInterval(Reg); VNInfo *VN = Interval.getNextValue( SlotIndex(getInstructionIndex(startInst).getRegSlot()), getVNInfoAllocator()); @@ -1049,7 +1049,7 @@ class LiveIntervals::HMEditor { private: /// Update a single live range, assuming an instruction has been moved from /// OldIdx to NewIdx. - void updateRange(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) { + void updateRange(LiveRange &LR, Register Reg, LaneBitmask LaneMask) { if (!Updated.insert(&LR).second) return; LLVM_DEBUG({ @@ -1246,7 +1246,7 @@ class LiveIntervals::HMEditor { /// Update LR to reflect an instruction has been moved upwards from OldIdx /// to NewIdx (NewIdx < OldIdx). - void handleMoveUp(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) { + void handleMoveUp(LiveRange &LR, Register Reg, LaneBitmask LaneMask) { LiveRange::iterator E = LR.end(); // Segment going into OldIdx. LiveRange::iterator OldIdxIn = LR.find(OldIdx.getBaseIndex()); @@ -1428,7 +1428,7 @@ class LiveIntervals::HMEditor { } // Return the last use of reg between NewIdx and OldIdx. - SlotIndex findLastUseBefore(SlotIndex Before, unsigned Reg, + SlotIndex findLastUseBefore(SlotIndex Before, Register Reg, LaneBitmask LaneMask) { if (Register::isVirtualRegister(Reg)) { SlotIndex LastUse = Before; @@ -1541,17 +1541,17 @@ void LiveIntervals::handleMoveIntoNewBundle(MachineInstr &BundleStart, void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin, const MachineBasicBlock::iterator End, - const SlotIndex endIdx, - LiveRange &LR, const unsigned Reg, + const SlotIndex EndIdx, LiveRange &LR, + const Register Reg, LaneBitmask LaneMask) { - LiveInterval::iterator LII = LR.find(endIdx); + LiveInterval::iterator LII = LR.find(EndIdx); SlotIndex lastUseIdx; if (LII == LR.begin()) { // This happens when the function is called for a subregister that only // occurs _after_ the range that is to be repaired. return; } - if (LII != LR.end() && LII->start < endIdx) + if (LII != LR.end() && LII->start < EndIdx) lastUseIdx = LII->end; else --LII; @@ -1645,11 +1645,11 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB, while (End != MBB->end() && !Indexes->hasIndex(*End)) ++End; - SlotIndex endIdx; + SlotIndex EndIdx; if (End == MBB->end()) - endIdx = getMBBEndIdx(MBB).getPrevSlot(); + EndIdx = getMBBEndIdx(MBB).getPrevSlot(); else - endIdx = getInstructionIndex(*End); + EndIdx = getInstructionIndex(*End); Indexes->repairIndexesInRange(MBB, Begin, End); @@ -1678,9 +1678,9 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB, continue; for (LiveInterval::SubRange &S : LI.subranges()) - repairOldRegInRange(Begin, End, endIdx, S, Reg, S.LaneMask); + repairOldRegInRange(Begin, End, EndIdx, S, Reg, S.LaneMask); - repairOldRegInRange(Begin, End, endIdx, LI, Reg); + repairOldRegInRange(Begin, End, EndIdx, LI, Reg); } } @@ -1717,7 +1717,7 @@ void LiveIntervals::splitSeparateComponents(LiveInterval &LI, if (NumComp <= 1) return; LLVM_DEBUG(dbgs() << " Split " << NumComp << " components: " << LI << '\n'); - unsigned Reg = LI.reg(); + Register Reg = LI.reg(); const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); for (unsigned I = 1; I < NumComp; ++I) { Register NewVReg = MRI->createVirtualRegister(RegClass); diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp index 4fba8f38425500..6490a797fd60b7 100644 --- a/llvm/lib/CodeGen/LiveVariables.cpp +++ b/llvm/lib/CodeGen/LiveVariables.cpp @@ -82,11 +82,10 @@ LLVM_DUMP_METHOD void LiveVariables::VarInfo::dump() const { #endif /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg. -LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { - assert(Register::isVirtualRegister(RegIdx) && - "getVarInfo: not a virtual register!"); - VirtRegInfo.grow(RegIdx); - return VirtRegInfo[RegIdx]; +LiveVariables::VarInfo &LiveVariables::getVarInfo(Register Reg) { + assert(Reg.isVirtual() && "getVarInfo: not a virtual register!"); + VirtRegInfo.grow(Reg); + return VirtRegInfo[Reg]; } void LiveVariables::MarkVirtRegAliveInBlock( @@ -127,13 +126,13 @@ void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo, } } -void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, +void LiveVariables::HandleVirtRegUse(Register Reg, MachineBasicBlock *MBB, MachineInstr &MI) { - assert(MRI->getVRegDef(reg) && "Register use before def!"); + assert(MRI->getVRegDef(Reg) && "Register use before def!"); unsigned BBNum = MBB->getNumber(); - VarInfo& VRInfo = getVarInfo(reg); + VarInfo &VRInfo = getVarInfo(Reg); // Check to see if this basic block is already a kill block. if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) { @@ -164,7 +163,8 @@ void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, // where there is a use in a PHI node that's a predecessor to the defining // block. We don't want to mark all predecessors as having the value "alive" // in this case. - if (MBB == MRI->getVRegDef(reg)->getParent()) return; + if (MBB == MRI->getVRegDef(Reg)->getParent()) + return; // Add a new kill entry for this basic block. If this virtual register is // already marked as alive in this basic block, that means it is alive in at @@ -175,10 +175,10 @@ void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, // Update all dominating blocks to mark them as "known live". for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), E = MBB->pred_end(); PI != E; ++PI) - MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI); + MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(Reg)->getParent(), *PI); } -void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr &MI) { +void LiveVariables::HandleVirtRegDef(Register Reg, MachineInstr &MI) { VarInfo &VRInfo = getVarInfo(Reg); if (VRInfo.AliveBlocks.empty()) @@ -188,8 +188,9 @@ void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr &MI) { /// FindLastPartialDef - Return the last partial def of the specified register. /// Also returns the sub-registers that're defined by the instruction. -MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, - SmallSet &PartDefRegs) { +MachineInstr * +LiveVariables::FindLastPartialDef(Register Reg, + SmallSet &PartDefRegs) { unsigned LastDefReg = 0; unsigned LastDefDist = 0; MachineInstr *LastDef = nullptr; @@ -227,7 +228,7 @@ MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add /// implicit defs to a machine instruction if there was an earlier def of its /// super-register. -void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) { +void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) { MachineInstr *LastDef = PhysRegDef[Reg]; // If there was a previous use or a "full" def all is well. if (!LastDef && !PhysRegUse[Reg]) { @@ -277,7 +278,7 @@ void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) { /// FindLastRefOrPartRef - Return the last reference or partial reference of /// the specified register. -MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) { +MachineInstr *LiveVariables::FindLastRefOrPartRef(Register Reg) { MachineInstr *LastDef = PhysRegDef[Reg]; MachineInstr *LastUse = PhysRegUse[Reg]; if (!LastDef && !LastUse) @@ -307,7 +308,7 @@ MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) { return LastRefOrPartRef; } -bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) { +bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) { MachineInstr *LastDef = PhysRegDef[Reg]; MachineInstr *LastUse = PhysRegUse[Reg]; if (!LastDef && !LastUse) @@ -439,7 +440,7 @@ void LiveVariables::HandleRegMask(const MachineOperand &MO) { } } -void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI, +void LiveVariables::HandlePhysRegDef(Register Reg, MachineInstr *MI, SmallVectorImpl &Defs) { // What parts of the register are previously defined? SmallSet Live; @@ -485,7 +486,7 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI, void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI, SmallVectorImpl &Defs) { while (!Defs.empty()) { - unsigned Reg = Defs.back(); + Register Reg = Defs.back(); Defs.pop_back(); for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); SubRegs.isValid(); ++SubRegs) { @@ -652,7 +653,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { // Convert and transfer the dead / killed information we have gathered into // VirtRegInfo onto MI's. for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) { - const unsigned Reg = Register::index2VirtReg(i); + const Register Reg = Register::index2VirtReg(i); for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j) if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg)) VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI); @@ -677,7 +678,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { /// replaceKillInstruction - Update register kill info by replacing a kill /// instruction with a new one. -void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr &OldMI, +void LiveVariables::replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI) { VarInfo &VI = getVarInfo(Reg); std::replace(VI.Kills.begin(), VI.Kills.end(), &OldMI, &NewMI); @@ -717,8 +718,7 @@ void LiveVariables::analyzePHINodes(const MachineFunction& Fn) { } bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB, - unsigned Reg, - MachineRegisterInfo &MRI) { + Register Reg, MachineRegisterInfo &MRI) { unsigned Num = MBB.getNumber(); // Reg is live-through. @@ -734,7 +734,7 @@ bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB, return findKill(&MBB); } -bool LiveVariables::isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) { +bool LiveVariables::isLiveOut(Register Reg, const MachineBasicBlock &MBB) { LiveVariables::VarInfo &VI = getVarInfo(Reg); SmallPtrSet Kills; @@ -792,7 +792,7 @@ void LiveVariables::addNewBlock(MachineBasicBlock *BB, // Update info for all live variables for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { - unsigned Reg = Register::index2VirtReg(i); + Register Reg = Register::index2VirtReg(i); // If the Defs is defined in the successor it can't be live in BB. if (Defs.count(Reg)) @@ -818,7 +818,7 @@ void LiveVariables::addNewBlock(MachineBasicBlock *BB, SparseBitVector<> &BV = LiveInSets[SuccBB->getNumber()]; for (auto R = BV.begin(), E = BV.end(); R != E; R++) { - unsigned VirtReg = Register::index2VirtReg(*R); + Register VirtReg = Register::index2VirtReg(*R); LiveVariables::VarInfo &VI = getVarInfo(VirtReg); VI.AliveBlocks.set(NumNew); } diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp index 521ae367cde337..3b0a55c04e8922 100644 --- a/llvm/lib/CodeGen/PHIElimination.cpp +++ b/llvm/lib/CodeGen/PHIElimination.cpp @@ -101,10 +101,10 @@ namespace { // These functions are temporary abstractions around LiveVariables and // LiveIntervals, so they can go away when LiveVariables does. - bool isLiveIn(unsigned Reg, const MachineBasicBlock *MBB); - bool isLiveOutPastPHIs(unsigned Reg, const MachineBasicBlock *MBB); + bool isLiveIn(Register Reg, const MachineBasicBlock *MBB); + bool isLiveOutPastPHIs(Register Reg, const MachineBasicBlock *MBB); - using BBVRegPair = std::pair; + using BBVRegPair = std::pair; using VRegPHIUse = DenseMap; VRegPHIUse VRegPHIUseCount; @@ -692,7 +692,7 @@ bool PHIElimination::SplitPHIEdges(MachineFunction &MF, return Changed; } -bool PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock *MBB) { +bool PHIElimination::isLiveIn(Register Reg, const MachineBasicBlock *MBB) { assert((LV || LIS) && "isLiveIn() requires either LiveVariables or LiveIntervals"); if (LIS) @@ -701,7 +701,7 @@ bool PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock *MBB) { return LV->isLiveIn(Reg, *MBB); } -bool PHIElimination::isLiveOutPastPHIs(unsigned Reg, +bool PHIElimination::isLiveOutPastPHIs(Register Reg, const MachineBasicBlock *MBB) { assert((LV || LIS) && "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");