diff --git a/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn b/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
index aecb65ab6c728..a71dfa518b1df 100644
--- a/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
@@ -1,5 +1,19 @@
 import("//llvm/utils/TableGen/tablegen.gni")
 
+tablegen("ARMTargetParserDef") {
+  visibility = [ ":gen" ]
+  args = [ "-gen-arm-target-def" ]
+  td_file = "//llvm/lib/Target/ARM/ARM.td"
+  tblgen_target = "//llvm/utils/TableGen:llvm-min-tblgen"
+}
+
+tablegen("AArch64TargetParserDef") {
+  visibility = [ ":gen" ]
+  args = [ "-gen-arm-target-def" ]
+  td_file = "//llvm/lib/Target/AArch64/AArch64.td"
+  tblgen_target = "//llvm/utils/TableGen:llvm-min-tblgen"
+}
+
 tablegen("RISCVTargetParserDef") {
   visibility = [ ":gen" ]
   args = [ "-gen-riscv-target-def" ]
@@ -8,5 +22,9 @@ tablegen("RISCVTargetParserDef") {
 }
 
 group("gen") {
-  deps = [ ":RISCVTargetParserDef" ]
+  deps = [
+    ":ARMTargetParserDef",
+    ":AArch64TargetParserDef",
+    ":RISCVTargetParserDef",
+  ]
 }
diff --git a/llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn b/llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
index 6a95699a0a814..f3ae5b5899ac6 100644
--- a/llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
@@ -1,5 +1,6 @@
 source_set("llvm-min-tblgen-sources") {
   sources = [
+    "ARMTargetDefEmitter.cpp",
     "Attributes.cpp",
     "DirectiveEmitter.cpp",
     "IntrinsicEmitter.cpp",
@@ -32,7 +33,6 @@ executable("llvm-tblgen") {
   ]
   include_dirs = [ "." ]
   sources = [
-    "ARMTargetDefEmitter.cpp",
     "AsmMatcherEmitter.cpp",
     "AsmWriterEmitter.cpp",
     "CTagsEmitter.cpp",