diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX11.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX11.rst new file mode 100644 index 0000000000000..c3eb05bdbd291 --- /dev/null +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX11.rst @@ -0,0 +1,3313 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +==================================================================================== +Syntax of GFX11 Instructions +==================================================================================== + +.. contents:: + :local: + +Introduction +============ + +This document describes the syntax of GFX11 instructions. + +GFX11 family includes gfx1100, gfx1101, gfx1102 and gfx1103 GPUs. + +Notation +======== + +Notation used in this document is explained :ref:`here`. + +Overview +======== + +An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document`. + +Instructions +============ + + +DS +-- + +.. parsed-literal:: + + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + ds_add_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_gs_reg_rtn :ref:`vdst`::ref:`b64`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_append :ref:`vdst` :ref:`offset` :ref:`gds` + ds_bpermute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` + ds_bvh_stack_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1`::ref:`b128` :ref:`offset` + ds_cmpstore_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpstore_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpstore_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpstore_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpstore_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpstore_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpstore_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpstore_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_consume :ref:`vdst` :ref:`offset` :ref:`gds` + ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_barrier :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_init :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_sema_br :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_sema_p :ref:`offset` :ref:`gds` + ds_gws_sema_release_all :ref:`offset` :ref:`gds` + ds_gws_sema_v :ref:`offset` :ref:`gds` + ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_load_2addr_b32 :ref:`vdst`::ref:`b64`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_load_2addr_b64 :ref:`vdst`::ref:`b128`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_load_2addr_stride64_b32 :ref:`vdst`::ref:`b64`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_load_2addr_stride64_b64 :ref:`vdst`::ref:`b128`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_load_addtid_b32 :ref:`vdst` :ref:`offset` + ds_load_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_load_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_load_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_load_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_load_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_load_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_load_i8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_load_i8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_load_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_load_u16_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_load_u16_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_load_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_load_u8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_load_u8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_nop + ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_ordered_count :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_permute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` + ds_read2_b32 :ref:`vdst`::ref:`b64`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2_b64 :ref:`vdst`::ref:`b128`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b32 :ref:`vdst`::ref:`b64`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b64 :ref:`vdst`::ref:`b128`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read_addtid_b32 :ref:`vdst` :ref:`offset` + ds_read_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_store_2addr_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_store_2addr_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_store_2addr_stride64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_store_2addr_stride64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_store_addtid_b32 :ref:`vdata` :ref:`offset` + ds_store_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_store_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_store_b16_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_store_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_store_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_store_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_store_b8_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_store_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_storexchg_2addr_rtn_b32 :ref:`vdst`::ref:`b64`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_storexchg_2addr_rtn_b64 :ref:`vdst`::ref:`b128`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_storexchg_2addr_stride64_rtn_b32 :ref:`vdst`::ref:`b64`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_storexchg_2addr_stride64_rtn_b64 :ref:`vdst`::ref:`b128`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_storexchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_storexchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_gs_reg_rtn :ref:`vdst`::ref:`b64`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_swizzle_b32 :ref:`vdst`, :ref:`vaddr` :ref:`pattern` + ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write_addtid_b32 :ref:`vdata` :ref:`offset` + ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b16_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b8_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b64`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b128`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b64`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b128`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + +EXP +--- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + exp :ref:`tgt`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vsrc2`, :ref:`vsrc3` :ref:`done` :ref:`row_en` + +FLAT +---- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + flat_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_add_f32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_add_u32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_add_u64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_and_b32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_and_b64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_cmpswap_b32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_cmpswap_b64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_cmpswap_f32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`f32x2` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_dec :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_dec_u32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_dec_u64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_dec_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_inc :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_inc_u32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_inc_u64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_inc_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_max_f32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_max_i32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_max_i64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_max_u32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_max_u64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_min_f32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_min_i32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_min_i64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_min_u32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_min_u64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_or_b32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_or_b64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_smax :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_smax_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_smin :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_smin_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_sub_u32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_sub_u64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_swap_b32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_swap_b64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_umax :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_umax_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_umin :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_umin_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_xor_b32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_xor_b64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_d16_b16 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_d16_hi_b16 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_d16_hi_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_d16_hi_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_d16_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_d16_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_dword :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_dwordx2 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_dwordx3 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_dwordx4 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_sbyte :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_sshort :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_ubyte :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_ushort :ref:`vdst`, :ref:`vaddr` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_byte :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_d16_hi_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_d16_hi_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_dword :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_dwordx2 :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_dwordx3 :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_dwordx4 :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_short :ref:`vaddr`, :ref:`vdata` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + +FLAT GLOBAL +----------- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + global_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_add_f32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_add_u32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_add_u64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_and_b32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_and_b64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_cmpswap_b32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_cmpswap_b64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_cmpswap_f32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`f32x2`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_csub_u32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_dec :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_dec_u32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_dec_u64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_dec_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_inc :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_inc_u32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_inc_u64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_inc_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_max_f32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_max_i32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_max_i64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_max_u32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_max_u64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_min_f32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_min_i32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_min_i64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_min_u32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_min_u64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_or_b32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_or_b64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_smax :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_smax_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_smin :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_smin_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_sub_u32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_sub_u64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_swap_b32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_swap_b64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_umax :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_umax_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_umin :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_umin_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_xor_b32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_xor_b64 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_addtid_b32 :ref:`vdst`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_b128 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_b96 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_d16_b16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_d16_hi_b16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_d16_hi_i8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_d16_hi_u8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_d16_i8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_d16_u8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_i16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_i8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_u16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_u8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_addtid_b32 :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_b128 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_b16 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_b32 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_b64 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_b8 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_b96 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_byte :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_d16_hi_b16 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_d16_hi_b8 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_dword :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_dwordx2 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_dwordx3 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_dwordx4 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_short :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + +FLAT SCRATCH +------------ + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + scratch_load_b128 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_b96 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_d16_b16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_d16_hi_b16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_d16_hi_i8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_d16_hi_u8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_d16_i8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_d16_u8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_i16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_i8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_u16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_u8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_b128 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_b16 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_b32 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_b64 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_b8 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_b96 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_byte :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_d16_hi_b16 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_d16_hi_b8 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_dword :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_dwordx2 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_dwordx3 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_dwordx4 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_short :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`glc` :ref:`slc` :ref:`dlc` + +LDSDIR +------ + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + lds_direct_load :ref:`vdst` :ref:`wait_vdst` + lds_param_load :ref:`vdst`, :ref:`attr` :ref:`wait_vdst` + +MIMG +---- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + image_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_cmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_dec :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_inc :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_smax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_smin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_umax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_umin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_bvh64_intersect_ray :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`a16` + image_bvh_intersect_ray :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`a16` + image_gather4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lwe` :ref:`d16` + image_gather4_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lwe` :ref:`d16` + image_gather4_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4h :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_get_lod :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_get_resinfo :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_load :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_load_mip :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_load_mip_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_load_mip_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_load_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_load_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_msaa_load :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_store :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_store_mip :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_store_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_store_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + +MTBUF +----- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + tbuffer_load_d16_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_d16_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_d16_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_d16_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_store_d16_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_store_d16_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_store_d16_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_store_d16_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + +MUBUF +----- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + buffer_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_add_f32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_add_u32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_add_u64 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_add_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_and_b32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_and_b64 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_and_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_cmpswap :ref:`vdata`::ref:`dst`::ref:`b32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_cmpswap_b32 :ref:`vdata`::ref:`dst`::ref:`b32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_cmpswap_b64 :ref:`vdata`::ref:`dst`::ref:`b64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_cmpswap_f32 :ref:`vdata`::ref:`dst`::ref:`f32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_cmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`b64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_csub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_csub_u32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_dec :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_dec_u32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_dec_u64 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_dec_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_fcmpswap :ref:`vdata`::ref:`dst`::ref:`f32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_fmax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_fmin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_inc :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_inc_u32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_inc_u64 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_inc_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_max_f32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_max_i32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_max_i64 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_max_u32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_max_u64 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_min_f32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_min_i32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_min_i64 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_min_u32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_min_u64 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_or_b32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_or_b64 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_or_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_smax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_smax_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_smin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_smin_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_sub_u32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_sub_u64 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_sub_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_swap_b32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_swap_b64 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_swap_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_umax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_umax_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_umin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_umin_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_xor_b32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_xor_b64 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_atomic_xor_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_gl0_inv + buffer_gl1_inv + buffer_load_b128 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_b96 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_d16_b16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_d16_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_d16_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_d16_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_d16_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_d16_hi_b16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_d16_hi_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_d16_hi_i8 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_d16_hi_u8 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_d16_i8 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_d16_u8 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_format_d16_hi_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_i16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_i8 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_lds_b32 :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_lds_format_x :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_lds_i16 :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_lds_i8 :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_lds_u16 :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_lds_u8 :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_short_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_short_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_u16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_u8 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` + buffer_store_b128 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_b16 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_b32 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_b64 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_b8 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_b96 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_byte :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_byte_d16_hi :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_d16_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_d16_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_d16_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_d16_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_d16_hi_b16 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_d16_hi_b8 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_d16_hi_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_dword :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_dwordx2 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_dwordx3 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_dwordx4 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_format_d16_hi_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_short :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_store_short_d16_hi :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + +SMEM +---- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_buffer_load_b128 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset20u` :ref:`glc` :ref:`dlc` + s_buffer_load_b256 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset20u` :ref:`glc` :ref:`dlc` + s_buffer_load_b32 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset20u` :ref:`glc` :ref:`dlc` + s_buffer_load_b512 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset20u` :ref:`glc` :ref:`dlc` + s_buffer_load_b64 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset20u` :ref:`glc` :ref:`dlc` + s_buffer_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset20u` :ref:`glc` :ref:`dlc` + s_buffer_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset20u` :ref:`glc` :ref:`dlc` + s_buffer_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset20u` :ref:`glc` :ref:`dlc` + s_buffer_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset20u` :ref:`glc` :ref:`dlc` + s_buffer_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset20u` :ref:`glc` :ref:`dlc` + s_dcache_inv + s_gl1_inv + s_load_b128 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset21s` :ref:`glc` :ref:`dlc` + s_load_b256 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset21s` :ref:`glc` :ref:`dlc` + s_load_b32 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset21s` :ref:`glc` :ref:`dlc` + s_load_b512 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset21s` :ref:`glc` :ref:`dlc` + s_load_b64 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset21s` :ref:`glc` :ref:`dlc` + s_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset21s` :ref:`glc` :ref:`dlc` + s_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset21s` :ref:`glc` :ref:`dlc` + s_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset21s` :ref:`glc` :ref:`dlc` + s_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset21s` :ref:`glc` :ref:`dlc` + s_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`offset21s` :ref:`glc` :ref:`dlc` + +SOP1 +---- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_abs_i32 :ref:`sdst`, :ref:`ssrc` + s_and_not0_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_and_not0_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_and_not0_wrexec_b32 :ref:`sdst`, :ref:`ssrc` + s_and_not0_wrexec_b64 :ref:`sdst`, :ref:`ssrc` + s_and_not1_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_and_not1_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_and_not1_wrexec_b32 :ref:`sdst`, :ref:`ssrc` + s_and_not1_wrexec_b64 :ref:`sdst`, :ref:`ssrc` + s_and_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_and_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_andn1_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_andn1_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_andn1_wrexec_b32 :ref:`sdst`, :ref:`ssrc` + s_andn1_wrexec_b64 :ref:`sdst`, :ref:`ssrc` + s_andn2_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_andn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_andn2_wrexec_b32 :ref:`sdst`, :ref:`ssrc` + s_andn2_wrexec_b64 :ref:`sdst`, :ref:`ssrc` + s_bcnt0_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_bcnt0_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_bcnt1_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_bcnt1_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_bitreplicate_b64_b32 :ref:`sdst`, :ref:`ssrc` + s_bitset0_b32 :ref:`sdst`, :ref:`ssrc`::ref:`u32` + s_bitset0_b64 :ref:`sdst`, :ref:`ssrc`::ref:`u32` + s_bitset1_b32 :ref:`sdst`, :ref:`ssrc`::ref:`u32` + s_bitset1_b64 :ref:`sdst`, :ref:`ssrc`::ref:`u32` + s_brev_b32 :ref:`sdst`, :ref:`ssrc` + s_brev_b64 :ref:`sdst`, :ref:`ssrc` + s_cls_i32 :ref:`sdst`, :ref:`ssrc` + s_cls_i32_i64 :ref:`sdst`, :ref:`ssrc` + s_clz_i32_u32 :ref:`sdst`, :ref:`ssrc` + s_clz_i32_u64 :ref:`sdst`, :ref:`ssrc` + s_cmov_b32 :ref:`sdst`, :ref:`ssrc` + s_cmov_b64 :ref:`sdst`, :ref:`ssrc` + s_ctz_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_ctz_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_ff1_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_ff1_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_i64 :ref:`sdst`, :ref:`ssrc` + s_getpc_b64 :ref:`sdst` + s_mov_b32 :ref:`sdst`, :ref:`ssrc` + s_mov_b64 :ref:`sdst`, :ref:`ssrc` + s_movreld_b32 :ref:`sdst`, :ref:`ssrc` + s_movreld_b64 :ref:`sdst`, :ref:`ssrc` + s_movrels_b32 :ref:`sdst`, :ref:`ssrc` + s_movrels_b64 :ref:`sdst`, :ref:`ssrc` + s_movrelsd_2_b32 :ref:`sdst`, :ref:`ssrc` + s_nand_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_nand_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_nor_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_nor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_not_b32 :ref:`sdst`, :ref:`ssrc` + s_not_b64 :ref:`sdst`, :ref:`ssrc` + s_or_not0_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_or_not0_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_or_not1_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_or_not1_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_or_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_or_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_orn1_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_orn1_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_orn2_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_orn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_quadmask_b32 :ref:`sdst`, :ref:`ssrc` + s_quadmask_b64 :ref:`sdst`, :ref:`ssrc` + s_rfe_b64 :ref:`ssrc` + s_sendmsg_rtn_b32 :ref:`sdst`, :ref:`msg` + s_sendmsg_rtn_b64 :ref:`sdst`, :ref:`msg` + s_setpc_b64 :ref:`ssrc` + s_sext_i32_i16 :ref:`sdst`, :ref:`ssrc` + s_sext_i32_i8 :ref:`sdst`, :ref:`ssrc` + s_swappc_b64 :ref:`sdst`, :ref:`ssrc` + s_wqm_b32 :ref:`sdst`, :ref:`ssrc` + s_wqm_b64 :ref:`sdst`, :ref:`ssrc` + s_xnor_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_xnor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_xor_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_xor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + +SOP2 +---- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_absdiff_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_add_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_addc_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_and_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_and_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_and_not1_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_and_not1_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_andn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_andn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_ashr_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_ashr_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_bfe_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfm_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_bfm_b64 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32` + s_cselect_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_cselect_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl1_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl2_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl3_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl4_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshl_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshr_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshr_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_max_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_max_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_min_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_min_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_mul_hi_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_mul_hi_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_mul_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nand_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nand_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_or_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_or_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_or_not1_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_or_not1_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_orn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_orn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_pack_hh_b32_b16 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32` + s_pack_hl_b32_b16 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1` + s_pack_lh_b32_b16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`b32` + s_pack_ll_b32_b16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_sub_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_sub_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_subb_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xnor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xnor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + +SOPC +---- + +.. parsed-literal:: + + **INSTRUCTION** **SRC0** **SRC1** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_bitcmp0_b32 :ref:`ssrc0`, :ref:`ssrc1` + s_bitcmp0_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bitcmp1_b32 :ref:`ssrc0`, :ref:`ssrc1` + s_bitcmp1_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_cmp_eq_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_eq_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_eq_u64 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_ge_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_ge_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_gt_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_gt_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_le_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_le_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_u64 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lt_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lt_u32 :ref:`ssrc0`, :ref:`ssrc1` + +SOPK +---- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_addk_i32 :ref:`sdst`, :ref:`imm16` + s_call_b64 :ref:`sdst`, :ref:`label` + s_cmovk_i32 :ref:`sdst`, :ref:`imm16` + s_cmpk_eq_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_eq_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_ge_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_ge_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_gt_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_gt_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_le_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_le_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lg_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lg_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lt_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lt_u32 :ref:`ssrc`, :ref:`imm16` + s_getreg_b32 :ref:`sdst`, :ref:`hwreg` + s_movk_i32 :ref:`sdst`, :ref:`imm16` + s_mulk_i32 :ref:`sdst`, :ref:`imm16` + s_setreg_b32 :ref:`hwreg`, :ref:`ssrc` + s_setreg_imm32_b32 :ref:`hwreg`, :ref:`simm32` + s_subvector_loop_begin :ref:`sdst`, :ref:`label` + s_subvector_loop_end :ref:`sdst`, :ref:`label` + s_version :ref:`imm16` + s_waitcnt_expcnt :ref:`ssrc`, :ref:`imm16` + s_waitcnt_lgkmcnt :ref:`ssrc`, :ref:`imm16` + s_waitcnt_vmcnt :ref:`ssrc`, :ref:`imm16` + s_waitcnt_vscnt :ref:`ssrc`, :ref:`imm16` + +SOPP +---- + +.. parsed-literal:: + + **INSTRUCTION** **SRC** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_barrier + s_branch :ref:`label` + s_cbranch_cdbgsys :ref:`label` + s_cbranch_cdbgsys_and_user :ref:`label` + s_cbranch_cdbgsys_or_user :ref:`label` + s_cbranch_cdbguser :ref:`label` + s_cbranch_execnz :ref:`label` + s_cbranch_execz :ref:`label` + s_cbranch_scc0 :ref:`label` + s_cbranch_scc1 :ref:`label` + s_cbranch_vccnz :ref:`label` + s_cbranch_vccz :ref:`label` + s_clause :ref:`imm16` + s_code_end + s_decperflevel :ref:`imm16` + s_delay_alu :ref:`delay` + s_denorm_mode :ref:`imm16` + s_endpgm + s_endpgm_saved + s_icache_inv + s_incperflevel :ref:`imm16` + s_inst_prefetch :ref:`imm16` + s_nop :ref:`imm16` + s_round_mode :ref:`imm16` + s_sendmsg :ref:`msg` + s_sendmsghalt :ref:`msg` + s_set_inst_prefetch_distance :ref:`imm16` + s_sethalt :ref:`imm16` + s_setkill :ref:`imm16` + s_setprio :ref:`imm16` + s_sleep :ref:`imm16` + s_trap :ref:`imm16` + s_ttracedata + s_ttracedata_imm :ref:`imm16` + s_wait_event :ref:`imm16` + s_wait_idle + s_waitcnt :ref:`waitcnt` + s_waitcnt_depctr :ref:`waitcnt_depctr` + s_wakeup + +VINTERP +------- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_interp_p10_f16_f32 :ref:`vdst`::ref:`f32`, :ref:`vparam`::ref:`m`::ref:`f16`, :ref:`vij`::ref:`m`, :ref:`vparam0`::ref:`m`::ref:`f16` :ref:`op_sel` :ref:`clamp` :ref:`wait_exp` + v_interp_p10_f32 :ref:`vdst`, :ref:`vparam`::ref:`m`, :ref:`vij`::ref:`m`, :ref:`vparam0`::ref:`m` :ref:`clamp` :ref:`wait_exp` + v_interp_p10_rtz_f16_f32 :ref:`vdst`::ref:`f32`, :ref:`vparam`::ref:`m`::ref:`f16`, :ref:`vij`::ref:`m`, :ref:`vparam0`::ref:`m`::ref:`f16` :ref:`op_sel` :ref:`clamp` :ref:`wait_exp` + v_interp_p2_f16_f32 :ref:`vdst`, :ref:`vparam`::ref:`m`::ref:`f16`, :ref:`vij`::ref:`m`, :ref:`vparam0`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`wait_exp` + v_interp_p2_f32 :ref:`vdst`, :ref:`vparam`::ref:`m`, :ref:`vij`::ref:`m`, :ref:`vparam0`::ref:`m` :ref:`clamp` :ref:`wait_exp` + v_interp_p2_rtz_f16_f32 :ref:`vdst`, :ref:`vparam`::ref:`m`::ref:`f16`, :ref:`vij`::ref:`m`, :ref:`vparam0`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`wait_exp` + +VOP1 +---- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_bfrev_b32 :ref:`vdst`, :ref:`src` + v_ceil_f16 :ref:`vdst`, :ref:`src` + v_ceil_f32 :ref:`vdst`, :ref:`src` + v_ceil_f64 :ref:`vdst`, :ref:`src` + v_cls_i32 :ref:`vdst`, :ref:`src` + v_clz_i32_u32 :ref:`vdst`, :ref:`src` + v_cos_f16 :ref:`vdst`, :ref:`src` + v_cos_f32 :ref:`vdst`, :ref:`src` + v_ctz_i32_b32 :ref:`vdst`, :ref:`src` + v_cvt_f16_f32 :ref:`vdst`, :ref:`src` + v_cvt_f16_i16 :ref:`vdst`, :ref:`src` + v_cvt_f16_u16 :ref:`vdst`, :ref:`src` + v_cvt_f32_f16 :ref:`vdst`, :ref:`src` + v_cvt_f32_f64 :ref:`vdst`, :ref:`src` + v_cvt_f32_i32 :ref:`vdst`, :ref:`src` + v_cvt_f32_u32 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src` + v_cvt_f64_f32 :ref:`vdst`, :ref:`src` + v_cvt_f64_i32 :ref:`vdst`, :ref:`src` + v_cvt_f64_u32 :ref:`vdst`, :ref:`src` + v_cvt_floor_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_flr_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_i16_f16 :ref:`vdst`, :ref:`src` + v_cvt_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_i32_f64 :ref:`vdst`, :ref:`src` + v_cvt_i32_i16 :ref:`vdst`, :ref:`src` + v_cvt_nearest_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_norm_i16_f16 :ref:`vdst`, :ref:`src` + v_cvt_norm_u16_f16 :ref:`vdst`, :ref:`src` + v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src` + v_cvt_rpi_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_u16_f16 :ref:`vdst`, :ref:`src` + v_cvt_u32_f32 :ref:`vdst`, :ref:`src` + v_cvt_u32_f64 :ref:`vdst`, :ref:`src` + v_cvt_u32_u16 :ref:`vdst`, :ref:`src` + v_exp_f16 :ref:`vdst`, :ref:`src` + v_exp_f32 :ref:`vdst`, :ref:`src` + v_ffbh_i32 :ref:`vdst`, :ref:`src` + v_ffbh_u32 :ref:`vdst`, :ref:`src` + v_ffbl_b32 :ref:`vdst`, :ref:`src` + v_floor_f16 :ref:`vdst`, :ref:`src` + v_floor_f32 :ref:`vdst`, :ref:`src` + v_floor_f64 :ref:`vdst`, :ref:`src` + v_fract_f16 :ref:`vdst`, :ref:`src` + v_fract_f32 :ref:`vdst`, :ref:`src` + v_fract_f64 :ref:`vdst`, :ref:`src` + v_frexp_exp_i16_f16 :ref:`vdst`, :ref:`src` + v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src` + v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src` + v_frexp_mant_f16 :ref:`vdst`, :ref:`src` + v_frexp_mant_f32 :ref:`vdst`, :ref:`src` + v_frexp_mant_f64 :ref:`vdst`, :ref:`src` + v_log_f16 :ref:`vdst`, :ref:`src` + v_log_f32 :ref:`vdst`, :ref:`src` + v_mov_b32 :ref:`vdst`, :ref:`src` + v_movreld_b32 :ref:`vdst`, :ref:`src` + v_movrels_b32 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_2_b32 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_b32 :ref:`vdst`, :ref:`vsrc` + v_nop + v_not_b16 :ref:`vdst`, :ref:`src` + v_not_b32 :ref:`vdst`, :ref:`src` + v_permlane64_b32 :ref:`vdst`, :ref:`vdata` + v_pipeflush + v_rcp_f16 :ref:`vdst`, :ref:`src` + v_rcp_f32 :ref:`vdst`, :ref:`src` + v_rcp_f64 :ref:`vdst`, :ref:`src` + v_rcp_iflag_f32 :ref:`vdst`, :ref:`src` + v_readfirstlane_b32 :ref:`sdst`, :ref:`vsrc` + v_rndne_f16 :ref:`vdst`, :ref:`src` + v_rndne_f32 :ref:`vdst`, :ref:`src` + v_rndne_f64 :ref:`vdst`, :ref:`src` + v_rsq_f16 :ref:`vdst`, :ref:`src` + v_rsq_f32 :ref:`vdst`, :ref:`src` + v_rsq_f64 :ref:`vdst`, :ref:`src` + v_sat_pk_u8_i16 :ref:`vdst`, :ref:`src` + v_sin_f16 :ref:`vdst`, :ref:`src` + v_sin_f32 :ref:`vdst`, :ref:`src` + v_sqrt_f16 :ref:`vdst`, :ref:`src` + v_sqrt_f32 :ref:`vdst`, :ref:`src` + v_sqrt_f64 :ref:`vdst`, :ref:`src` + v_swap_b32 :ref:`vdst`, :ref:`vsrc` + v_swaprel_b32 :ref:`vdst`, :ref:`vsrc` + v_trunc_f16 :ref:`vdst`, :ref:`src` + v_trunc_f32 :ref:`vdst`, :ref:`src` + v_trunc_f64 :ref:`vdst`, :ref:`src` + +VOP1 DPP16 +---------- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_bfrev_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cls_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_clz_i32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ctz_i32_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte0_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte1_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte2_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte3_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_floor_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_i32_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_nearest_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_norm_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_norm_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_off_f32_i4_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_u32_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ffbh_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ffbh_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ffbl_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_log_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_log_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mov_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movreld_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movrels_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movrelsd_2_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movrelsd_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_not_b16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_not_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sat_pk_u8_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + +VOP1 DPP8 +--------- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_bfrev_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cls_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_clz_i32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ctz_i32_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte0_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte1_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte2_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte3_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_floor_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_i32_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_nearest_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_norm_i16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_norm_u16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_off_f32_i4_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_u32_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ffbh_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ffbh_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ffbl_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_log_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_log_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_mov_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movreld_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movrels_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movrelsd_2_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movrelsd_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_not_b16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_not_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sat_pk_u8_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + +VOP2 +---- + +.. parsed-literal:: + + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_add_co_ci_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_add_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_and_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_ashrrev_i32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_cndmask_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_cvt_pk_rtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` + v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` + v_dot2acc_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` + v_dot2c_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` + v_fmaak_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` + v_fmaak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` + v_fmac_dx9_zero_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_fmac_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_fmac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_fmac_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_fmamk_f16 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` + v_fmamk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` + v_ldexp_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`i16` + v_lshlrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_lshrrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_max_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_dx9_zero_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_hi_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_hi_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_pk_fmac_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_sub_co_ci_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_sub_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_sub_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_subrev_co_ci_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_subrev_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_subrev_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_xnor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_xor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + +VOP2 DPP16 +---------- + +.. parsed-literal:: + + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_add_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_and_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ashrrev_i32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cndmask_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_pk_rtz_f16_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`m`::ref:`f32` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_pkrtz_f16_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`m`::ref:`f32` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_dot2acc_f32_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f16x2`, :ref:`vsrc1`::ref:`m`::ref:`f16x2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_dot2c_f32_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f16x2`, :ref:`vsrc1`::ref:`m`::ref:`f16x2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fmac_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fmac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`i16` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_lshlrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_lshrrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_dx9_zero_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_hi_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_hi_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_or_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_xnor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_xor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + +VOP2 DPP8 +--------- + +.. parsed-literal:: + + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_add_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` + v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_add_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_and_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_ashrrev_i32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cndmask_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_pk_rtz_f16_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` :ref:`dpp8_sel` :ref:`fi` + v_cvt_pkrtz_f16_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` :ref:`dpp8_sel` :ref:`fi` + v_dot2acc_f32_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` :ref:`dpp8_sel` :ref:`fi` + v_dot2c_f32_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` :ref:`dpp8_sel` :ref:`fi` + v_fmac_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_fmac_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`::ref:`i16` :ref:`dpp8_sel` :ref:`fi` + v_lshlrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_lshrrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_max_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_max_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_min_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_min_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_dx9_zero_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_hi_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_hi_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_or_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_sub_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` + v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_sub_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_subrev_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` + v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_subrev_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_xnor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_xor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + +VOP3 +---- + +.. parsed-literal:: + + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_add3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_add_co_ci_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_add_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_add_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_lshl_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_add_nc_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` + v_add_nc_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_add_nc_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` + v_add_nc_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`b16` + v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`b16` + v_and_b16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_and_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_ashrrev_i16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_ashrrev_i64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` + v_ceil_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cls_i32_e64 :ref:`vdst`, :ref:`src` + v_clz_i32_u32_e64 :ref:`vdst`, :ref:`src` + v_cmp_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b16` + v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_t_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_t_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_t_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_class_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b16` + v_cmpx_class_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_class_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_eq_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_eq_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_eq_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_eq_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_eq_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_eq_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_f_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_f_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_f_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_f_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_f_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_f_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_f_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ge_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ge_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ge_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_gt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_gt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_gt_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_le_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_le_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_le_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lg_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lg_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lg_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lt_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lt_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lt_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lt_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lt_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_neq_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_neq_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_neq_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_t_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_t_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_t_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_t_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_t_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_t_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_t_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_tru_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_tru_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_tru_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cndmask_b16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`ssrc2` + v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`ssrc2` + v_cos_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ctz_i32_b32_e64 :ref:`vdst`, :ref:`src` + v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f16_i16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f16_u16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_floor_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_i32_i16_e64 :ref:`vdst`, :ref:`src` + v_cvt_nearest_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_norm_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_norm_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_pk_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`::ref:`i32`, :ref:`src1`::ref:`i32` + v_cvt_pk_norm_i16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` + v_cvt_pk_norm_u16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` + v_cvt_pk_rtz_f16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` :ref:`clamp` + v_cvt_pk_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1`::ref:`u32` + v_cvt_pk_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_cvt_pknorm_i16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` + v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pknorm_u16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` + v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pkrtz_f16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` :ref:`clamp` + v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_u32_u16_e64 :ref:`vdst`, :ref:`src` + v_div_fixup_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`omod` + v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_dot2_bf16_bf16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`bf16x2`, :ref:`src1`::ref:`m`::ref:`bf16x2`, :ref:`src2`::ref:`m` :ref:`op_sel` + v_dot2_f16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16x2`, :ref:`src1`::ref:`m`::ref:`f16x2`, :ref:`src2`::ref:`m` :ref:`op_sel` + v_exp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` + v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` + v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` + v_floor_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_dx9_zero_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`omod` + v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fmac_dx9_zero_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_fmac_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_fmac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_fmac_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_exp_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_mant_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ldexp_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i16` :ref:`clamp` :ref:`omod` + v_ldexp_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` + v_log_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_lshl_add_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_lshl_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2` + v_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshlrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshrrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshrrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` + v_mad_i32_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`op_sel` :ref:`clamp` + v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`clamp` + v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` :ref:`clamp` + v_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` + v_mad_u32_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`op_sel` :ref:`clamp` + v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` :ref:`clamp` + v_max3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`omod` + v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_max3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_maxmin_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_maxmin_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_maxmin_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_maxmin_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_med3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`omod` + v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_med3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_med3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`omod` + v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_min3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_minmax_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_minmax_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_minmax_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_minmax_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_mov_b32_e64 :ref:`vdst`, :ref:`src` + v_movreld_b32_e64 :ref:`vdst`, :ref:`src` + v_movrels_b32_e64 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_2_b32_e64 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_b32_e64 :ref:`vdst`, :ref:`vsrc` + v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` + v_mqsad_u32_u8 :ref:`vdst`::ref:`u32x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`vsrc2`::ref:`u32x4` :ref:`clamp` + v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` :ref:`clamp` + v_mul_dx9_zero_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_lo_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_mullit_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_nop_e64 + v_not_b16_e64 :ref:`vdst`, :ref:`src` + v_not_b32_e64 :ref:`vdst`, :ref:`src` + v_or3_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_or_b16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_pack_b32_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`op_sel` + v_perm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_permlane16_b32 :ref:`vdst`, :ref:`vdata`, :ref:`ssrc1`, :ref:`ssrc2` :ref:`dpp_op_sel` + v_permlanex16_b32 :ref:`vdst`, :ref:`vdata`, :ref:`ssrc1`, :ref:`ssrc2` :ref:`dpp_op_sel` + v_pipeflush_e64 + v_qsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` + v_rcp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_readlane_b32 :ref:`sdst`, :ref:`vsrc0`, :ref:`ssrc1` + v_rndne_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` + v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sat_pk_u8_i16_e64 :ref:`vdst`, :ref:`src` + v_sin_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_co_ci_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_sub_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_sub_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_nc_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` + v_sub_nc_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_sub_nc_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` + v_sub_nc_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_subrev_co_ci_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_subrev_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_subrev_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_nc_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` + v_trunc_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` + v_xad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_xnor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_xor3_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_xor_b16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + +VOP3 DPP16 +---------- + +.. parsed-literal:: + + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_add3_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_co_ci_u32_e64_dpp :ref:`vdst`, :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`ssrc2` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_co_u32_e64_dpp :ref:`vdst`, :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_lshl_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_nc_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`op_sel` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_nc_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_nc_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`op_sel` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_nc_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_alignbit_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2`::ref:`b16` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_alignbyte_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2`::ref:`b16` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_and_b16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_and_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_and_or_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ashrrev_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ashrrev_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_bcnt_u32_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_bfe_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`::ref:`u32`, :ref:`src2`::ref:`u32` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_bfe_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_bfi_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_bfm_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_bfrev_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ceil_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ceil_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cls_i32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_clz_i32_u32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_class_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`b16` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_class_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`b32` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_eq_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_eq_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_eq_i16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_eq_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_eq_u16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_eq_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_f_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_f_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_f_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_f_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ge_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ge_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ge_i16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ge_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ge_u16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ge_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_gt_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_gt_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_gt_i16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_gt_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_gt_u16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_gt_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_le_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_le_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_le_i16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_le_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_le_u16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_le_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lg_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lg_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lt_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lt_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lt_i16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lt_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lt_u16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lt_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ne_i16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ne_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ne_u16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ne_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_neq_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_neq_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nge_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nge_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ngt_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ngt_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nle_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nle_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nlg_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nlg_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nlt_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nlt_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_o_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_o_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_t_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_t_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_t_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_t_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_tru_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_tru_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_u_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_u_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_class_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`b16` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_class_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`b32` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_eq_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_eq_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_eq_i16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_eq_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_eq_u16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_eq_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_f_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_f_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_f_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_f_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ge_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ge_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ge_i16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ge_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ge_u16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ge_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_gt_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_gt_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_gt_i16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_gt_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_gt_u16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_gt_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_le_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_le_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_le_i16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_le_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_le_u16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_le_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lg_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lg_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lt_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lt_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lt_i16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lt_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lt_u16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lt_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ne_i16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ne_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ne_u16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ne_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_neq_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_neq_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nge_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nge_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ngt_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ngt_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nle_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nle_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nlg_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nlg_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nlt_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nlt_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_o_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_o_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_t_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_t_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_t_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_t_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_tru_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_tru_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_u_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_u_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cndmask_b16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`ssrc2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cndmask_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`ssrc2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cos_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cos_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ctz_i32_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cubeid_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cubema_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cubesc_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cubetc_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f16_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f16_i16_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f16_u16_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_i32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_u32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte0_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte1_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte2_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte3_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_floor_i32_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_flr_i32_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_i16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_i32_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_i32_i16_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_nearest_i32_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_norm_i16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_norm_u16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_off_f32_i4_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_pk_i16_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`m`::ref:`f32` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_pk_i16_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`i32`, :ref:`vsrc1`::ref:`i32` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_pk_norm_i16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f16`, :ref:`vsrc1`::ref:`m`::ref:`f16` :ref:`op_sel` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_pk_norm_u16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f16`, :ref:`vsrc1`::ref:`m`::ref:`f16` :ref:`op_sel` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_pk_rtz_f16_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`m`::ref:`f32` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_pk_u16_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`m`::ref:`f32` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_pk_u16_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1`::ref:`u32` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_pk_u8_f32_e64_dpp :ref:`vdst`::ref:`b32`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`u32`, :ref:`src2`::ref:`u32` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_pknorm_i16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f16`, :ref:`vsrc1`::ref:`m`::ref:`f16` :ref:`op_sel` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_pknorm_i16_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`m`::ref:`f32` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_pknorm_u16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f16`, :ref:`vsrc1`::ref:`m`::ref:`f16` :ref:`op_sel` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_pknorm_u16_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`m`::ref:`f32` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_pkrtz_f16_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`m`::ref:`f32` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_rpi_i32_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_u16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_u32_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_u32_u16_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_div_fixup_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_dot2_bf16_bf16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`bf16x2`, :ref:`vsrc1`::ref:`m`::ref:`bf16x2`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_dot2_f16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f16x2`, :ref:`vsrc1`::ref:`m`::ref:`f16x2`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_exp_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_exp_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ffbh_i32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ffbh_u32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ffbl_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_floor_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_floor_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fma_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fma_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fmac_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fmac_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fract_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fract_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_exp_i16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_exp_i32_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_mant_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_mant_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ldexp_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`i16` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ldexp_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`i32` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_lerp_u8_e64_dpp :ref:`vdst`::ref:`u32`, :ref:`vsrc0`::ref:`b32`, :ref:`vsrc1`::ref:`b32`, :ref:`src2`::ref:`b32` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_log_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_log_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_lshl_add_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_lshl_or_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`::ref:`u32`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_lshlrev_b16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_lshlrev_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_lshrrev_b16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_lshrrev_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mad_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mad_i32_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2`::ref:`i32` :ref:`op_sel` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mad_i32_i24_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2`::ref:`i32` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mad_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mad_u32_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2`::ref:`u32` :ref:`op_sel` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mad_u32_u24_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2`::ref:`u32` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max3_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max3_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max3_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max3_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max3_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max3_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_maxmin_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_maxmin_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_maxmin_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_maxmin_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mbcnt_hi_u32_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mbcnt_lo_u32_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_med3_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_med3_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_med3_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_med3_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_med3_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_med3_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min3_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min3_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min3_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min3_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min3_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min3_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_minmax_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_minmax_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_minmax_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_minmax_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mov_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movreld_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movrels_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movrelsd_2_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movrelsd_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_msad_u8_e64_dpp :ref:`vdst`::ref:`u32`, :ref:`vsrc0`::ref:`b32`, :ref:`vsrc1`::ref:`b32`, :ref:`src2`::ref:`b32` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_dx9_zero_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_hi_i32_i24_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_hi_u32_u24_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_i32_i24_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_legacy_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_lo_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_u32_u24_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mullit_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_not_b16_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_not_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_or3_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_or_b16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_or_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_pack_b32_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`op_sel` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_perm_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rcp_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rcp_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rcp_iflag_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rndne_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rndne_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rsq_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rsq_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sad_hi_u8_e64_dpp :ref:`vdst`::ref:`u32`, :ref:`vsrc0`::ref:`u8x4`, :ref:`vsrc1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sad_u16_e64_dpp :ref:`vdst`::ref:`u32`, :ref:`vsrc0`::ref:`u16x2`, :ref:`vsrc1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sad_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sad_u8_e64_dpp :ref:`vdst`::ref:`u32`, :ref:`vsrc0`::ref:`u8x4`, :ref:`vsrc1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sat_pk_u8_i16_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sin_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sin_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sqrt_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sqrt_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_co_ci_u32_e64_dpp :ref:`vdst`, :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`ssrc2` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_co_u32_e64_dpp :ref:`vdst`, :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_nc_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`op_sel` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_nc_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_nc_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`op_sel` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_nc_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_co_ci_u32_e64_dpp :ref:`vdst`, :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`ssrc2` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_co_u32_e64_dpp :ref:`vdst`, :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_nc_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_trunc_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_trunc_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_xad_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_xnor_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_xor3_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_xor_b16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_xor_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + +VOP3 DPP8 +--------- + +.. parsed-literal:: + + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_add3_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_add_co_ci_u32_e64_dpp :ref:`vdst`, :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`ssrc2` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_add_co_u32_e64_dpp :ref:`vdst`, :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_add_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_add_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_add_lshl_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_add_nc_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`op_sel` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_add_nc_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_add_nc_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`op_sel` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_add_nc_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_alignbit_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2`::ref:`b16` :ref:`dpp8_sel` :ref:`fi` + v_alignbyte_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2`::ref:`b16` :ref:`dpp8_sel` :ref:`fi` + v_and_b16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_and_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_and_or_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_ashrrev_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_ashrrev_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_bcnt_u32_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_bfe_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`::ref:`u32`, :ref:`src2`::ref:`u32` :ref:`dpp8_sel` :ref:`fi` + v_bfe_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_bfi_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_bfm_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_bfrev_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ceil_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_ceil_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cls_i32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_clz_i32_u32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cmp_class_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`b16` :ref:`dpp8_sel` :ref:`fi` + v_cmp_class_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`b32` :ref:`dpp8_sel` :ref:`fi` + v_cmp_eq_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_eq_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_eq_i16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_eq_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_eq_u16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_eq_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_f_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_f_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_f_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_f_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ge_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ge_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ge_i16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ge_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ge_u16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ge_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_gt_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_gt_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_gt_i16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_gt_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_gt_u16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_gt_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_le_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_le_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_le_i16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_le_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_le_u16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_le_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lg_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lg_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lt_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lt_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lt_i16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lt_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lt_u16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lt_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ne_i16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ne_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ne_u16_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ne_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_neq_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_neq_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nge_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nge_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ngt_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ngt_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nle_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nle_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nlg_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nlg_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nlt_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nlt_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_o_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_o_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_t_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_t_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_t_i32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_t_u32_e64_dpp :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_tru_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_tru_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_u_f16_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmp_u_f32_e64_dpp :ref:`sdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_class_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`b16` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_class_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`b32` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_eq_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_eq_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_eq_i16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_eq_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_eq_u16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_eq_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_f_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_f_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_f_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_f_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ge_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ge_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ge_i16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ge_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ge_u16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ge_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_gt_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_gt_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_gt_i16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_gt_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_gt_u16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_gt_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_le_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_le_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_le_i16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_le_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_le_u16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_le_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lg_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lg_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lt_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lt_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lt_i16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lt_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lt_u16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lt_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ne_i16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ne_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ne_u16_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ne_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_neq_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_neq_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nge_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nge_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ngt_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ngt_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nle_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nle_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nlg_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nlg_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nlt_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nlt_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_o_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_o_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_t_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_t_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_t_i32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_t_u32_e64_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_tru_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_tru_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_u_f16_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_u_f32_e64_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cndmask_b16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`ssrc2` :ref:`dpp8_sel` :ref:`fi` + v_cndmask_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`ssrc2` :ref:`dpp8_sel` :ref:`fi` + v_cos_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cos_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_ctz_i32_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cubeid_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cubema_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cubesc_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cubetc_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f16_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f16_i16_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f16_u16_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_i32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_u32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte0_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte1_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte2_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte3_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cvt_floor_i32_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp8_sel` :ref:`fi` + v_cvt_flr_i32_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp8_sel` :ref:`fi` + v_cvt_i16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cvt_i32_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cvt_i32_i16_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_nearest_i32_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp8_sel` :ref:`fi` + v_cvt_norm_i16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp8_sel` :ref:`fi` + v_cvt_norm_u16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp8_sel` :ref:`fi` + v_cvt_off_f32_i4_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_cvt_pk_i16_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`m`::ref:`f32` :ref:`dpp8_sel` :ref:`fi` + v_cvt_pk_i16_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`i32`, :ref:`vsrc1`::ref:`i32` :ref:`dpp8_sel` :ref:`fi` + v_cvt_pk_norm_i16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f16`, :ref:`vsrc1`::ref:`m`::ref:`f16` :ref:`op_sel` :ref:`dpp8_sel` :ref:`fi` + v_cvt_pk_norm_u16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f16`, :ref:`vsrc1`::ref:`m`::ref:`f16` :ref:`op_sel` :ref:`dpp8_sel` :ref:`fi` + v_cvt_pk_rtz_f16_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`m`::ref:`f32` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cvt_pk_u16_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`m`::ref:`f32` :ref:`dpp8_sel` :ref:`fi` + v_cvt_pk_u16_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1`::ref:`u32` :ref:`dpp8_sel` :ref:`fi` + v_cvt_pk_u8_f32_e64_dpp :ref:`vdst`::ref:`b32`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`u32`, :ref:`src2`::ref:`u32` :ref:`dpp8_sel` :ref:`fi` + v_cvt_pknorm_i16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f16`, :ref:`vsrc1`::ref:`m`::ref:`f16` :ref:`op_sel` :ref:`dpp8_sel` :ref:`fi` + v_cvt_pknorm_i16_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`m`::ref:`f32` :ref:`dpp8_sel` :ref:`fi` + v_cvt_pknorm_u16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f16`, :ref:`vsrc1`::ref:`m`::ref:`f16` :ref:`op_sel` :ref:`dpp8_sel` :ref:`fi` + v_cvt_pknorm_u16_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`m`::ref:`f32` :ref:`dpp8_sel` :ref:`fi` + v_cvt_pkrtz_f16_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`vsrc1`::ref:`m`::ref:`f32` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cvt_rpi_i32_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp8_sel` :ref:`fi` + v_cvt_u16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cvt_u32_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_cvt_u32_u16_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_div_fixup_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_dot2_bf16_bf16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`bf16x2`, :ref:`vsrc1`::ref:`m`::ref:`bf16x2`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`dpp8_sel` :ref:`fi` + v_dot2_f16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f16x2`, :ref:`vsrc1`::ref:`m`::ref:`f16x2`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`dpp8_sel` :ref:`fi` + v_exp_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_exp_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_ffbh_i32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ffbh_u32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ffbl_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_floor_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_floor_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_fma_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_fma_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_fmac_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_fmac_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_fract_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_fract_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_frexp_exp_i16_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp8_sel` :ref:`fi` + v_frexp_exp_i32_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp8_sel` :ref:`fi` + v_frexp_mant_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_frexp_mant_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_ldexp_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`i16` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_ldexp_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`i32` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_lerp_u8_e64_dpp :ref:`vdst`::ref:`u32`, :ref:`vsrc0`::ref:`b32`, :ref:`vsrc1`::ref:`b32`, :ref:`src2`::ref:`b32` :ref:`dpp8_sel` :ref:`fi` + v_log_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_log_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_lshl_add_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_lshl_or_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`::ref:`u32`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_lshlrev_b16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_lshlrev_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_lshrrev_b16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_lshrrev_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mad_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_mad_i32_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2`::ref:`i32` :ref:`op_sel` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_mad_i32_i24_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2`::ref:`i32` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_mad_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_mad_u32_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2`::ref:`u32` :ref:`op_sel` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_mad_u32_u24_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2`::ref:`u32` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_max3_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_max3_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_max3_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`dpp8_sel` :ref:`fi` + v_max3_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_max3_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`dpp8_sel` :ref:`fi` + v_max3_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_max_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_max_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_max_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_max_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_max_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_max_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_maxmin_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_maxmin_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_maxmin_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_maxmin_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_mbcnt_hi_u32_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mbcnt_lo_u32_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_med3_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_med3_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_med3_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`dpp8_sel` :ref:`fi` + v_med3_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_med3_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`dpp8_sel` :ref:`fi` + v_med3_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_min3_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_min3_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_min3_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`dpp8_sel` :ref:`fi` + v_min3_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_min3_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`op_sel` :ref:`dpp8_sel` :ref:`fi` + v_min3_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_min_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_min_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_min_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_min_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_min_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_min_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_minmax_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_minmax_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_minmax_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_minmax_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_mov_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movreld_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movrels_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movrelsd_2_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movrelsd_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_msad_u8_e64_dpp :ref:`vdst`::ref:`u32`, :ref:`vsrc0`::ref:`b32`, :ref:`vsrc1`::ref:`b32`, :ref:`src2`::ref:`b32` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_mul_dx9_zero_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_mul_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_mul_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_mul_hi_i32_i24_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_hi_u32_u24_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_i32_i24_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_mul_legacy_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_mul_lo_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_u32_u24_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_mullit_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_not_b16_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_not_b32_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_or3_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_or_b16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_or_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_pack_b32_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`op_sel` :ref:`dpp8_sel` :ref:`fi` + v_perm_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_rcp_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_rcp_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_rcp_iflag_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_rndne_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_rndne_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_rsq_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_rsq_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_sad_hi_u8_e64_dpp :ref:`vdst`::ref:`u32`, :ref:`vsrc0`::ref:`u8x4`, :ref:`vsrc1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_sad_u16_e64_dpp :ref:`vdst`::ref:`u32`, :ref:`vsrc0`::ref:`u16x2`, :ref:`vsrc1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_sad_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_sad_u8_e64_dpp :ref:`vdst`::ref:`u32`, :ref:`vsrc0`::ref:`u8x4`, :ref:`vsrc1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_sat_pk_u8_i16_e64_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sin_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_sin_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_sqrt_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_sqrt_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_sub_co_ci_u32_e64_dpp :ref:`vdst`, :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`ssrc2` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_sub_co_u32_e64_dpp :ref:`vdst`, :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_sub_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_sub_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_sub_nc_i16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`op_sel` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_sub_nc_i32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_sub_nc_u16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`op_sel` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_sub_nc_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_subrev_co_ci_u32_e64_dpp :ref:`vdst`, :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`ssrc2` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_subrev_co_u32_e64_dpp :ref:`vdst`, :ref:`sdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_subrev_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_subrev_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_subrev_nc_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_trunc_f16_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_trunc_f32_e64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dpp8_sel` :ref:`fi` + v_xad_u32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_xnor_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_xor3_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`src2` :ref:`dpp8_sel` :ref:`fi` + v_xor_b16_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_xor_b32_e64_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + +VOP3P +----- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_dot2_f32_bf16 :ref:`vdst`, :ref:`src0`::ref:`bf16x2`, :ref:`src1`::ref:`bf16x2`, :ref:`src2`::ref:`f32` :ref:`clamp` + v_dot2_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`f16x2`, :ref:`src1`::ref:`f16x2`, :ref:`src2`::ref:`f32` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_dot4_i32_i8 :ref:`vdst`, :ref:`src0`::ref:`iu8x4`, :ref:`src1`::ref:`iu8x4`, :ref:`src2`::ref:`i32` :ref:`neg_lo` + v_dot4_i32_iu8 :ref:`vdst`, :ref:`src0`::ref:`iu8x4`, :ref:`src1`::ref:`iu8x4`, :ref:`src2`::ref:`i32` :ref:`neg_lo` + v_dot4_u32_u8 :ref:`vdst`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` + v_dot8_i32_i4 :ref:`vdst`, :ref:`src0`::ref:`iu4x8`, :ref:`src1`::ref:`iu4x8`, :ref:`src2`::ref:`i32` :ref:`neg_lo` :ref:`clamp` + v_dot8_i32_iu4 :ref:`vdst`, :ref:`src0`::ref:`iu4x8`, :ref:`src1`::ref:`iu4x8`, :ref:`src2`::ref:`i32` :ref:`neg_lo` :ref:`clamp` + v_dot8_u32_u4 :ref:`vdst`, :ref:`src0`::ref:`u4x8`, :ref:`src1`::ref:`u4x8`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_fma_mix_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_fma_mixhi_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_fma_mixlo_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_pk_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_pk_add_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_pk_add_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_pk_ashrrev_i16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_fma_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_pk_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_lshrrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_pk_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_pk_max_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_pk_max_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_max_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_pk_min_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_min_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_pk_mul_lo_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_sub_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_pk_sub_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_wmma_bf16_16x16x16_bf16 :ref:`vdst`::ref:`bf16x4/8`, :ref:`vsrc0`::ref:`bf16x16`, :ref:`vsrc1`::ref:`bf16x16`, :ref:`src2`::ref:`bf16x4/8` :ref:`op_sel` :ref:`neg_lo` :ref:`neg_hi` + v_wmma_f16_16x16x16_f16 :ref:`vdst`::ref:`f16x4/8`, :ref:`vsrc0`::ref:`f16x16`, :ref:`vsrc1`::ref:`f16x16`, :ref:`src2`::ref:`f16x4/8` :ref:`op_sel` :ref:`neg_lo` :ref:`neg_hi` + v_wmma_f32_16x16x16_bf16 :ref:`vdst`::ref:`f32x4/8`, :ref:`vsrc0`::ref:`f16x16`, :ref:`vsrc1`::ref:`f16x16`, :ref:`src2`::ref:`f32x4/8` :ref:`neg_lo` :ref:`neg_hi` + v_wmma_f32_16x16x16_f16 :ref:`vdst`::ref:`f32x4/8`, :ref:`vsrc0`::ref:`f16x16`, :ref:`vsrc1`::ref:`f16x16`, :ref:`src2`::ref:`f32x4/8` :ref:`neg_lo` :ref:`neg_hi` + v_wmma_i32_16x16x16_iu4 :ref:`vdst`::ref:`i32x4/8`, :ref:`vsrc0`::ref:`iu4x16`, :ref:`vsrc1`::ref:`iu4x16`, :ref:`src2`::ref:`i32x4/8` :ref:`neg_lo` :ref:`clamp` + v_wmma_i32_16x16x16_iu8 :ref:`vdst`::ref:`i32x4/8`, :ref:`vsrc0`::ref:`iu8x16`, :ref:`vsrc1`::ref:`iu8x16`, :ref:`src2`::ref:`i32x4/8` :ref:`neg_lo` :ref:`clamp` + +VOP3P DPP16 +----------- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_fma_mix_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`fx`, :ref:`vsrc1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fma_mixhi_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`fx`, :ref:`vsrc1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fma_mixlo_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`fx`, :ref:`vsrc1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + +VOP3P DPP8 +---------- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_fma_mix_f32_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`fx`, :ref:`vsrc1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_fma_mixhi_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`fx`, :ref:`vsrc1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + v_fma_mixlo_f16_e64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`fx`, :ref:`vsrc1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` :ref:`dpp8_sel` :ref:`fi` + +VOPC +---- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_cmp_class_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b16` + v_cmp_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmp_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmp_eq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_class_f16 :ref:`src0`, :ref:`vsrc1`::ref:`b16` + v_cmpx_class_f32 :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmpx_class_f64 :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmpx_eq_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f64 :ref:`src0`, :ref:`vsrc1` + +VOPC DPP16 +---------- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_cmp_class_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`b16` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_class_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`b32` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_eq_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_eq_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_eq_i16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_eq_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_eq_u16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_eq_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_f_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_f_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_f_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_f_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ge_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ge_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ge_i16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ge_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ge_u16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ge_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_gt_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_gt_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_gt_i16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_gt_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_gt_u16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_gt_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_le_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_le_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_le_i16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_le_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_le_u16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_le_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lg_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lg_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lt_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lt_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lt_i16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lt_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lt_u16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_lt_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ne_i16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ne_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ne_u16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ne_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_neq_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_neq_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nge_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nge_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ngt_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_ngt_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nle_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nle_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nlg_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nlg_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nlt_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_nlt_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_o_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_o_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_t_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_t_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_t_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_t_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_tru_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_tru_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_u_f16_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmp_u_f32_dpp :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_class_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`b16` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_class_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`b32` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_eq_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_eq_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_eq_i16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_eq_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_eq_u16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_eq_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_f_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_f_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_f_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_f_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ge_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ge_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ge_i16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ge_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ge_u16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ge_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_gt_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_gt_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_gt_i16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_gt_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_gt_u16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_gt_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_le_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_le_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_le_i16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_le_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_le_u16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_le_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lg_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lg_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lt_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lt_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lt_i16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lt_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lt_u16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_lt_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ne_i16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ne_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ne_u16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ne_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_neq_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_neq_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nge_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nge_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ngt_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_ngt_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nle_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nle_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nlg_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nlg_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nlt_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_nlt_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_o_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_o_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_t_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_t_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_t_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_t_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_tru_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_tru_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_u_f16_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cmpx_u_f32_dpp :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + +VOPC DPP8 +--------- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_cmp_class_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`::ref:`b16` :ref:`dpp8_sel` :ref:`fi` + v_cmp_class_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`::ref:`b32` :ref:`dpp8_sel` :ref:`fi` + v_cmp_eq_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_eq_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_eq_i16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_eq_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_eq_u16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_eq_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_f_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_f_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_f_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_f_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ge_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ge_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ge_i16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ge_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ge_u16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ge_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_gt_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_gt_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_gt_i16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_gt_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_gt_u16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_gt_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_le_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_le_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_le_i16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_le_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_le_u16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_le_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lg_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lg_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lt_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lt_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lt_i16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lt_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lt_u16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_lt_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ne_i16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ne_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ne_u16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ne_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_neq_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_neq_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nge_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nge_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ngt_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_ngt_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nle_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nle_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nlg_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nlg_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nlt_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_nlt_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_o_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_o_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_t_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_t_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_t_i32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_t_u32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_tru_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_tru_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_u_f16_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmp_u_f32_dpp :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_class_f16_dpp :ref:`vsrc0`, :ref:`vsrc1`::ref:`b16` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_class_f32_dpp :ref:`vsrc0`, :ref:`vsrc1`::ref:`b32` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_eq_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_eq_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_eq_i16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_eq_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_eq_u16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_eq_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_f_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_f_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_f_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_f_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ge_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ge_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ge_i16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ge_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ge_u16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ge_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_gt_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_gt_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_gt_i16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_gt_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_gt_u16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_gt_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_le_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_le_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_le_i16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_le_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_le_u16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_le_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lg_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lg_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lt_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lt_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lt_i16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lt_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lt_u16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_lt_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ne_i16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ne_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ne_u16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ne_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_neq_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_neq_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nge_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nge_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ngt_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_ngt_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nle_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nle_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nlg_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nlg_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nlt_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_nlt_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_o_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_o_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_t_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_t_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_t_i32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_t_u32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_tru_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_tru_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_u_f16_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_cmpx_u_f32_dpp :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + +VOPDX +----- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_dual_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_cndmask_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_dot2acc_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` + v_dual_fmaak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` + v_dual_fmac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_fmamk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` + v_dual_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_mov_b32 :ref:`vdst`, :ref:`src` + v_dual_mul_dx9_zero_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + +VOPDY +----- + +.. parsed-literal:: + + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_dual_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_add_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_and_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_cndmask_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_dot2acc_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` + v_dual_fmaak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` + v_dual_fmac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_fmamk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` + v_dual_lshlrev_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_mov_b32 :ref:`vdst`, :ref:`src` + v_dual_mul_dx9_zero_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_dual_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + +.. |---| unicode:: U+02014 .. em dash + +.. toctree:: + :hidden: + + gfx11_attr + gfx11_delay + gfx11_dst + gfx11_fx_operand + gfx11_hwreg + gfx11_imm16_0533c2 + gfx11_imm16_169952 + gfx11_label + gfx11_m_181aa0 + gfx11_m_c141fc + gfx11_msg_b8ff6d + gfx11_msg_e37f7b + gfx11_opt + gfx11_saddr_844ded + gfx11_saddr_8a0af3 + gfx11_saddr_beaa25 + gfx11_sbase_30e75b + gfx11_sbase_b0aa25 + gfx11_sdst_0804b1 + gfx11_sdst_362c37 + gfx11_sdst_386c33 + gfx11_sdst_3bc700 + gfx11_sdst_3cd7ad + gfx11_sdst_54e16e + gfx11_sdst_8078f5 + gfx11_sdst_ea3f10 + gfx11_simm32_6f0844 + gfx11_simm32_a3e80c + gfx11_simm32_be0c1c + gfx11_soffset_0f304c + gfx11_soffset_73dae7 + gfx11_soffset_fef808 + gfx11_src_0879fb + gfx11_src_17933a + gfx11_src_25d8ac + gfx11_src_7af462 + gfx11_src_852d86 + gfx11_src_9cb8cf + gfx11_src_d01e4c + gfx11_src_d5ffa3 + gfx11_srsrc_5dafbc + gfx11_srsrc_80eef6 + gfx11_srsrc_cf7132 + gfx11_ssamp + gfx11_ssrc_05f584 + gfx11_ssrc_121527 + gfx11_ssrc_1a3009 + gfx11_ssrc_361664 + gfx11_ssrc_460c63 + gfx11_ssrc_6fbc49 + gfx11_ssrc_81ba27 + gfx11_ssrc_8dd4e0 + gfx11_tgt + gfx11_type_deviation_8d2078 + gfx11_type_deviation_a14eb1 + gfx11_vaddr_0212e3 + gfx11_vaddr_0bfea4 + gfx11_vaddr_6ab80d + gfx11_vaddr_9f7133 + gfx11_vaddr_a5639c + gfx11_vaddr_b73dc0 + gfx11_vaddr_f20ee4 + gfx11_vcc + gfx11_vdata0_6802ce + gfx11_vdata0_fd235e + gfx11_vdata1_6802ce + gfx11_vdata1_e016a1 + gfx11_vdata1_fd235e + gfx11_vdata_21b58d + gfx11_vdata_2d6239 + gfx11_vdata_4b260e + gfx11_vdata_56f215 + gfx11_vdata_6802ce + gfx11_vdata_84fab6 + gfx11_vdata_aa5a53 + gfx11_vdata_ad559c + gfx11_vdata_c08393 + gfx11_vdata_e016a1 + gfx11_vdata_fd235e + gfx11_vdst_227281 + gfx11_vdst_463513 + gfx11_vdst_48e42f + gfx11_vdst_5d50a1 + gfx11_vdst_5ec176 + gfx11_vdst_69a144 + gfx11_vdst_709347 + gfx11_vdst_81a6ed + gfx11_vdst_89680f + gfx11_vdst_9041ac + gfx11_vdst_a49b76 + gfx11_vdst_bdb32f + gfx11_vdst_d0dc43 + gfx11_vdst_d180f4 + gfx11_vdst_d71f1c + gfx11_vdst_d7c57e + gfx11_vdst_dd8a32 + gfx11_vdst_dfa6da + gfx11_vdst_e2d005 + gfx11_vdst_eae4c8 + gfx11_vdst_f47754 + gfx11_vij + gfx11_vparam + gfx11_vparam0 + gfx11_vsrc_1c4e7f + gfx11_vsrc_24f3d2 + gfx11_vsrc_6802ce + gfx11_vsrc_731030 + gfx11_vsrc_e016a1 + gfx11_vsrc_fd235e + gfx11_waitcnt + gfx11_waitcnt_depctr diff --git a/llvm/docs/AMDGPU/gfx11_attr.rst b/llvm/docs/AMDGPU/gfx11_attr.rst new file mode 100644 index 0000000000000..a625afa4ed9ab --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_attr.rst @@ -0,0 +1,28 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_attr: + +attr +==== + +Interpolation attribute and channel: + + ============== =================================== + Syntax Description + ============== =================================== + attr{0..32}.x Attribute 0..32 with *x* channel. + attr{0..32}.y Attribute 0..32 with *y* channel. + attr{0..32}.z Attribute 0..32 with *z* channel. + attr{0..32}.w Attribute 0..32 with *w* channel. + ============== =================================== + +Examples: + +.. parsed-literal:: + + lds_param_load v5, attr0.z diff --git a/llvm/docs/AMDGPU/gfx11_delay.rst b/llvm/docs/AMDGPU/gfx11_delay.rst new file mode 100644 index 0000000000000..a773c2887f87a --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_delay.rst @@ -0,0 +1,81 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_delay: + +delay +===== + +A delay between dependent SALU/VALU instructions. +This operand may specify a delay for 2 instructions: +the one after the current *s_delay_alu* instruction +and for the second instruction indicated by *SKIP*. + +The bits of this operand have the following meaning: + + ===== ========================================================== ============ + Bits Description Value Range + ===== ========================================================== ============ + 3:0 ID0: indicates a delay for the first instruction. 0..11 + 6:4 SKIP: indicates the position of the second instruction. 0..5 + 10:7 ID1: indicates a delay for the second instruction. 0..11 + ===== ========================================================== ============ + +This operand may be specified as one of the following: + +* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from 0 to 0xFFFF. +* A combination of *instid0*, *instskip*, *instid1* values which are described below. + + ======================== =========================== =============== + Syntax Description Default Value + ======================== =========================== =============== + instid0(<*ID name*>) A symbolic *ID0* value. instid0(NO_DEP) + instskip(<*SKIP name*>) A symbolic *SKIP* value. instskip(SAME) + instid1(<*ID name*>) A symbolic *ID1* value. instid1(NO_DEP) + ======================== =========================== =============== + +These values may be specified in any order. +When more than one value is specified, the values must be separated from each other by a '|'. + +Valid *ID names* are defined below. + + =================== =================================================================== + Name Description + =================== =================================================================== + NO_DEP No dependency on any prior instruction. This is the default value. + VALU_DEP_1 Dependency on a previous VALU instruction, 1 opcode back. + VALU_DEP_2 Dependency on a previous VALU instruction, 2 opcodes back. + VALU_DEP_3 Dependency on a previous VALU instruction, 3 opcodes back. + VALU_DEP_4 Dependency on a previous VALU instruction, 4 opcodes back. + TRANS32_DEP_1 Dependency on a previous TRANS32 instruction, 1 opcode back. + TRANS32_DEP_2 Dependency on a previous TRANS32 instruction, 2 opcodes back. + TRANS32_DEP_3 Dependency on a previous TRANS32 instruction, 3 opcodes back. + FMA_ACCUM_CYCLE_1 Single cycle penalty for FMA accumulation. + SALU_CYCLE_1 1 cycle penalty for a prior SALU instruction. + SALU_CYCLE_2 2 cycle penalty for a prior SALU instruction. + SALU_CYCLE_3 3 cycle penalty for a prior SALU instruction. + =================== =================================================================== + +Legal *SKIP names* are described in the following table. + + ======== ============================================================================ + Name Description + ======== ============================================================================ + SAME Apply second dependency to the same instruction. This is the default value. + NEXT Apply second dependency to the next instruction. + SKIP_1 Skip 1 instruction then apply dependency. + SKIP_2 Skip 2 instructions then apply dependency. + SKIP_3 Skip 3 instructions then apply dependency. + SKIP_4 Skip 4 instructions then apply dependency. + ======== ============================================================================ + +Examples: + +.. parsed-literal:: + + s_delay_alu instid0(VALU_DEP_1) + s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) diff --git a/llvm/docs/AMDGPU/gfx11_dst.rst b/llvm/docs/AMDGPU/gfx11_dst.rst new file mode 100644 index 0000000000000..49e4af6e1eb25 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_dst.rst @@ -0,0 +1,13 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_dst: + +dst +=== + +This is an input operand. It may optionally serve as a destination if :ref:`glc` is specified. diff --git a/llvm/docs/AMDGPU/gfx11_fx_operand.rst b/llvm/docs/AMDGPU/gfx11_fx_operand.rst new file mode 100644 index 0000000000000..b569f56765fe8 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_fx_operand.rst @@ -0,0 +1,16 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_fx_operand: + +FX Operand +========== + +This is a *f32* or *f16* operand depending on instruction modifiers: + +* Operand size is controlled by :ref:`m_op_sel_hi`. +* Location of the 16-bit operand is controlled by :ref:`m_op_sel`. diff --git a/llvm/docs/AMDGPU/gfx11_hwreg.rst b/llvm/docs/AMDGPU/gfx11_hwreg.rst new file mode 100644 index 0000000000000..1d1e8e2de28be --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_hwreg.rst @@ -0,0 +1,76 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_hwreg: + +hwreg +===== + +Bits of a hardware register being accessed. + +The bits of this operand have the following meaning: + + ======= ===================== ============ + Bits Description Value Range + ======= ===================== ============ + 5:0 Register *id*. 0..63 + 10:6 First bit *offset*. 0..31 + 15:11 *Size* in bits. 1..32 + ======= ===================== ============ + +This operand may be specified as one of the following: + +* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from 0 to 0xFFFF. +* An *hwreg* value which is described below. + + ==================================== =============================================================================== + Hwreg Value Syntax Description + ==================================== =============================================================================== + hwreg({0..63}) All bits of a register indicated by the register *id*. + hwreg(<*name*>) All bits of a register indicated by the register *name*. + hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by the register *id*, first bit *offset* and *size*. + hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by the register *name*, first bit *offset* and *size*. + ==================================== =============================================================================== + +Numeric values may be specified as positive :ref:`integer numbers` +or :ref:`absolute expressions`. + +Predefined register *names* include: + + ============================== ========================================== + Name Description + ============================== ========================================== + HW_REG_MODE Shader writable mode bits. + HW_REG_STATUS Shader read-only status. + HW_REG_TRAPSTS Trap status. + HW_REG_HW_ID1 Id of wave, simd, compute unit, etc. + HW_REG_HW_ID2 Id of queue, pipeline, etc. + HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation. + HW_REG_LDS_ALLOC Per-wave LDS allocation. + HW_REG_IB_STS Counters of outstanding instructions. + HW_REG_SH_MEM_BASES Memory aperture. + HW_REG_FLAT_SCR_LO flat_scratch_lo register. + HW_REG_FLAT_SCR_HI flat_scratch_hi register. + ============================== ========================================== + +Examples: + +.. parsed-literal:: + + reg = 1 + offset = 2 + size = 4 + hwreg_enc = reg | (offset << 6) | ((size - 1) << 11) + + s_getreg_b32 s2, 0x1881 + s_getreg_b32 s2, hwreg_enc // the same as above + s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above + s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above + + s_getreg_b32 s2, hwreg(15) + s_getreg_b32 s2, hwreg(51, 1, 31) + s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) diff --git a/llvm/docs/AMDGPU/gfx11_imm16_0533c2.rst b/llvm/docs/AMDGPU/gfx11_imm16_0533c2.rst new file mode 100644 index 0000000000000..7838d7ecb501f --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_imm16_0533c2.rst @@ -0,0 +1,13 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_imm16_0533c2: + +imm16 +===== + +An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from -32768 to 65535. diff --git a/llvm/docs/AMDGPU/gfx11_imm16_169952.rst b/llvm/docs/AMDGPU/gfx11_imm16_169952.rst new file mode 100644 index 0000000000000..b1dc16a88ba5e --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_imm16_169952.rst @@ -0,0 +1,13 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_imm16_169952: + +imm16 +===== + +An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from 0 to 65535. diff --git a/llvm/docs/AMDGPU/gfx11_label.rst b/llvm/docs/AMDGPU/gfx11_label.rst new file mode 100644 index 0000000000000..1887236c136de --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_label.rst @@ -0,0 +1,36 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_label: + +label +===== + +A branch target, which is a 16-bit signed integer treated as a PC-relative dword offset. + +This operand may be specified as one of the following: + +* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from -32768 to 65535. +* A :ref:`symbol` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker. + +Examples: + +.. parsed-literal:: + + offset = 30 + label_1: + label_2 = . + 4 + + s_branch 32 + s_branch offset + 2 + s_branch label_1 + s_branch label_2 + s_branch label_3 + s_branch label_4 + + label_3 = label_2 + 4 + label_4: diff --git a/llvm/docs/AMDGPU/gfx11_m_181aa0.rst b/llvm/docs/AMDGPU/gfx11_m_181aa0.rst new file mode 100644 index 0000000000000..e5bed6c76c2dc --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_m_181aa0.rst @@ -0,0 +1,13 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_m_181aa0: + +m += + +This operand may be used with a floating-point operand modifier :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx11_m_c141fc.rst b/llvm/docs/AMDGPU/gfx11_m_c141fc.rst new file mode 100644 index 0000000000000..30b7283dbf5f9 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_m_c141fc.rst @@ -0,0 +1,13 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_m_c141fc: + +m += + +This operand may be used with floating-point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx11_msg_b8ff6d.rst b/llvm/docs/AMDGPU/gfx11_msg_b8ff6d.rst new file mode 100644 index 0000000000000..ff7fd762323da --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_msg_b8ff6d.rst @@ -0,0 +1,44 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_msg_b8ff6d: + +msg +=== + +A 16-bit message code. The bits of this operand have the following meaning: + + ============ =============================== =============== + Bits Description Value Range + ============ =============================== =============== + 6:0 Message *type*. 0..127 + 7:7 Must be 1. 1 + 15:8 Unused. \- + ============ =============================== =============== + + This operand may be specified as one of the following: + + * An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from 0 to 0xFFFF. + * A *sendmsg* value which is described below. + + ==================================== ==================================================== + Sendmsg Value Syntax Description + ==================================== ==================================================== + sendmsg(MSG_RTN_GET_DOORBELL) Get doorbell ID. + sendmsg(MSG_RTN_GET_DDID) Get Draw/Dispatch ID. + sendmsg(MSG_RTN_GET_TMA) Get TMA value. + sendmsg(MSG_RTN_GET_TBA) Get TBA value. + sendmsg(MSG_RTN_GET_REALTIME) Get REALTIME value. + sendmsg(MSG_RTN_SAVE_WAVE) Report that this wave is ready to be context-saved. + ==================================== ==================================================== + +Examples: + +.. parsed-literal:: + + s_sendmsg_rtn_b32 s0, 132 + s_sendmsg_rtn_b32 s0, sendmsg(MSG_GET_REALTIME) diff --git a/llvm/docs/AMDGPU/gfx11_msg_e37f7b.rst b/llvm/docs/AMDGPU/gfx11_msg_e37f7b.rst new file mode 100644 index 0000000000000..050ecd9148e5c --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_msg_e37f7b.rst @@ -0,0 +1,85 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_msg_e37f7b: + +msg +=== + +A 16-bit message code. The bits of this operand have the following meaning: + + ============ =============================== =============== + Bits Description Value Range + ============ =============================== =============== + 3:0 Message *type*. 0..15 + 6:4 Optional *operation*. 0..7 + 7:7 Must be 0. 0 + 9:8 Optional *stream*. 0..3 + 15:10 Unused. \- + ============ =============================== =============== + +This operand may be specified as one of the following: + +* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from 0 to 0xFFFF. +* A *sendmsg* value which is described below. + + ==================================== ==================================================== + Sendmsg Value Syntax Description + ==================================== ==================================================== + sendmsg(<*type*>) A message identified by its *type*. + sendmsg(<*type*>,<*op*>) A message identified by its *type* and *operation*. + sendmsg(<*type*>,<*op*>,<*stream*>) A message identified by its *type* and *operation* + with a stream *id*. + ==================================== ==================================================== + +*Type* may be specified using message *name* or message *id*. + +*Op* may be specified using operation *name* or operation *id*. + +Stream *id* is an integer in the range from 0 to 3. + +Numeric values may be specified as positive :ref:`integer numbers` +or :ref:`absolute expressions`. + +Each message type supports specific operations: + + ====================== ========== ============================== ============ ========== + Message name Message Id Supported Operations Operation Id Stream Id + ====================== ========== ============================== ============ ========== + MSG_INTERRUPT 1 \- \- \- + MSG_HS_TESSFACTOR 2 \- \- \- + MSG_DEALLOC_VGPRS 3 \- \- \- + MSG_STALL_WAVE_GEN 5 \- \- \- + MSG_HALT_WAVES 6 \- \- \- + MSG_GS_ALLOC_REQ 9 \- \- \- + MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \- + \ SYSMSG_OP_REG_RD 2 \- + \ SYSMSG_OP_TTRACE_PC 4 \- + ====================== ========== ============================== ============ ========== + +*Sendmsg* arguments are validated depending on how *type* value is specified: + +* If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above. +* If message *type* is specified as a number, each argument must not exceed the corresponding value range (see the first table). + +Examples: + +.. parsed-literal:: + + // numeric message code + msg = 0x10 + s_sendmsg 0x12 + s_sendmsg msg + 2 + + // sendmsg with strict arguments validation + s_sendmsg sendmsg(MSG_INTERRUPT) + s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC) + + // sendmsg with validation of value range only + msg = 2 + op = 3 + s_sendmsg sendmsg(msg, op) diff --git a/llvm/docs/AMDGPU/gfx11_opt.rst b/llvm/docs/AMDGPU/gfx11_opt.rst new file mode 100644 index 0000000000000..9c0a41c529988 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_opt.rst @@ -0,0 +1,13 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_opt: + +opt +=== + +This is an optional operand. It must be used if and only if :ref:`glc` is specified. diff --git a/llvm/docs/AMDGPU/gfx11_saddr_844ded.rst b/llvm/docs/AMDGPU/gfx11_saddr_844ded.rst new file mode 100644 index 0000000000000..55ea1b501d85c --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_saddr_844ded.rst @@ -0,0 +1,21 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_saddr_844ded: + +saddr +===== + +A 64-bit flat global address. Must be specified as :ref:`off` if not used. + +The final memory address is computed as follows: + +* Address = [:ref:`saddr`] + :ref:`offset13s` + ThreadID * 4. + +*Size:* 2 dwords. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`off` diff --git a/llvm/docs/AMDGPU/gfx11_saddr_8a0af3.rst b/llvm/docs/AMDGPU/gfx11_saddr_8a0af3.rst new file mode 100644 index 0000000000000..b51fb36f14e9c --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_saddr_8a0af3.rst @@ -0,0 +1,19 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_saddr_8a0af3: + +saddr +===== + +An optional 32-bit flat scratch offset. Must be specified as :ref:`off` if not used. + +* Offset = [:ref:`vaddr`] + [:ref:`saddr`] + :ref:`offset13s`. + +*Size:* 1 dword. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`off` diff --git a/llvm/docs/AMDGPU/gfx11_saddr_beaa25.rst b/llvm/docs/AMDGPU/gfx11_saddr_beaa25.rst new file mode 100644 index 0000000000000..1b6ea12a04d6d --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_saddr_beaa25.rst @@ -0,0 +1,19 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_saddr_beaa25: + +saddr +===== + +An optional 64-bit flat global address. Must be specified as :ref:`off` if not used. + +See :ref:`vaddr` for description of available addressing modes. + +*Size:* 2 dwords. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`off` diff --git a/llvm/docs/AMDGPU/gfx11_sbase_30e75b.rst b/llvm/docs/AMDGPU/gfx11_sbase_30e75b.rst new file mode 100644 index 0000000000000..11c039fd8f615 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_sbase_30e75b.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_sbase_30e75b: + +sbase +===== + +A 64-bit base address for scalar memory operations. + +*Size:* 2 dwords. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null` diff --git a/llvm/docs/AMDGPU/gfx11_sbase_b0aa25.rst b/llvm/docs/AMDGPU/gfx11_sbase_b0aa25.rst new file mode 100644 index 0000000000000..acbb6f8981dc4 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_sbase_b0aa25.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_sbase_b0aa25: + +sbase +===== + +A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size, and a stride. + +*Size:* 4 dwords. + +*Operands:* :ref:`s`, :ref:`ttmp` diff --git a/llvm/docs/AMDGPU/gfx11_sdst_0804b1.rst b/llvm/docs/AMDGPU/gfx11_sdst_0804b1.rst new file mode 100644 index 0000000000000..5d8c0a0e664d9 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_sdst_0804b1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_sdst_0804b1: + +sdst +==== + +Instruction output. + +*Size:* 4 dwords. + +*Operands:* :ref:`s`, :ref:`ttmp` diff --git a/llvm/docs/AMDGPU/gfx11_sdst_362c37.rst b/llvm/docs/AMDGPU/gfx11_sdst_362c37.rst new file mode 100644 index 0000000000000..cdd9a2eb2f29b --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_sdst_362c37.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_sdst_362c37: + +sdst +==== + +Instruction output. + +*Size:* 8 dwords. + +*Operands:* :ref:`s`, :ref:`ttmp` diff --git a/llvm/docs/AMDGPU/gfx11_sdst_386c33.rst b/llvm/docs/AMDGPU/gfx11_sdst_386c33.rst new file mode 100644 index 0000000000000..5a7e5e9cfc4f4 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_sdst_386c33.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_sdst_386c33: + +sdst +==== + +Instruction output. + +*Size:* 2 dwords. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null` diff --git a/llvm/docs/AMDGPU/gfx11_sdst_3bc700.rst b/llvm/docs/AMDGPU/gfx11_sdst_3bc700.rst new file mode 100644 index 0000000000000..5edb588cbf57a --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_sdst_3bc700.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_sdst_3bc700: + +sdst +==== + +Instruction output. + +*Size:* 16 dwords. + +*Operands:* :ref:`s`, :ref:`ttmp` diff --git a/llvm/docs/AMDGPU/gfx11_sdst_3cd7ad.rst b/llvm/docs/AMDGPU/gfx11_sdst_3cd7ad.rst new file mode 100644 index 0000000000000..a87487ab89210 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_sdst_3cd7ad.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_sdst_3cd7ad: + +sdst +==== + +Instruction output. + +*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null` diff --git a/llvm/docs/AMDGPU/gfx11_sdst_54e16e.rst b/llvm/docs/AMDGPU/gfx11_sdst_54e16e.rst new file mode 100644 index 0000000000000..3815fd09dbe78 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_sdst_54e16e.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_sdst_54e16e: + +sdst +==== + +Instruction output. + +*Size:* 1 dword. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null` diff --git a/llvm/docs/AMDGPU/gfx11_sdst_8078f5.rst b/llvm/docs/AMDGPU/gfx11_sdst_8078f5.rst new file mode 100644 index 0000000000000..75edf5f0b4319 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_sdst_8078f5.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_sdst_8078f5: + +sdst +==== + +Instruction output. + +*Size:* 1 dword. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`m0`, :ref:`exec` diff --git a/llvm/docs/AMDGPU/gfx11_sdst_ea3f10.rst b/llvm/docs/AMDGPU/gfx11_sdst_ea3f10.rst new file mode 100644 index 0000000000000..2412cb1000d76 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_sdst_ea3f10.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_sdst_ea3f10: + +sdst +==== + +Instruction output. + +*Size:* 2 dwords. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`exec` diff --git a/llvm/docs/AMDGPU/gfx11_simm32_6f0844.rst b/llvm/docs/AMDGPU/gfx11_simm32_6f0844.rst new file mode 100644 index 0000000000000..0c4395a899007 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_simm32_6f0844.rst @@ -0,0 +1,14 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_simm32_6f0844: + +simm32 +====== + +A :ref:`floating-point_number`, an :ref:`integer_number`, or an :ref:`absolute_expression`. +The value is converted to *f32* as described :ref:`here`. diff --git a/llvm/docs/AMDGPU/gfx11_simm32_a3e80c.rst b/llvm/docs/AMDGPU/gfx11_simm32_a3e80c.rst new file mode 100644 index 0000000000000..5e965a011cfff --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_simm32_a3e80c.rst @@ -0,0 +1,13 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_simm32_a3e80c: + +simm32 +====== + +An :ref:`integer_number` or an :ref:`absolute_expression`. The value is truncated to 32 bits. diff --git a/llvm/docs/AMDGPU/gfx11_simm32_be0c1c.rst b/llvm/docs/AMDGPU/gfx11_simm32_be0c1c.rst new file mode 100644 index 0000000000000..38a27b5a6011f --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_simm32_be0c1c.rst @@ -0,0 +1,14 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_simm32_be0c1c: + +simm32 +====== + +A :ref:`floating-point_number`, an :ref:`integer_number`, or an :ref:`absolute_expression`. +The value is converted to *f16* as described :ref:`here`. diff --git a/llvm/docs/AMDGPU/gfx11_soffset_0f304c.rst b/llvm/docs/AMDGPU/gfx11_soffset_0f304c.rst new file mode 100644 index 0000000000000..b333d553671a2 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_soffset_0f304c.rst @@ -0,0 +1,19 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_soffset_0f304c: + +soffset +======= + +An unsigned offset from the base address. May be specified as either a register or a 20-bit immediate. + +Note that an *immediate* offset may be specified using either :ref:`uimm20` operand or :ref:`offset20u` modifier, but not both. + +*Size:* 1 dword. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`m0`, :ref:`uimm20` diff --git a/llvm/docs/AMDGPU/gfx11_soffset_73dae7.rst b/llvm/docs/AMDGPU/gfx11_soffset_73dae7.rst new file mode 100644 index 0000000000000..899974d56e218 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_soffset_73dae7.rst @@ -0,0 +1,22 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_soffset_73dae7: + +soffset +======= + +An offset from the base address. + +* If offset is specified as a register, it supplies an unsigned byte offset. +* If offset is specified as a 21-bit immediate, it supplies a signed byte offset. + +Note that an *immediate* offset may be specified using either :ref:`simm21` operand or :ref:`offset21s` modifier, but not both. + +*Size:* 1 dword. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`m0`, :ref:`simm21` diff --git a/llvm/docs/AMDGPU/gfx11_soffset_fef808.rst b/llvm/docs/AMDGPU/gfx11_soffset_fef808.rst new file mode 100644 index 0000000000000..44ba8a8b4ed10 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_soffset_fef808.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_soffset_fef808: + +soffset +======= + +An unsigned byte offset. + +*Size:* 1 dword. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`m0`, :ref:`iconst`, :ref:`fconst` diff --git a/llvm/docs/AMDGPU/gfx11_src_0879fb.rst b/llvm/docs/AMDGPU/gfx11_src_0879fb.rst new file mode 100644 index 0000000000000..5b957ab6b4962 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_src_0879fb.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_src_0879fb: + +src +=== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`exec`, :ref:`scc`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx11_src_17933a.rst b/llvm/docs/AMDGPU/gfx11_src_17933a.rst new file mode 100644 index 0000000000000..794d3d6401e4d --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_src_17933a.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_src_17933a: + +src +=== + +Instruction input. + +*Size:* 16 bits. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`m0`, :ref:`exec`, :ref:`scc`, :ref:`iconst`, :ref:`ival`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx11_src_25d8ac.rst b/llvm/docs/AMDGPU/gfx11_src_25d8ac.rst new file mode 100644 index 0000000000000..1c6ab66473753 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_src_25d8ac.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_src_25d8ac: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`m0`, :ref:`exec`, :ref:`scc`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx11_src_7af462.rst b/llvm/docs/AMDGPU/gfx11_src_7af462.rst new file mode 100644 index 0000000000000..b41a6a626bcbd --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_src_7af462.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_src_7af462: + +src +=== + +Instruction input. + +*Size:* 4 dwords if wavefront size is 64, otherwise 8 dwords. + +*Operands:* :ref:`v`, :ref:`iconst`, :ref:`fconst` diff --git a/llvm/docs/AMDGPU/gfx11_src_852d86.rst b/llvm/docs/AMDGPU/gfx11_src_852d86.rst new file mode 100644 index 0000000000000..26b6949cc2cce --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_src_852d86.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_src_852d86: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`m0`, :ref:`exec`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx11_src_9cb8cf.rst b/llvm/docs/AMDGPU/gfx11_src_9cb8cf.rst new file mode 100644 index 0000000000000..724cedfb95216 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_src_9cb8cf.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_src_9cb8cf: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`m0`, :ref:`exec`, :ref:`scc`, :ref:`iconst`, :ref:`ival`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx11_src_d01e4c.rst b/llvm/docs/AMDGPU/gfx11_src_d01e4c.rst new file mode 100644 index 0000000000000..9996cae9172f8 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_src_d01e4c.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_src_d01e4c: + +src +=== + +Instruction input. + +*Size:* 16 bits. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`m0`, :ref:`exec`, :ref:`scc`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx11_src_d5ffa3.rst b/llvm/docs/AMDGPU/gfx11_src_d5ffa3.rst new file mode 100644 index 0000000000000..1f2e73600bc0f --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_src_d5ffa3.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_src_d5ffa3: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`m0`, :ref:`exec`, :ref:`scc`, :ref:`iconst`, :ref:`ival` diff --git a/llvm/docs/AMDGPU/gfx11_srsrc_5dafbc.rst b/llvm/docs/AMDGPU/gfx11_srsrc_5dafbc.rst new file mode 100644 index 0000000000000..1ee7138dd3d5b --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_srsrc_5dafbc.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_srsrc_5dafbc: + +srsrc +===== + +Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format. + +*Size:* 4 dwords. + +*Operands:* :ref:`s`, :ref:`ttmp` diff --git a/llvm/docs/AMDGPU/gfx11_srsrc_80eef6.rst b/llvm/docs/AMDGPU/gfx11_srsrc_80eef6.rst new file mode 100644 index 0000000000000..f6b09010a55dc --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_srsrc_80eef6.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_srsrc_80eef6: + +srsrc +===== + +Buffer resource constant, which defines the address and characteristics of the buffer in memory. + +*Size:* 4 dwords. + +*Operands:* :ref:`s`, :ref:`ttmp` diff --git a/llvm/docs/AMDGPU/gfx11_srsrc_cf7132.rst b/llvm/docs/AMDGPU/gfx11_srsrc_cf7132.rst new file mode 100644 index 0000000000000..08bae2646d9ac --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_srsrc_cf7132.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_srsrc_cf7132: + +srsrc +===== + +Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format. + +*Size:* 8 dwords by default, 4 dwords if :ref:`r128` is specified. + +*Operands:* :ref:`s`, :ref:`ttmp` diff --git a/llvm/docs/AMDGPU/gfx11_ssamp.rst b/llvm/docs/AMDGPU/gfx11_ssamp.rst new file mode 100644 index 0000000000000..f13c967ba6099 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_ssamp.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_ssamp: + +ssamp +===== + +Sampler constant used to specify filtering options applied to the image data after it is read. + +*Size:* 4 dwords. + +*Operands:* :ref:`s`, :ref:`ttmp` diff --git a/llvm/docs/AMDGPU/gfx11_ssrc_05f584.rst b/llvm/docs/AMDGPU/gfx11_ssrc_05f584.rst new file mode 100644 index 0000000000000..c8dccfee42662 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_ssrc_05f584.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_ssrc_05f584: + +ssrc +==== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`null` diff --git a/llvm/docs/AMDGPU/gfx11_ssrc_121527.rst b/llvm/docs/AMDGPU/gfx11_ssrc_121527.rst new file mode 100644 index 0000000000000..ff0b75f397392 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_ssrc_121527.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_ssrc_121527: + +ssrc +==== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`m0`, :ref:`exec`, :ref:`scc`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx11_ssrc_1a3009.rst b/llvm/docs/AMDGPU/gfx11_ssrc_1a3009.rst new file mode 100644 index 0000000000000..30d7ae458da68 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_ssrc_1a3009.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_ssrc_1a3009: + +ssrc +==== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`exec`, :ref:`scc`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx11_ssrc_361664.rst b/llvm/docs/AMDGPU/gfx11_ssrc_361664.rst new file mode 100644 index 0000000000000..3f319b6bebf3d --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_ssrc_361664.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_ssrc_361664: + +ssrc +==== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`m0`, :ref:`iconst` diff --git a/llvm/docs/AMDGPU/gfx11_ssrc_460c63.rst b/llvm/docs/AMDGPU/gfx11_ssrc_460c63.rst new file mode 100644 index 0000000000000..ac466ee7eb320 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_ssrc_460c63.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_ssrc_460c63: + +ssrc +==== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`m0`, :ref:`exec` diff --git a/llvm/docs/AMDGPU/gfx11_ssrc_6fbc49.rst b/llvm/docs/AMDGPU/gfx11_ssrc_6fbc49.rst new file mode 100644 index 0000000000000..5a2de40e37e35 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_ssrc_6fbc49.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_ssrc_6fbc49: + +ssrc +==== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null` diff --git a/llvm/docs/AMDGPU/gfx11_ssrc_81ba27.rst b/llvm/docs/AMDGPU/gfx11_ssrc_81ba27.rst new file mode 100644 index 0000000000000..d1159ea6368ed --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_ssrc_81ba27.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_ssrc_81ba27: + +ssrc +==== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null` diff --git a/llvm/docs/AMDGPU/gfx11_ssrc_8dd4e0.rst b/llvm/docs/AMDGPU/gfx11_ssrc_8dd4e0.rst new file mode 100644 index 0000000000000..899d4a4d94fa9 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_ssrc_8dd4e0.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_ssrc_8dd4e0: + +ssrc +==== + +Instruction input. + +*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords. + +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null` diff --git a/llvm/docs/AMDGPU/gfx11_tgt.rst b/llvm/docs/AMDGPU/gfx11_tgt.rst new file mode 100644 index 0000000000000..a462172c3ce8f --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_tgt.rst @@ -0,0 +1,31 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_tgt: + +tgt +=== + +An export target: + + ================== =================================== + Syntax Description + ================== =================================== + pos{0..4} Copy vertex position 0..4. + mrt{0..7} Copy pixel color to the MRTs 0..7. + mrtz Copy pixel depth (Z) data. + prim Copy primitive (connectivity) data. + dual_src_blend0 Copy dual source blend left. + dual_src_blend1 Copy dual source blend right. + ================== =================================== + +Examples: + +.. parsed-literal:: + + exp pos3 v1, v2, v3, v4 + exp mrt0 v1, v2, v3, v4 diff --git a/llvm/docs/AMDGPU/gfx11_type_deviation_8d2078.rst b/llvm/docs/AMDGPU/gfx11_type_deviation_8d2078.rst new file mode 100644 index 0000000000000..7aa11608468d9 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_type_deviation_8d2078.rst @@ -0,0 +1,14 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_type_deviation_8d2078: + +Type Deviation +============== + +The *type* of this operand differs from the *type* :ref:`implied by the opcode`. This tag specifies the actual operand *type*. +The number of data components depends on wavesize: 8 in wave32 mode and 4 in wave64 mode. diff --git a/llvm/docs/AMDGPU/gfx11_type_deviation_a14eb1.rst b/llvm/docs/AMDGPU/gfx11_type_deviation_a14eb1.rst new file mode 100644 index 0000000000000..04bd604c233e6 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_type_deviation_a14eb1.rst @@ -0,0 +1,13 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_type_deviation_a14eb1: + +Type Deviation +============== + +The *type* of this operand differs from the *type* :ref:`implied by the opcode`. This tag specifies the actual operand *type*. diff --git a/llvm/docs/AMDGPU/gfx11_vaddr_0212e3.rst b/llvm/docs/AMDGPU/gfx11_vaddr_0212e3.rst new file mode 100644 index 0000000000000..95c8646b18e6d --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vaddr_0212e3.rst @@ -0,0 +1,20 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vaddr_0212e3: + +vaddr +===== + +A 64-bit flat global address or a 32-bit offset depending on addressing mode: + +* Address = :ref:`vaddr` + :ref:`offset13s`. :ref:`vaddr` is a 64-bit address. This mode is indicated by :ref:`saddr` set to :ref:`off`. +* Address = :ref:`saddr` + :ref:`vaddr` + :ref:`offset13s`. :ref:`vaddr` is a 32-bit offset. This mode is used when :ref:`saddr` is not :ref:`off`. + +*Size:* 1 or 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vaddr_0bfea4.rst b/llvm/docs/AMDGPU/gfx11_vaddr_0bfea4.rst new file mode 100644 index 0000000000000..2656690d1ff81 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vaddr_0bfea4.rst @@ -0,0 +1,30 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vaddr_0bfea4: + +vaddr +===== + +Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image. + +This operand may be specified using either :ref:`standard VGPR syntax` or special :ref:`NSA VGPR syntax`. + +*Size:* 8-12 dwords. Actual size depends on opcode and :ref:`a16`. + + This instruction expects NSA address to be partitioned into 5 groups; registers within each group must be contiguous. + + Examples: + + .. parsed-literal:: + + image_bvh_intersect_ray v[4:7], v[9:16], s[4:7] + image_bvh64_intersect_ray v[5:8], v[1:12], s[8:11] + image_bvh_intersect_ray v[39:42], [v50, v46, v[20:22], v[40:42], v[47:49]], s[12:15] + image_bvh64_intersect_ray v[39:42], [v[50:51], v46, v[20:22], v[40:42], v[47:49]], s[12:15] + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vaddr_6ab80d.rst b/llvm/docs/AMDGPU/gfx11_vaddr_6ab80d.rst new file mode 100644 index 0000000000000..cacd621809917 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vaddr_6ab80d.rst @@ -0,0 +1,19 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vaddr_6ab80d: + +vaddr +===== + +An optional 32-bit flat scratch offset. Must be specified as :ref:`off` if not used. + +* Offset = [:ref:`vaddr`] + [:ref:`saddr`] + :ref:`offset13s`. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`off` diff --git a/llvm/docs/AMDGPU/gfx11_vaddr_9f7133.rst b/llvm/docs/AMDGPU/gfx11_vaddr_9f7133.rst new file mode 100644 index 0000000000000..fc79739381ad1 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vaddr_9f7133.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vaddr_9f7133: + +vaddr +===== + +A 64-bit flat address. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vaddr_a5639c.rst b/llvm/docs/AMDGPU/gfx11_vaddr_a5639c.rst new file mode 100644 index 0000000000000..1bf425f7bc4b8 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vaddr_a5639c.rst @@ -0,0 +1,19 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vaddr_a5639c: + +vaddr +===== + +Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image. + +This operand may be specified using either :ref:`standard VGPR syntax` or special :ref:`NSA VGPR syntax`. + +*Size:* 1-12 dwords. Actual size depends on opcode, :ref:`dim` and :ref:`a16`. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vaddr_b73dc0.rst b/llvm/docs/AMDGPU/gfx11_vaddr_b73dc0.rst new file mode 100644 index 0000000000000..597996340aca9 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vaddr_b73dc0.rst @@ -0,0 +1,22 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vaddr_b73dc0: + +vaddr +===== + +This is an optional operand which may specify offset and/or index. + +*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen` and :ref:`idxen`: + +* If only :ref:`idxen` is specified, this operand supplies an index. Size is 1 dword. +* If only :ref:`offen` is specified, this operand supplies an offset. Size is 1 dword. +* If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords. +* If none of these modifiers are specified, this operand must be set to :ref:`off`. + +*Operands:* :ref:`v`, :ref:`off` diff --git a/llvm/docs/AMDGPU/gfx11_vaddr_f20ee4.rst b/llvm/docs/AMDGPU/gfx11_vaddr_f20ee4.rst new file mode 100644 index 0000000000000..33f2f2763d9fb --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vaddr_f20ee4.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vaddr_f20ee4: + +vaddr +===== + +An offset from the start of GDS/LDS memory. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vcc.rst b/llvm/docs/AMDGPU/gfx11_vcc.rst new file mode 100644 index 0000000000000..66790bb82cb67 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vcc.rst @@ -0,0 +1,16 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vcc: + +vcc +=== + +Vector condition code. This operand depends on wavefront size: + +* Should be :ref:`vcc_lo` if wavefront size is 32. +* Should be :ref:`vcc` if wavefront size is 64. diff --git a/llvm/docs/AMDGPU/gfx11_vdata0_6802ce.rst b/llvm/docs/AMDGPU/gfx11_vdata0_6802ce.rst new file mode 100644 index 0000000000000..a3cf76cffc183 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata0_6802ce.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata0_6802ce: + +vdata0 +====== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdata0_fd235e.rst b/llvm/docs/AMDGPU/gfx11_vdata0_fd235e.rst new file mode 100644 index 0000000000000..bbd8a707fd8e3 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata0_fd235e.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata0_fd235e: + +vdata0 +====== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdata1_6802ce.rst b/llvm/docs/AMDGPU/gfx11_vdata1_6802ce.rst new file mode 100644 index 0000000000000..126f318f9d21a --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata1_6802ce.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata1_6802ce: + +vdata1 +====== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdata1_e016a1.rst b/llvm/docs/AMDGPU/gfx11_vdata1_e016a1.rst new file mode 100644 index 0000000000000..91ece42ea29ac --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata1_e016a1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata1_e016a1: + +vdata1 +====== + +Instruction input. + +*Size:* 4 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdata1_fd235e.rst b/llvm/docs/AMDGPU/gfx11_vdata1_fd235e.rst new file mode 100644 index 0000000000000..3bb936a683366 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata1_fd235e.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata1_fd235e: + +vdata1 +====== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdata_21b58d.rst b/llvm/docs/AMDGPU/gfx11_vdata_21b58d.rst new file mode 100644 index 0000000000000..2df0af8333d0e --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata_21b58d.rst @@ -0,0 +1,20 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata_21b58d: + +vdata +===== + +Image data to store by an *image_store* instruction. + +*Size:* depends on :ref:`dmask` and :ref:`d16`: + +* :ref:`dmask` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits, depending on :ref:`d16`. +* :ref:`d16` specifies that data in registers are packed; each value occupies 16 bits. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdata_2d6239.rst b/llvm/docs/AMDGPU/gfx11_vdata_2d6239.rst new file mode 100644 index 0000000000000..bf9f97731e133 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata_2d6239.rst @@ -0,0 +1,21 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata_2d6239: + +vdata +===== + +Input data for an atomic instruction. + +Optionally, this operand may be used to store output data: + +* If :ref:`glc` is specified, gets the memory value before the operation. + +*Size:* 4 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdata_4b260e.rst b/llvm/docs/AMDGPU/gfx11_vdata_4b260e.rst new file mode 100644 index 0000000000000..ffffa71226e50 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata_4b260e.rst @@ -0,0 +1,21 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata_4b260e: + +vdata +===== + +Input data for an atomic instruction. + +Optionally, this operand may be used to store output data: + +* If :ref:`glc` is specified, gets the memory value before the operation. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdata_56f215.rst b/llvm/docs/AMDGPU/gfx11_vdata_56f215.rst new file mode 100644 index 0000000000000..123eedaec20dd --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata_56f215.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata_56f215: + +vdata +===== + +Instruction input. + +*Size:* 3 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdata_6802ce.rst b/llvm/docs/AMDGPU/gfx11_vdata_6802ce.rst new file mode 100644 index 0000000000000..3c61e33f9462b --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata_6802ce.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata_6802ce: + +vdata +===== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdata_84fab6.rst b/llvm/docs/AMDGPU/gfx11_vdata_84fab6.rst new file mode 100644 index 0000000000000..094dddc5844ed --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata_84fab6.rst @@ -0,0 +1,26 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata_84fab6: + +vdata +===== + +Input data for an atomic instruction. + +Optionally, this operand may be used to store output data: + +* If :ref:`glc` is specified, gets the memory value before the operation. + +*Size:* depends on :ref:`dmask`: + +* :ref:`dmask` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword. + + + Note: the surface data format is indicated in the image resource constant, but not in the instruction. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdata_aa5a53.rst b/llvm/docs/AMDGPU/gfx11_vdata_aa5a53.rst new file mode 100644 index 0000000000000..6dd063a9721c8 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata_aa5a53.rst @@ -0,0 +1,26 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata_aa5a53: + +vdata +===== + +Input data for an atomic instruction. + +Optionally, this operand may be used to store output data: + +* If :ref:`glc` is specified, gets the memory value before the operation. + +*Size:* depends on :ref:`dmask`: + +* :ref:`dmask` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword. + + + Note: the surface data format is indicated in the image resource constant, but not in the instruction. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdata_ad559c.rst b/llvm/docs/AMDGPU/gfx11_vdata_ad559c.rst new file mode 100644 index 0000000000000..8ecfbf7a76798 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata_ad559c.rst @@ -0,0 +1,21 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata_ad559c: + +vdata +===== + +Input data for an atomic instruction. + +Optionally, this operand may be used to store output data: + +* If :ref:`glc` is specified, gets the memory value before the operation. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdata_c08393.rst b/llvm/docs/AMDGPU/gfx11_vdata_c08393.rst new file mode 100644 index 0000000000000..3946f576e7cdc --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata_c08393.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata_c08393: + +vdata +===== + +Image data to store by an *image_store* instruction. + +*Size:* depends on :ref:`dmask` which may specify from 1 to 4 data elements. Each data element occupies 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdata_e016a1.rst b/llvm/docs/AMDGPU/gfx11_vdata_e016a1.rst new file mode 100644 index 0000000000000..1f3bf2062a913 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata_e016a1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata_e016a1: + +vdata +===== + +Instruction input. + +*Size:* 4 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdata_fd235e.rst b/llvm/docs/AMDGPU/gfx11_vdata_fd235e.rst new file mode 100644 index 0000000000000..c78b982521101 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdata_fd235e.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdata_fd235e: + +vdata +===== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_227281.rst b/llvm/docs/AMDGPU/gfx11_vdst_227281.rst new file mode 100644 index 0000000000000..9e4bdeae35d9f --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_227281.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_227281: + +vdst +==== + +Instruction output. + +*Size:* 4 dwords if wavefront size is 64, otherwise 8 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_463513.rst b/llvm/docs/AMDGPU/gfx11_vdst_463513.rst new file mode 100644 index 0000000000000..e084980b10fda --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_463513.rst @@ -0,0 +1,19 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_463513: + +vdst +==== + +Data returned by a 64-bit atomic flat instruction. + +This is an optional operand. It must be used if and only if :ref:`glc` is specified. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_48e42f.rst b/llvm/docs/AMDGPU/gfx11_vdst_48e42f.rst new file mode 100644 index 0000000000000..fbbc1ce859ddf --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_48e42f.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_48e42f: + +vdst +==== + +Instruction output. + +*Size:* 3 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_5d50a1.rst b/llvm/docs/AMDGPU/gfx11_vdst_5d50a1.rst new file mode 100644 index 0000000000000..3ff14be0f6fe8 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_5d50a1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_5d50a1: + +vdst +==== + +Instruction output: data read from a memory buffer. + +*Size:* 1 dword by default. :ref:`tfe` adds 1 dword if specified. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_5ec176.rst b/llvm/docs/AMDGPU/gfx11_vdst_5ec176.rst new file mode 100644 index 0000000000000..ae4166bed30fe --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_5ec176.rst @@ -0,0 +1,22 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_5ec176: + +vdst +==== + +Image data to be loaded by an *image_gather4* instruction. + +*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits, depending on :ref:`d16`. + +:ref:`d16` affects operand size as follows: + +* :ref:`d16` specifies that data elements in registers are packed; each value occupies 16 bits. + + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_69a144.rst b/llvm/docs/AMDGPU/gfx11_vdst_69a144.rst new file mode 100644 index 0000000000000..06504908abc69 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_69a144.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_69a144: + +vdst +==== + +Instruction output. + +*Size:* 4 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_709347.rst b/llvm/docs/AMDGPU/gfx11_vdst_709347.rst new file mode 100644 index 0000000000000..f497044731bf8 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_709347.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_709347: + +vdst +==== + +Instruction output: data read from a memory buffer. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_81a6ed.rst b/llvm/docs/AMDGPU/gfx11_vdst_81a6ed.rst new file mode 100644 index 0000000000000..09c4d6060dcac --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_81a6ed.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_81a6ed: + +vdst +==== + +Instruction output: data read from a memory buffer. + +*Size:* 3 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_89680f.rst b/llvm/docs/AMDGPU/gfx11_vdst_89680f.rst new file mode 100644 index 0000000000000..5331d638469aa --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_89680f.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_89680f: + +vdst +==== + +Instruction output. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_9041ac.rst b/llvm/docs/AMDGPU/gfx11_vdst_9041ac.rst new file mode 100644 index 0000000000000..a8e9ef22571bc --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_9041ac.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_9041ac: + +vdst +==== + +Image data to be loaded by an image instruction. + +*Size:* 4 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_a49b76.rst b/llvm/docs/AMDGPU/gfx11_vdst_a49b76.rst new file mode 100644 index 0000000000000..222c3ff1fba58 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_a49b76.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_a49b76: + +vdst +==== + +Instruction output: data read from a memory buffer. + +*Size:* 3 dwords by default. :ref:`tfe` adds 1 dword if specified. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_bdb32f.rst b/llvm/docs/AMDGPU/gfx11_vdst_bdb32f.rst new file mode 100644 index 0000000000000..a4d009df1be73 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_bdb32f.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_bdb32f: + +vdst +==== + +Instruction output. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_d0dc43.rst b/llvm/docs/AMDGPU/gfx11_vdst_d0dc43.rst new file mode 100644 index 0000000000000..a0ed454737c96 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_d0dc43.rst @@ -0,0 +1,19 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_d0dc43: + +vdst +==== + +Data returned by a 32-bit atomic flat instruction. + +This is an optional operand. It must be used if and only if :ref:`glc` is specified. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_d180f4.rst b/llvm/docs/AMDGPU/gfx11_vdst_d180f4.rst new file mode 100644 index 0000000000000..75955e539d3c2 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_d180f4.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_d180f4: + +vdst +==== + +Instruction output. + +*Size:* 16 bits. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_d71f1c.rst b/llvm/docs/AMDGPU/gfx11_vdst_d71f1c.rst new file mode 100644 index 0000000000000..e496bb45723d9 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_d71f1c.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_d71f1c: + +vdst +==== + +Instruction output: data read from a memory buffer. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_d7c57e.rst b/llvm/docs/AMDGPU/gfx11_vdst_d7c57e.rst new file mode 100644 index 0000000000000..54cdde0212bc7 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_d7c57e.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_d7c57e: + +vdst +==== + +Instruction output: data read from a memory buffer. + +*Size:* 2 dwords by default. :ref:`tfe` adds 1 dword if specified. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_dd8a32.rst b/llvm/docs/AMDGPU/gfx11_vdst_dd8a32.rst new file mode 100644 index 0000000000000..1b40e1bd39c14 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_dd8a32.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_dd8a32: + +vdst +==== + +Instruction output: data read from a memory buffer. + +*Size:* 4 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_dfa6da.rst b/llvm/docs/AMDGPU/gfx11_vdst_dfa6da.rst new file mode 100644 index 0000000000000..d6370a484f5b5 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_dfa6da.rst @@ -0,0 +1,20 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_dfa6da: + +vdst +==== + +Image data to be loaded by an image instruction. + +*Size:* depends on :ref:`dmask` and :ref:`tfe`: + +* :ref:`dmask` may specify from 1 to 4 data elements. Each data element occupies 1 dword. +* :ref:`tfe` adds 1 dword if specified. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_e2d005.rst b/llvm/docs/AMDGPU/gfx11_vdst_e2d005.rst new file mode 100644 index 0000000000000..99fc89516c2bb --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_e2d005.rst @@ -0,0 +1,22 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_e2d005: + +vdst +==== + +Image data to be loaded by an image instruction. + +*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits, depending on :ref:`d16`. + +:ref:`d16` and :ref:`tfe` affect operand size as follows: + +* :ref:`d16` specifies that data elements in registers are packed; each value occupies 16 bits. +* :ref:`tfe` adds 1 dword if specified. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_eae4c8.rst b/llvm/docs/AMDGPU/gfx11_vdst_eae4c8.rst new file mode 100644 index 0000000000000..187ad652180b4 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_eae4c8.rst @@ -0,0 +1,21 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_eae4c8: + +vdst +==== + +Image data to be loaded by an image instruction. + +*Size:* depends on :ref:`dmask`, :ref:`tfe` and :ref:`d16`: + +* :ref:`dmask` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits, depending on :ref:`d16`. +* :ref:`d16` specifies that data elements in registers are packed; each value occupies 16 bits. +* :ref:`tfe` adds 1 dword if specified. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vdst_f47754.rst b/llvm/docs/AMDGPU/gfx11_vdst_f47754.rst new file mode 100644 index 0000000000000..f6a670d131fa2 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vdst_f47754.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vdst_f47754: + +vdst +==== + +Instruction output: data read from a memory buffer. + +*Size:* 4 dwords by default. :ref:`tfe` adds 1 dword if specified. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vij.rst b/llvm/docs/AMDGPU/gfx11_vij.rst new file mode 100644 index 0000000000000..849662e320ed5 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vij.rst @@ -0,0 +1,15 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vij: + +vij +=== + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vparam.rst b/llvm/docs/AMDGPU/gfx11_vparam.rst new file mode 100644 index 0000000000000..1ff2db7530c8f --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vparam.rst @@ -0,0 +1,15 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vparam: + +vparam +====== + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vparam0.rst b/llvm/docs/AMDGPU/gfx11_vparam0.rst new file mode 100644 index 0000000000000..0b61e3e1d581a --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vparam0.rst @@ -0,0 +1,15 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vparam0: + +vparam0 +======= + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vsrc_1c4e7f.rst b/llvm/docs/AMDGPU/gfx11_vsrc_1c4e7f.rst new file mode 100644 index 0000000000000..8048b35674c16 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vsrc_1c4e7f.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vsrc_1c4e7f: + +vsrc +==== + +Instruction input. + +*Size:* 16 bits. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vsrc_24f3d2.rst b/llvm/docs/AMDGPU/gfx11_vsrc_24f3d2.rst new file mode 100644 index 0000000000000..3da7b6b8167a1 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vsrc_24f3d2.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vsrc_24f3d2: + +vsrc +==== + +Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off` if not used. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`off` diff --git a/llvm/docs/AMDGPU/gfx11_vsrc_6802ce.rst b/llvm/docs/AMDGPU/gfx11_vsrc_6802ce.rst new file mode 100644 index 0000000000000..c8b6237365ef7 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vsrc_6802ce.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vsrc_6802ce: + +vsrc +==== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vsrc_731030.rst b/llvm/docs/AMDGPU/gfx11_vsrc_731030.rst new file mode 100644 index 0000000000000..ae8021b9acc5f --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vsrc_731030.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vsrc_731030: + +vsrc +==== + +Instruction input. + +*Size:* 8 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vsrc_e016a1.rst b/llvm/docs/AMDGPU/gfx11_vsrc_e016a1.rst new file mode 100644 index 0000000000000..aa19c1026275b --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vsrc_e016a1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vsrc_e016a1: + +vsrc +==== + +Instruction input. + +*Size:* 4 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_vsrc_fd235e.rst b/llvm/docs/AMDGPU/gfx11_vsrc_fd235e.rst new file mode 100644 index 0000000000000..206a6045e9a14 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_vsrc_fd235e.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_vsrc_fd235e: + +vsrc +==== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx11_waitcnt.rst b/llvm/docs/AMDGPU/gfx11_waitcnt.rst new file mode 100644 index 0000000000000..709b98aa7046f --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_waitcnt.rst @@ -0,0 +1,56 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_waitcnt: + +waitcnt +======= + +Counts of outstanding instructions to wait for. + +The bits of this operand have the following meaning: + + ===== ================================================ ============ + Bits Description Value Range + ===== ================================================ ============ + 2:0 EXP_CNT: export and LDSDIR count. 0..7 + 3:3 Unused \- + 9:4 LGKM_CNT: LDS, GDS, Constant and Message count. 0..63 + 15:10 VM_CNT: vector memory operations count. 0..63 + ===== ================================================ ============ + +This operand may be specified as one of the following: + +* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from 0 to 0xFFFF. +* A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below. + + ====================== ====================================================================== + Syntax Description + ====================== ====================================================================== + vmcnt(<*N*>) A VM_CNT value. *N* must not exceed the largest VM_CNT value. + expcnt(<*N*>) An EXP_CNT value. *N* must not exceed the largest EXP_CNT value. + lgkmcnt(<*N*>) An LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value. + vmcnt_sat(<*N*>) A VM_CNT value computed as min(*N*, the largest VM_CNT value). + expcnt_sat(<*N*>) An EXP_CNT value computed as min(*N*, the largest EXP_CNT value). + lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value). + ====================== ====================================================================== + +These values may be specified in any order. Spaces, ampersands, and commas may be used as optional separators. +If some values are omitted, the corresponding fields will default to their maximum value. + +*N* is either an +:ref:`integer number` or an +:ref:`absolute expression`. + +Examples: + +.. parsed-literal:: + + s_waitcnt vmcnt(1) + s_waitcnt expcnt(2) lgkmcnt(3) + s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3) + s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2) diff --git a/llvm/docs/AMDGPU/gfx11_waitcnt_depctr.rst b/llvm/docs/AMDGPU/gfx11_waitcnt_depctr.rst new file mode 100644 index 0000000000000..6d1af96487ed6 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx11_waitcnt_depctr.rst @@ -0,0 +1,40 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx11_waitcnt_depctr: + +waitcnt_depctr +============== + +Dependency counters to wait for. + +This operand may be specified as one of the following: + +* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from -32768 to 65535. +* A combination of *symbolic values* described below. + + ======================== ======================== ================ ================= + Syntax Description Valid *N* Values Default *N* Value + ======================== ======================== ================ ================= + depctr_hold_cnt(<*N*>) Wait for HOLD_CNT <= N 0..1 1 + depctr_sa_sdst(<*N*>) Wait for SA_SDST <= N 0..1 1 + depctr_va_vdst(<*N*>) Wait for VA_VDST <= N 0..15 15 + depctr_va_sdst(<*N*>) Wait for VA_SDST <= N 0..7 7 + depctr_va_ssrc(<*N*>) Wait for VA_SSRC <= N 0..1 1 + depctr_va_vcc(<*N*>) Wait for VA_VCC <= N 0..1 1 + depctr_vm_vsrc(<*N*>) Wait for VM_VSRC <= N 0..7 7 + ======================== ======================== ================ ================= + + These values may be specified in any order. Spaces, ampersands, and commas may be used as optional separators. + +Examples: + +.. parsed-literal:: + + s_waitcnt_depctr depctr_sa_sdst(0) depctr_va_vdst(0) + s_waitcnt_depctr depctr_sa_sdst(1) & depctr_va_vdst(1) + s_waitcnt_depctr depctr_va_vdst(3), depctr_va_sdst(5) diff --git a/llvm/docs/AMDGPUInstructionSyntax.rst b/llvm/docs/AMDGPUInstructionSyntax.rst index 1f5483ed6fc15..38669a3c8d3e8 100644 --- a/llvm/docs/AMDGPUInstructionSyntax.rst +++ b/llvm/docs/AMDGPUInstructionSyntax.rst @@ -13,6 +13,9 @@ Instructions Syntax ~~~~~~ +Syntax of Regular Instructions +------------------------------ + An instruction has the following syntax: | ``<``\ *opcode mnemonic*\ ``> <``\ *operand0*\ ``>, @@ -24,6 +27,21 @@ An instruction has the following syntax: The order of *operands* and *modifiers* is fixed. Most *modifiers* are optional and may be omitted. +Syntax of VOPD Instructions +--------------------------- + +*VOPDX* and *VOPDY* instructions must be concatenated with the :: operator to form a single *VOPD* instruction: + + ``<``\ *VOPDX instruction*\ ``> :: <``\ *VOPDY instruction*\ ``>`` + +An example: + +.. parsed-literal:: + + v_dual_add_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 1.0 + +Note that *VOPDX* and *VOPDY* instructions cannot be used as separate opcodes. + .. _amdgpu_syn_instruction_mnemo: Opcode Mnemonic @@ -102,6 +120,10 @@ The size of typeless data is specified by size suffices: d16_xy b16x2 2 for GFX8.0, 1 for GFX8.1 and GFX9+ d16_xyz b16x3 3 for GFX8.0, 2 for GFX8.1 and GFX9+ d16_xyzw b16x4 4 for GFX8.0, 2 for GFX8.1 and GFX9+ + d16_format_x b16 1 + d16_format_xy b16x2 1 + d16_format_xyz b16x3 2 + d16_format_xyzw b16x4 2 ================= =================== ===================================== .. WARNING:: @@ -158,6 +180,7 @@ To force specific encoding, one can add a suffix to the opcode of the instructio *VOP3* (64-bit) encoding _e64 *DPP* encoding _dpp *SDWA* encoding _sdwa + *VOP3 DPP* encoding _e64_dpp =================================================== ================= This reference uses encoding suffices to specify which encoding is implied. diff --git a/llvm/docs/AMDGPUModifierSyntax.rst b/llvm/docs/AMDGPUModifierSyntax.rst index dd9cbaa532652..bde59f9b441c2 100644 --- a/llvm/docs/AMDGPUModifierSyntax.rst +++ b/llvm/docs/AMDGPUModifierSyntax.rst @@ -230,6 +230,19 @@ Specifies if the :ref:`exec` mask is valid for this *export* :ref:`exec` mask. ======================================== ================================================ +.. _amdgpu_synid_row_en: + +row_en +~~~~~~ + +Specifies whether to export one row or multiple rows of data. + + ======================================== ================================================ + Syntax Description + ======================================== ================================================ + row_en Export multiple rows using row index from M0. + ======================================== ================================================ + FLAT Modifiers -------------- @@ -402,6 +415,7 @@ This modifier has some limitations depending on the instruction kind: 64-bit atomic *cmpswap* 0xF 64-bit atomic instructions except for *cmpswap* 0x3 *gather4* 0x1, 0x2, 0x4, 0x8 + GFX11+ *msaa_load* 0x1, 0x2, 0x4, 0x8 Other instructions any value =================================================== ======================== @@ -897,9 +911,9 @@ provided that the combination of formats can be mapped to a unified format. Supported unified formats and equivalent combinations of data and numeric formats are defined below: - ============================== ============================== ============================= - Unified Format Syntax Equivalent Data Format Equivalent Numeric Format - ============================== ============================== ============================= + ============================== ============================== ============================= ============ + Unified Format Syntax Equivalent Data Format Equivalent Numeric Format Note + ============================== ============================== ============================= ============ BUF_FMT_INVALID BUF_DATA_FORMAT_INVALID BUF_NUM_FORMAT_UNORM BUF_FMT_8_UNORM BUF_DATA_FORMAT_8 BUF_NUM_FORMAT_UNORM @@ -936,26 +950,26 @@ are defined below: BUF_FMT_16_16_SINT BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_SINT BUF_FMT_16_16_FLOAT BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_FLOAT - BUF_FMT_10_11_11_UNORM BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_UNORM - BUF_FMT_10_11_11_SNORM BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_SNORM - BUF_FMT_10_11_11_USCALED BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_USCALED - BUF_FMT_10_11_11_SSCALED BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_SSCALED - BUF_FMT_10_11_11_UINT BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_UINT - BUF_FMT_10_11_11_SINT BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_SINT + BUF_FMT_10_11_11_UNORM BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_UNORM GFX10 only + BUF_FMT_10_11_11_SNORM BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_SNORM GFX10 only + BUF_FMT_10_11_11_USCALED BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_USCALED GFX10 only + BUF_FMT_10_11_11_SSCALED BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_SSCALED GFX10 only + BUF_FMT_10_11_11_UINT BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_UINT GFX10 only + BUF_FMT_10_11_11_SINT BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_SINT GFX10 only BUF_FMT_10_11_11_FLOAT BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_FLOAT - BUF_FMT_11_11_10_UNORM BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_UNORM - BUF_FMT_11_11_10_SNORM BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_SNORM - BUF_FMT_11_11_10_USCALED BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_USCALED - BUF_FMT_11_11_10_SSCALED BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_SSCALED - BUF_FMT_11_11_10_UINT BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_UINT - BUF_FMT_11_11_10_SINT BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_SINT + BUF_FMT_11_11_10_UNORM BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_UNORM GFX10 only + BUF_FMT_11_11_10_SNORM BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_SNORM GFX10 only + BUF_FMT_11_11_10_USCALED BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_USCALED GFX10 only + BUF_FMT_11_11_10_SSCALED BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_SSCALED GFX10 only + BUF_FMT_11_11_10_UINT BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_UINT GFX10 only + BUF_FMT_11_11_10_SINT BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_SINT GFX10 only BUF_FMT_11_11_10_FLOAT BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_FLOAT BUF_FMT_10_10_10_2_UNORM BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_UNORM BUF_FMT_10_10_10_2_SNORM BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_SNORM - BUF_FMT_10_10_10_2_USCALED BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_USCALED - BUF_FMT_10_10_10_2_SSCALED BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_SSCALED + BUF_FMT_10_10_10_2_USCALED BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_USCALED GFX10 only + BUF_FMT_10_10_10_2_SSCALED BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_SSCALED GFX10 only BUF_FMT_10_10_10_2_UINT BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_UINT BUF_FMT_10_10_10_2_SINT BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_SINT @@ -991,7 +1005,7 @@ are defined below: BUF_FMT_32_32_32_32_UINT BUF_DATA_FORMAT_32_32_32_32 BUF_NUM_FORMAT_UINT BUF_FMT_32_32_32_32_SINT BUF_DATA_FORMAT_32_32_32_32 BUF_NUM_FORMAT_SINT BUF_FMT_32_32_32_32_FLOAT BUF_DATA_FORMAT_32_32_32_32 BUF_NUM_FORMAT_FLOAT - ============================== ============================== ============================= + ============================== ============================== ============================= ============ Examples: @@ -1064,8 +1078,8 @@ Examples: offset:0xfffff offset:-x -VINTRP Modifiers ----------------- +VINTRP/VINTERP/LDSDIR Modifiers +------------------------------- .. _amdgpu_synid_high: @@ -1080,6 +1094,47 @@ Specifies which half of the LDS word to use. Low half of LDS word is used by def high Use the high half of LDS word. ======================================== ================================ +neg +~~~ + +See a description :ref:`here`. + +.. _amdgpu_synid_wait_exp: + +wait_exp +~~~~~~~~ + +Specifies a wait on the EXP counter before issuing the current instruction. +The counter must be less than or equal to this value before the instruction is issued. +If set to 7, no wait is performed. + +The default value is zero. This is a safe value, but it may be suboptimal. + + ================ ====================================================== + Syntax Description + ================ ====================================================== + wait_exp:{0..7} An additional wait on the EXP counter before + issuing this instruction. + ================ ====================================================== + +.. _amdgpu_synid_wait_vdst: + +wait_vdst +~~~~~~~~~ + +Specifies a wait on the VA_VDST counter before issuing the current instruction. +The counter must be less than or equal to this value before the instruction is issued. +If set to 15, no wait is performed. + +The default value is zero. This is a safe value, but it may be suboptimal. + + ================== ====================================================== + Syntax Description + ================== ====================================================== + wait_vdst:{0..15} An additional wait on the VA_VDST counter before + issuing this instruction. + ================== ====================================================== + DPP8 Modifiers -------------- diff --git a/llvm/docs/AMDGPUOperandSyntax.rst b/llvm/docs/AMDGPUOperandSyntax.rst index 7aa957870f97e..ff6ec6cf71ff2 100644 --- a/llvm/docs/AMDGPUOperandSyntax.rst +++ b/llvm/docs/AMDGPUOperandSyntax.rst @@ -24,8 +24,8 @@ Operands .. _amdgpu_synid_v: -v -- +v (32-bit) +---------- Vector registers. There are 256 32-bit vector registers. @@ -83,6 +83,8 @@ Examples: .. _amdgpu_synid_nsa: +**Non-Sequential Address (NSA) Syntax** + GFX10+ *image* instructions may use special *NSA* (Non-Sequential Address) syntax for *image addresses*: @@ -97,6 +99,10 @@ syntax for *image addresses*: in *NSA* sequence are not required to have consecutive indices. Moreover, the same register may appear in the sequence more than once. + + GFX11+ has an additional limitation: if address + size occupies more than 5 dwords, registers + starting from the 5th element must be contiguous. ===================================== ================================================= Examples: @@ -107,6 +113,35 @@ Examples: [v[32],v[1:1],[v2]] [v4,v4,v4,v4] +.. _amdgpu_synid_v16: + +v (16-bit) +---------- + +16-bit vector registers. Each :ref:`32-bit vector register` is divided into two 16-bit low and high registers, so there are 512 16-bit vector registers. + +Only VOP3, VOP3P and VINTERP instructions may access all 512 registers (using :ref:`op_sel` modifier). +VOP1, VOP2 and VOPC instructions may currently access only 128 low 16-bit registers using the syntax described below. + +.. WARNING:: This section is incomplete. The support of 16-bit registers in the assembler is still WIP. + +\ + =================================================== ==================================================================== + Syntax Description + =================================================== ==================================================================== + **v**\ A single 16-bit *vector* register (low half). + =================================================== ==================================================================== + +Note: *N* must satisfy the following conditions: + +* 0 <= *N* <= 127. + +Examples: + +.. parsed-literal:: + + v127 + .. _amdgpu_synid_a: a diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index 3030b14aaefcd..9ae09b1c424de 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -21,6 +21,7 @@ User Guide for AMDGPU Backend AMDGPU/AMDGPUAsmGFX1011 AMDGPU/AMDGPUAsmGFX1013 AMDGPU/AMDGPUAsmGFX1030 + AMDGPU/AMDGPUAsmGFX11 AMDGPUModifierSyntax AMDGPUOperandSyntax AMDGPUInstructionSyntax @@ -445,7 +446,7 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following Add product names. - **GCN GFX11** + **GCN GFX11 (RDNA 3)** [AMD-GCN-GFX11-RDNA3]_ ----------------------------------------------------------------------------------------------------------------------- ``gfx1100`` ``amdgcn`` dGPU - cumode - Architected - *pal-amdpal* *TBA* - wavefrontsize64 flat @@ -14346,14 +14347,22 @@ in this description. :doc:`gfx1035` :doc:`gfx1036` + + RDNA 3 :doc:`GFX11` :doc:`gfx1100` + + :doc:`gfx1101` + + :doc:`gfx1102` + + :doc:`gfx1103` ============= ============================================= ======================================= For more information about instructions, their semantics and supported combinations of operands, refer to one of instruction set architecture manuals [AMD-GCN-GFX6]_, [AMD-GCN-GFX7]_, [AMD-GCN-GFX8]_, [AMD-GCN-GFX900-GFX904-VEGA]_, [AMD-GCN-GFX906-VEGA7NM]_, -[AMD-GCN-GFX908-CDNA1]_, [AMD-GCN-GFX90A-CDNA2]_, [AMD-GCN-GFX10-RDNA1]_ and -[AMD-GCN-GFX10-RDNA2]_. +[AMD-GCN-GFX908-CDNA1]_, [AMD-GCN-GFX90A-CDNA2]_, [AMD-GCN-GFX10-RDNA1]_, +[AMD-GCN-GFX10-RDNA2]_ and [AMD-GCN-GFX11-RDNA3]_. Operands ~~~~~~~~ @@ -15128,6 +15137,7 @@ Additional Documentation .. [AMD-GCN-GFX90A-CDNA2] `AMD Instinct MI200 Instruction Set Architecture `__ .. [AMD-GCN-GFX10-RDNA1] `AMD RDNA 1.0 Instruction Set Architecture `__ .. [AMD-GCN-GFX10-RDNA2] `AMD RDNA 2 Instruction Set Architecture `__ +.. [AMD-GCN-GFX11-RDNA3] `AMD RDNA 3 Instruction Set Architecture `__ .. [AMD-RADEON-HD-2000-3000] `AMD R6xx shader ISA `__ .. [AMD-RADEON-HD-4000] `AMD R7xx shader ISA `__ .. [AMD-RADEON-HD-5000] `AMD Evergreen shader ISA `__