diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4eda3d3f4b10b..c9c03be511905 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -42,6 +42,19 @@ using namespace llvm;
 
 STATISTIC(NumTailCalls, "Number of tail calls");
 
+static unsigned getLMULForFixedLengthVector(MVT VT,
+                                            const RISCVSubtarget &Subtarget) {
+  unsigned MinVLen = Subtarget.getMinRVVVectorSizeInBits();
+
+  // Masks only occupy a single register. An LMUL==1 operation can only use
+  // at most 1/8 of the register. Only an LMUL==8 operaton on i8 types can
+  // use the whole register.
+  if (VT.getVectorElementType() == MVT::i1)
+    MinVLen /= 8;
+
+  return divideCeil(VT.getSizeInBits(), MinVLen);
+}
+
 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
                                          const RISCVSubtarget &STI)
     : TargetLowering(TM), Subtarget(STI) {
@@ -143,7 +156,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
     if (Subtarget.useRVVForFixedLengthVectors()) {
       auto addRegClassForFixedVectors = [this](MVT VT) {
-        unsigned LMul = Subtarget.getLMULForFixedLengthVector(VT);
+        unsigned LMul = getLMULForFixedLengthVector(VT, Subtarget);
         const TargetRegisterClass *RC;
         if (LMul == 1 || VT.getVectorElementType() == MVT::i1)
           RC = &RISCV::VRRegClass;
@@ -1111,7 +1124,7 @@ static MVT getContainerForFixedLengthVector(const TargetLowering &TLI, MVT VT,
   assert(VT.isFixedLengthVector() && TLI.isTypeLegal(VT) &&
          "Expected legal fixed length vector!");
 
-  unsigned LMul = Subtarget.getLMULForFixedLengthVector(VT);
+  unsigned LMul = getLMULForFixedLengthVector(VT, Subtarget);
   assert(LMul <= 8 && isPowerOf2_32(LMul) && "Unexpected LMUL!");
 
   MVT EltVT = VT.getVectorElementType();
@@ -8027,7 +8040,7 @@ bool RISCVTargetLowering::useRVVForFixedLengthVectorVT(MVT VT) const {
     break;
   }
 
-  unsigned LMul = Subtarget.getLMULForFixedLengthVector(VT);
+  unsigned LMul = getLMULForFixedLengthVector(VT, Subtarget);
   // Don't use RVV for types that don't fit.
   if (LMul > Subtarget.getMaxLMULForFixedLengthVectors())
     return false;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index f6463c0251143..c8764b5b4ffca 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -146,15 +146,3 @@ unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
 bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
   return hasStdExtV() && getMinRVVVectorSizeInBits() != 0;
 }
-
-unsigned RISCVSubtarget::getLMULForFixedLengthVector(MVT VT) const {
-  unsigned MinVLen = getMinRVVVectorSizeInBits();
-
-  // Masks only occupy a single register. An LMUL==1 operation can only use
-  // at most 1/8 of the register. Only an LMUL==8 operaton on i8 types can
-  // use the whole register.
-  if (VT.getVectorElementType() == MVT::i1)
-    MinVLen /= 8;
-
-  return divideCeil(VT.getSizeInBits(), MinVLen);
-}
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index aae8b810bf3c3..148f09f532b38 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -153,7 +153,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   // implied by the architecture.
   unsigned getMaxRVVVectorSizeInBits() const;
   unsigned getMinRVVVectorSizeInBits() const;
-  unsigned getLMULForFixedLengthVector(MVT VT) const;
   unsigned getMaxLMULForFixedLengthVectors() const;
   bool useRVVForFixedLengthVectors() const;
 };