diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index 155a7c107f28a..bc3b88c61e8a6 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -953,6 +953,75 @@ def PNR32_p8to15  : PNRP8to15RegOp<"s", PNRAsmOp32_p8to15, 32, PPR_p8to15>;
 def PNR64_p8to15  : PNRP8to15RegOp<"d", PNRAsmOp64_p8to15, 64, PPR_p8to15>;
 
 
+let Namespace = "AArch64" in {
+  def psub0 : SubRegIndex<16, -1>;
+  def psub1 : SubRegIndex<16, -1>;
+}
+
+// Pairs of SVE predicate vector registers.
+def PSeqPairs : RegisterTuples<[psub0, psub1], [(rotl PPR, 0), (rotl PPR, 1)]>;
+
+def PPR2 : RegisterClass<"AArch64", [untyped], 16, (add PSeqPairs)> {
+  let Size = 32;
+}
+
+class PPRVectorList<int ElementWidth, int NumRegs> : AsmOperandClass {
+  let Name = "SVEPredicateList" # NumRegs # "x" # ElementWidth;
+  let ParserMethod = "tryParseVectorList<RegKind::SVEPredicateVector>";
+  let PredicateMethod = "isTypedVectorList<RegKind::SVEPredicateVector, "
+                            # NumRegs #", 0, "#ElementWidth #">";
+  let RenderMethod = "addVectorListOperands<AArch64Operand::VecListIdx_PReg, "
+                         # NumRegs #">";
+}
+
+def PP_b : RegisterOperand<PPR2, "printTypedVectorList<0,'b'>"> {
+  let ParserMatchClass = PPRVectorList<8, 2>;
+}
+
+def PP_h : RegisterOperand<PPR2, "printTypedVectorList<0,'h'>"> {
+  let ParserMatchClass = PPRVectorList<16, 2>;
+}
+
+def PP_s : RegisterOperand<PPR2, "printTypedVectorList<0,'s'>"> {
+  let ParserMatchClass = PPRVectorList<32, 2>;
+}
+
+def PP_d : RegisterOperand<PPR2, "printTypedVectorList<0,'d'>"> {
+  let ParserMatchClass = PPRVectorList<64, 2>;
+}
+
+// SVE2 multiple-of-2 multi-predicate-vector operands
+def PPR2Mul2 : RegisterClass<"AArch64", [untyped], 16, (add (decimate PSeqPairs, 2))> {
+  let Size = 32;
+}
+
+class PPRVectorListMul<int ElementWidth, int NumRegs> : PPRVectorList<ElementWidth, NumRegs> {
+  let Name = "SVEPredicateListMul" # NumRegs # "x" # ElementWidth;
+  let DiagnosticType = "Invalid" # Name;
+  let PredicateMethod =
+      "isTypedVectorListMultiple<RegKind::SVEPredicateVector, " # NumRegs # ", 0, "
+                                                                # ElementWidth # ">";
+}
+
+let EncoderMethod = "EncodeRegAsMultipleOf<2>",
+    DecoderMethod = "DecodePPR2Mul2RegisterClass" in {
+  def PP_b_mul_r : RegisterOperand<PPR2Mul2, "printTypedVectorList<0,'b'>"> {
+    let ParserMatchClass = PPRVectorListMul<8, 2>;
+  }
+
+  def PP_h_mul_r : RegisterOperand<PPR2Mul2, "printTypedVectorList<0,'h'>"> {
+    let ParserMatchClass = PPRVectorListMul<16, 2>;
+  }
+
+  def PP_s_mul_r : RegisterOperand<PPR2Mul2, "printTypedVectorList<0,'s'>"> {
+    let ParserMatchClass = PPRVectorListMul<32, 2>;
+  }
+
+  def PP_d_mul_r : RegisterOperand<PPR2Mul2, "printTypedVectorList<0,'d'>"> {
+    let ParserMatchClass = PPRVectorListMul<64, 2>;
+  }
+}  // end let EncoderMethod/DecoderMethod
+
 
 //******************************************************************************
 
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index bef0f715e46ac..4099884040c1a 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -3591,6 +3591,7 @@ def UDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"udot", 0b1>;
 
 defm CNTP_XCI : sve2p1_pcount_pn<"cntp", 0b000>;
 defm PEXT_PCI : sve2p1_pred_as_ctr_to_mask<"pext">;
+defm PEXT_2PCI : sve2p1_pred_as_ctr_to_mask_pair<"pext">;
 defm PTRUE_C  : sve2p1_ptrue_pn<"ptrue">;
 
 defm SQCVTN_Z2Z_StoH  : sve2p1_multi_vec_extract_narrow<"sqcvtn", 0b00>;
@@ -3672,6 +3673,14 @@ defm STNT1H_4Z_IMM : sve2p1_mem_cst_si_4z<"stnt1h", 0b01, 0b1, ZZZZ_h_mul_r>;
 defm STNT1W_4Z_IMM : sve2p1_mem_cst_si_4z<"stnt1w", 0b10, 0b1, ZZZZ_s_mul_r>;
 defm STNT1D_4Z_IMM : sve2p1_mem_cst_si_4z<"stnt1d", 0b11, 0b1, ZZZZ_d_mul_r>;
 
+defm WHILEGE_2PXX : sve2p1_int_while_rr_pair<"whilege", 0b000>;
+defm WHILEGT_2PXX : sve2p1_int_while_rr_pair<"whilegt", 0b001>;
+defm WHILELT_2PXX : sve2p1_int_while_rr_pair<"whilelt", 0b010>;
+defm WHILELE_2PXX : sve2p1_int_while_rr_pair<"whilele", 0b011>;
+defm WHILEHS_2PXX : sve2p1_int_while_rr_pair<"whilehs", 0b100>;
+defm WHILEHI_2PXX : sve2p1_int_while_rr_pair<"whilehi", 0b101>;
+defm WHILELO_2PXX : sve2p1_int_while_rr_pair<"whilelo", 0b110>;
+defm WHILELS_2PXX : sve2p1_int_while_rr_pair<"whilels", 0b111>;
 defm WHILEGE_CXX  : sve2p1_int_while_rr_pn<"whilege", 0b000>;
 defm WHILEGT_CXX  : sve2p1_int_while_rr_pn<"whilegt", 0b001>;
 defm WHILELT_CXX  : sve2p1_int_while_rr_pn<"whilelt", 0b010>;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index c51c9c1c927cd..49d54f8e9a849 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -225,6 +225,7 @@ class AArch64AsmParser : public MCTargetAsmParser {
 
   bool validateInstruction(MCInst &Inst, SMLoc &IDLoc,
                            SmallVectorImpl<SMLoc> &Loc);
+  unsigned getNumRegsForRegKind(RegKind K);
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
                                uint64_t &ErrorInfo,
@@ -1726,6 +1727,7 @@ class AArch64Operand : public MCParsedAsmOperand {
     VecListIdx_DReg = 0,
     VecListIdx_QReg = 1,
     VecListIdx_ZReg = 2,
+    VecListIdx_PReg = 3,
   };
 
   template <VecListIndexType RegTy, unsigned NumRegs>
@@ -1740,12 +1742,17 @@ class AArch64Operand : public MCParsedAsmOperand {
                    AArch64::Q0_Q1_Q2, AArch64::Q0_Q1_Q2_Q3 },
       /* ZReg */ { AArch64::Z0,
                    AArch64::Z0,       AArch64::Z0_Z1,
-                   AArch64::Z0_Z1_Z2, AArch64::Z0_Z1_Z2_Z3 }
+                   AArch64::Z0_Z1_Z2, AArch64::Z0_Z1_Z2_Z3 },
+      /* PReg */ { AArch64::P0,
+                   AArch64::P0,       AArch64::P0_P1 }
     };
 
     assert((RegTy != VecListIdx_ZReg || NumRegs <= 4) &&
            " NumRegs must be <= 4 for ZRegs");
 
+    assert((RegTy != VecListIdx_PReg || NumRegs <= 2) &&
+           " NumRegs must be <= 2 for PRegs");
+
     unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs];
     Inst.addOperand(MCOperand::createReg(FirstReg + getVectorListStart() -
                                          FirstRegs[(unsigned)RegTy][0]));
@@ -2807,6 +2814,20 @@ unsigned AArch64AsmParser::matchRegisterNameAlias(StringRef Name,
   return RegNum;
 }
 
+unsigned AArch64AsmParser::getNumRegsForRegKind(RegKind K) {
+  switch (K) {
+  case RegKind::Scalar:
+  case RegKind::NeonVector:
+  case RegKind::SVEDataVector:
+    return 32;
+  case RegKind::Matrix:
+  case RegKind::SVEPredicateVector:
+  case RegKind::SVEPredicateAsCounter:
+    return 16;
+  }
+  llvm_unreachable("Unsupported RegKind");
+}
+
 /// tryParseScalarRegister - Try to parse a register name. The token must be an
 /// Identifier when called, and if it is a register name the token is eaten and
 /// the register is added to the operand list.
@@ -4169,6 +4190,7 @@ AArch64AsmParser::tryParseVectorList(OperandVector &Operands,
     return MatchOperand_NoMatch;
   };
 
+  int NumRegs = getNumRegsForRegKind(VectorKind);
   SMLoc S = getLoc();
   auto LCurly = getTok();
   Lex(); // Eat left bracket token.
@@ -4203,7 +4225,8 @@ AArch64AsmParser::tryParseVectorList(OperandVector &Operands,
       return MatchOperand_ParseFail;
     }
 
-    unsigned Space = (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + 32 - PrevReg);
+    unsigned Space =
+        (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + NumRegs - PrevReg);
 
     if (Space == 0 || Space > 3) {
       Error(Loc, "invalid number of vectors");
@@ -4229,7 +4252,8 @@ AArch64AsmParser::tryParseVectorList(OperandVector &Operands,
 
       // Registers must be incremental (with wraparound at 31)
       if (getContext().getRegisterInfo()->getEncodingValue(Reg) !=
-          (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % 32) {
+          (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) %
+              NumRegs) {
         Error(Loc, "registers must be sequential");
         return MatchOperand_ParseFail;
       }
@@ -5678,6 +5702,13 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
                       "pn0..pn15 with element suffix.");
   case Match_InvalidSVEVecLenSpecifier:
     return Error(Loc, "Invalid vector length specifier, expected VLx2 or VLx4");
+  case Match_InvalidSVEPredicateListMul2x8:
+  case Match_InvalidSVEPredicateListMul2x16:
+  case Match_InvalidSVEPredicateListMul2x32:
+  case Match_InvalidSVEPredicateListMul2x64:
+    return Error(Loc, "Invalid vector list, expected list with 2 consecutive "
+                      "predicate registers, where the first vector is a multiple of 2 "
+                      "and with correct element type");
   case Match_InvalidSVEExactFPImmOperandHalfOne:
     return Error(Loc, "Invalid floating point constant, expected 0.5 or 1.0.");
   case Match_InvalidSVEExactFPImmOperandHalfTwo:
@@ -6262,6 +6293,10 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidSVEPNPredicateHReg:
   case Match_InvalidSVEPNPredicateSReg:
   case Match_InvalidSVEPNPredicateDReg:
+  case Match_InvalidSVEPredicateListMul2x8:
+  case Match_InvalidSVEPredicateListMul2x16:
+  case Match_InvalidSVEPredicateListMul2x32:
+  case Match_InvalidSVEPredicateListMul2x64:
   case Match_InvalidSVEExactFPImmOperandHalfOne:
   case Match_InvalidSVEExactFPImmOperandHalfTwo:
   case Match_InvalidSVEExactFPImmOperandZeroOne:
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index b5f205f7705fc..1438f026f6792 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -140,6 +140,12 @@ static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
 static DecodeStatus
 DecodePPR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
                               const MCDisassembler *Decoder);
+static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder);
+static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
+                                                uint64_t Address,
+                                                const void *Decoder);
 
 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
                                                uint64_t Address,
@@ -707,6 +713,29 @@ DecodePPR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
   return DecodePPRRegisterClass(Inst, RegNo + 8, Addr, Decoder);
 }
 
+static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder) {
+  if (RegNo > 15)
+    return Fail;
+
+  unsigned Register =
+      AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo);
+  Inst.addOperand(MCOperand::createReg(Register));
+  return Success;
+}
+
+static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
+                                                uint64_t Address,
+                                                const void *Decoder) {
+  if ((RegNo * 2) > 14)
+    return Fail;
+  unsigned Register =
+      AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
+  Inst.addOperand(MCOperand::createReg(Register));
+  return Success;
+}
+
 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
                                           uint64_t Addr,
                                           const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index f38ded6fb792a..9324ee41c3123 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -1415,6 +1415,23 @@ static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
     case AArch64::Z31:
       Reg = AArch64::Z0;
       break;
+    case AArch64::P0:  Reg = AArch64::P1;  break;
+    case AArch64::P1:  Reg = AArch64::P2;  break;
+    case AArch64::P2:  Reg = AArch64::P3;  break;
+    case AArch64::P3:  Reg = AArch64::P4;  break;
+    case AArch64::P4:  Reg = AArch64::P5;  break;
+    case AArch64::P5:  Reg = AArch64::P6;  break;
+    case AArch64::P6:  Reg = AArch64::P7;  break;
+    case AArch64::P7:  Reg = AArch64::P8;  break;
+    case AArch64::P8:  Reg = AArch64::P9;  break;
+    case AArch64::P9:  Reg = AArch64::P10; break;
+    case AArch64::P10: Reg = AArch64::P11; break;
+    case AArch64::P11: Reg = AArch64::P12; break;
+    case AArch64::P12: Reg = AArch64::P13; break;
+    case AArch64::P13: Reg = AArch64::P14; break;
+    case AArch64::P14: Reg = AArch64::P15; break;
+    // Vector lists can wrap around.
+    case AArch64::P15: Reg = AArch64::P0; break;
     }
   }
   return Reg;
@@ -1477,7 +1494,8 @@ void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
   unsigned NumRegs = 1;
   if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
       MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
-      MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))
+      MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) ||
+      MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg))
     NumRegs = 2;
   else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
            MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
@@ -1495,6 +1513,8 @@ void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
     Reg = FirstReg;
   else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
     Reg = FirstReg;
+  else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::psub0))
+    Reg = FirstReg;
 
   // If it's a D-reg, we need to promote it to the equivalent Q-reg before
   // printing (otherwise getRegisterName fails).
@@ -1504,7 +1524,9 @@ void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
     Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
   }
 
-  if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) && NumRegs > 1 &&
+  if ((MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
+       MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) &&
+      NumRegs > 1 &&
       // Do not print the range when the last register is lower than the first.
       // Because it is a wrap-around register.
       Reg < getNextVectorRegister(Reg, NumRegs - 1)) {
@@ -1520,7 +1542,8 @@ void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
   } else {
     for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
       // wrap-around sve register
-      if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
+      if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
+          MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg))
         printRegName(O, Reg);
       else
         printRegName(O, Reg, AArch64::vreg);
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index fa98fa57d0e49..63098194e45c5 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -8732,22 +8732,29 @@ multiclass sve2p1_ptrue_pn<string mnemonic> {
 }
 
 
-class sve2p1_pred_as_ctr_to_mask<string mnemonic, bits<2> sz, PPRRegOp pprty>
-    : I<(outs pprty:$Pd), (ins PNRAny_p8to15:$PNn, VectorIndexS:$imm2),
-        mnemonic, "\t$Pd, $PNn$imm2",
+// SVE extract mask predicate from predicate-as-counter
+class sve2p1_pred_as_ctr_to_mask_base<string mnemonic, bits<2> sz, bits<3> opc,
+                                      RegisterOperand pprty, Operand idxty>
+    : I<(outs pprty:$Pd), (ins PNRAny_p8to15:$PNn, idxty:$index),
+        mnemonic, "\t$Pd, $PNn$index",
         "", []>, Sched<[]> {
   bits<4> Pd;
   bits<3> PNn;
   bits<2> imm2;
   let Inst{31-24} = 0b00100101;
   let Inst{23-22} = sz;
-  let Inst{21-10} = 0b100000011100;
-  let Inst{9-8}   = imm2;
+  let Inst{21-11} = 0b10000001110;
+  let Inst{10-8}  = opc;
   let Inst{7-5}   = PNn;
   let Inst{4}     = 0b1;
   let Inst{3-0}   = Pd;
 }
 
+class sve2p1_pred_as_ctr_to_mask<string mnemonic, bits<2> sz, PPRRegOp pprty>
+    : sve2p1_pred_as_ctr_to_mask_base<mnemonic, sz, {0, ?, ?}, pprty, VectorIndexS> {
+  bits<2> index;
+  let Inst{9-8} = index;
+}
 
 multiclass sve2p1_pred_as_ctr_to_mask<string mnemonic> {
  def _B : sve2p1_pred_as_ctr_to_mask<mnemonic, 0b00, PPR8>;
@@ -8757,6 +8764,20 @@ multiclass sve2p1_pred_as_ctr_to_mask<string mnemonic> {
 }
 
 
+class sve2p1_pred_as_ctr_to_mask_pair<string mnemonic, bits<2> sz, RegisterOperand pprty>
+    : sve2p1_pred_as_ctr_to_mask_base<mnemonic, sz, {1, 0, ?}, pprty, VectorIndexD> {
+  bit index;
+  let Inst{8}    = index;
+}
+
+multiclass sve2p1_pred_as_ctr_to_mask_pair<string mnemonic> {
+ def _B : sve2p1_pred_as_ctr_to_mask_pair<mnemonic, 0b00, PP_b>;
+ def _H : sve2p1_pred_as_ctr_to_mask_pair<mnemonic, 0b01, PP_h>;
+ def _S : sve2p1_pred_as_ctr_to_mask_pair<mnemonic, 0b10, PP_s>;
+ def _D : sve2p1_pred_as_ctr_to_mask_pair<mnemonic, 0b11, PP_d>;
+}
+
+
 // SME2 multi-vec extract narrow
 class sve2p1_multi_vec_extract_narrow<string mnemonic, bits<2> opc, bits<3> tsz>
     : I<(outs ZPR16:$Zd), (ins ZZ_s_mul_r:$Zn),
@@ -9060,6 +9081,7 @@ multiclass sve2p1_pcount_pn<string mnemonic, bits<3> opc> {
 }
 
 
+// SVE integer compare scalar count and limit (predicate-as-counter)
 class sve2p1_int_while_rr_pn<string mnemonic, bits<2> sz, bits<3> opc,
                              PNRP8to15RegOp pnrty>
     : I<(outs pnrty:$PNd), (ins GPR64:$Rn, GPR64:$Rm, sve_vec_len_specifier_enum:$vl),
@@ -9092,3 +9114,35 @@ multiclass sve2p1_int_while_rr_pn<string mnemonic, bits<3> opc> {
  def _S : sve2p1_int_while_rr_pn<mnemonic, 0b10, opc, PNR32_p8to15>;
  def _D : sve2p1_int_while_rr_pn<mnemonic, 0b11, opc, PNR64_p8to15>;
 }
+
+
+// SVE integer compare scalar count and limit (predicate pair)
+class sve2p1_int_while_rr_pair<string mnemonic, bits<2> sz, bits<3> opc,
+                             RegisterOperand ppr_ty>
+    : I<(outs ppr_ty:$Pd), (ins GPR64:$Rn, GPR64:$Rm),
+        mnemonic, "\t$Pd, $Rn, $Rm",
+        "", []>, Sched<[]> {
+  bits<3> Pd;
+  bits<5> Rn;
+  bits<5> Rm;
+  let Inst{31-24} = 0b00100101;
+  let Inst{23-22} = sz;
+  let Inst{21}    = 0b1;
+  let Inst{20-16} = Rm;
+  let Inst{15-12} = 0b0101;
+  let Inst{11-10} = opc{2-1};
+  let Inst{9-5}   = Rn;
+  let Inst{4}     = 0b1;
+  let Inst{3-1}   = Pd;
+  let Inst{0}     = opc{0};
+
+  let Defs = [NZCV];
+}
+
+
+multiclass sve2p1_int_while_rr_pair<string mnemonic, bits<3> opc> {
+ def _B : sve2p1_int_while_rr_pair<mnemonic, 0b00, opc, PP_b_mul_r>;
+ def _H : sve2p1_int_while_rr_pair<mnemonic, 0b01, opc, PP_h_mul_r>;
+ def _S : sve2p1_int_while_rr_pair<mnemonic, 0b10, opc, PP_s_mul_r>;
+ def _D : sve2p1_int_while_rr_pair<mnemonic, 0b11, opc, PP_d_mul_r>;
+}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
index 9c27dfca7df76..fa3466047ae13 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
@@ -26,7 +26,7 @@ define void @asm_simple_register_clobber() {
 define i64 @asm_register_early_clobber() {
   ; CHECK-LABEL: name: asm_register_early_clobber
   ; CHECK: bb.1 (%ir-block.0):
-  ; CHECK-NEXT:   INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, 1769483 /* regdef-ec:GPR64common */, def early-clobber %0, 1769483 /* regdef-ec:GPR64common */, def early-clobber %1, !0
+  ; CHECK-NEXT:   INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, 2555915 /* regdef-ec:GPR64common */, def early-clobber %0, 2555915 /* regdef-ec:GPR64common */, def early-clobber %1, !0
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY %0
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY %1
   ; CHECK-NEXT:   [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]]
@@ -54,7 +54,7 @@ entry:
 define i32 @test_single_register_output() nounwind ssp {
   ; CHECK-LABEL: name: test_single_register_output
   ; CHECK: bb.1.entry:
-  ; CHECK-NEXT:   INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 720906 /* regdef:GPR32common */, def %0
+  ; CHECK-NEXT:   INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %0
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY %0
   ; CHECK-NEXT:   $w0 = COPY [[COPY]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
@@ -66,7 +66,7 @@ entry:
 define i64 @test_single_register_output_s64() nounwind ssp {
   ; CHECK-LABEL: name: test_single_register_output_s64
   ; CHECK: bb.1.entry:
-  ; CHECK-NEXT:   INLINEASM &"mov $0, 7", 0 /* attdialect */, 1769482 /* regdef:GPR64common */, def %0
+  ; CHECK-NEXT:   INLINEASM &"mov $0, 7", 0 /* attdialect */, 2555914 /* regdef:GPR64common */, def %0
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY %0
   ; CHECK-NEXT:   $x0 = COPY [[COPY]](s64)
   ; CHECK-NEXT:   RET_ReallyLR implicit $x0
@@ -79,7 +79,7 @@ entry:
 define float @test_multiple_register_outputs_same() #0 {
   ; CHECK-LABEL: name: test_multiple_register_outputs_same
   ; CHECK: bb.1 (%ir-block.0):
-  ; CHECK-NEXT:   INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 720906 /* regdef:GPR32common */, def %0, 720906 /* regdef:GPR32common */, def %1
+  ; CHECK-NEXT:   INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %0, 1507338 /* regdef:GPR32common */, def %1
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY %0
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY %1
   ; CHECK-NEXT:   [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
@@ -96,7 +96,7 @@ define float @test_multiple_register_outputs_same() #0 {
 define double @test_multiple_register_outputs_mixed() #0 {
   ; CHECK-LABEL: name: test_multiple_register_outputs_mixed
   ; CHECK: bb.1 (%ir-block.0):
-  ; CHECK-NEXT:   INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 720906 /* regdef:GPR32common */, def %0, 1572874 /* regdef:FPR64 */, def %1
+  ; CHECK-NEXT:   INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %0, 2359306 /* regdef:FPR64 */, def %1
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY %0
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY %1
   ; CHECK-NEXT:   $d0 = COPY [[COPY1]](s64)
@@ -126,7 +126,7 @@ define zeroext i8 @test_register_output_trunc(i8* %src) nounwind {
   ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
-  ; CHECK-NEXT:   INLINEASM &"mov ${0:w}, 32", 0 /* attdialect */, 720906 /* regdef:GPR32common */, def %1
+  ; CHECK-NEXT:   INLINEASM &"mov ${0:w}, 32", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %1
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY %1
   ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
   ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
@@ -156,7 +156,7 @@ define void @test_input_register_imm() {
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64common = COPY [[C]](s64)
-  ; CHECK-NEXT:   INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, 1769481 /* reguse:GPR64common */, [[COPY]]
+  ; CHECK-NEXT:   INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, 2555913 /* reguse:GPR64common */, [[COPY]]
   ; CHECK-NEXT:   RET_ReallyLR
   call void asm sideeffect "mov x0, $0", "r"(i64 42)
   ret void
@@ -191,7 +191,7 @@ define zeroext i8 @test_input_register(i8* %src) nounwind {
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]](p0)
-  ; CHECK-NEXT:   INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, 720906 /* regdef:GPR32common */, def %1, 1769481 /* reguse:GPR64common */, [[COPY1]]
+  ; CHECK-NEXT:   INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %1, 2555913 /* reguse:GPR64common */, [[COPY1]]
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY %1
   ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
   ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
@@ -208,7 +208,7 @@ define i32 @test_memory_constraint(i32* %a) nounwind {
   ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
-  ; CHECK-NEXT:   INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, 720906 /* regdef:GPR32common */, def %1, 262158 /* mem:m */, [[COPY]](p0)
+  ; CHECK-NEXT:   INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, 1507338 /* regdef:GPR32common */, def %1, 262158 /* mem:m */, [[COPY]](p0)
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY %1
   ; CHECK-NEXT:   $w0 = COPY [[COPY1]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
@@ -222,7 +222,7 @@ define i16 @test_anyext_input() {
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
   ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
-  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 720906 /* regdef:GPR32common */, def %0, 720905 /* reguse:GPR32common */, [[COPY]]
+  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 1507338 /* regdef:GPR32common */, def %0, 1507337 /* reguse:GPR32common */, [[COPY]]
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY %0
   ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
   ; CHECK-NEXT:   [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
@@ -238,7 +238,7 @@ define i16 @test_anyext_input_with_matching_constraint() {
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
   ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
-  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 720906 /* regdef:GPR32common */, def %0, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3)
+  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 1507338 /* regdef:GPR32common */, def %0, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3)
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY %0
   ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
   ; CHECK-NEXT:   [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
index 39970e116960e..8cb6309a10af4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
@@ -69,7 +69,7 @@ define void @test2() #0 personality i32 (...)* @__gcc_personality_v0 {
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64common = COPY [[DEF]](p0)
-  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 1769481 /* reguse:GPR64common */, [[COPY]]
+  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 2555913 /* reguse:GPR64common */, [[COPY]]
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2.a:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
index 95a3c46a752c3..28b56945c7775 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
@@ -57,7 +57,7 @@ tracksRegLiveness: true
 body:             |
   bb.1:
     ; CHECK-LABEL: name: inlineasm_virt_reg_output
-    ; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1310730 /* regdef:WSeqPairsClass_with_sube32_in_GPR32arg */, def %0
+    ; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1310730 /* regdef:FPR32 */, def %0
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
     ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -75,7 +75,7 @@ tracksRegLiveness: true
 body:             |
   bb.1:
     ; CHECK-LABEL: name: inlineasm_virt_mixed_types
-    ; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1310730 /* regdef:WSeqPairsClass_with_sube32_in_GPR32arg */, def %0, 2162698 /* regdef:GPR64arg */, def %1
+    ; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1310730 /* regdef:FPR32 */, def %0, 2162698 /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %1
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY %1
     ; CHECK-NEXT: $d0 = COPY [[COPY1]](s64)
diff --git a/llvm/test/MC/AArch64/SVE2p1/pext-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/pext-diagnostics.s
index 97a3e6cc9f7b9..7ae1ce3fa65ba 100644
--- a/llvm/test/MC/AArch64/SVE2p1/pext-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE2p1/pext-diagnostics.s
@@ -1,5 +1,33 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
 
+// --------------------------------------------------------------------------//
+// Invalid vector lists
+
+pext {p0.h, p2.h}, pn8[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: pext {p0.h, p2.h}, pn8[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pext {p15.h, p1.h}, pn8[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: pext {p15.h, p1.h}, pn8[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pext {p0.h, p1.b}, pn8[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: pext {p0.h, p1.b}, pn8[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pext {p0.h, p1.h, p2.h, p3.h}, pn8[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: pext {p0.h, p1.h, p2.h, p3.h}, pn8[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pext {p0.h}, pn8[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: pext {p0.h}, pn8[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 // --------------------------------------------------------------------------//
 // Invalid predicate as counter register
 
@@ -11,6 +39,16 @@ pext    p0.h, pn3[0]
 // --------------------------------------------------------------------------//
 // Invalid lane index
 
+pext {p0.h, p1.h}, pn8[2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: pext {p0.h, p1.h}, pn8[2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pext {p0.h, p1.h}, pn8[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: pext {p0.h, p1.h}, pn8[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 pext    p0.d, pn8[4]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
 // CHECK-NEXT: pext    p0.d, pn8[4]
diff --git a/llvm/test/MC/AArch64/SVE2p1/pext.s b/llvm/test/MC/AArch64/SVE2p1/pext.s
index 5e9ac6d1b2ae6..cefade005a6ca 100644
--- a/llvm/test/MC/AArch64/SVE2p1/pext.s
+++ b/llvm/test/MC/AArch64/SVE2p1/pext.s
@@ -108,3 +108,87 @@ pext    p15.b, pn15[3]  // 00100101-00100000-01110011-11111111
 // CHECK-ENCODING: [0xff,0x73,0x20,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 252073ff <unknown>
+
+pext    {p0.h, p1.h}, pn8[0]  // 00100101-01100000-01110100-00010000
+// CHECK-INST: pext    { p0.h, p1.h }, pn8[0]
+// CHECK-ENCODING: [0x10,0x74,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25607410 <unknown>
+
+pext    {p5.h, p6.h}, pn10[1]  // 00100101-01100000-01110101-01010101
+// CHECK-INST: pext    { p5.h, p6.h }, pn10[1]
+// CHECK-ENCODING: [0x55,0x75,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25607555 <unknown>
+
+pext    {p7.h, p8.h}, pn13[1]  // 00100101-01100000-01110101-10110111
+// CHECK-INST: pext    { p7.h, p8.h }, pn13[1]
+// CHECK-ENCODING: [0xb7,0x75,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256075b7 <unknown>
+
+pext    {p15.h, p0.h}, pn15[1]  // 00100101-01100000-01110101-11111111
+// CHECK-INST: pext    { p15.h, p0.h }, pn15[1]
+// CHECK-ENCODING: [0xff,0x75,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256075ff <unknown>
+
+pext    {p0.s, p1.s}, pn8[0]  // 00100101-10100000-01110100-00010000
+// CHECK-INST: pext    { p0.s, p1.s }, pn8[0]
+// CHECK-ENCODING: [0x10,0x74,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a07410 <unknown>
+
+pext    {p5.s, p6.s}, pn10[1]  // 00100101-10100000-01110101-01010101
+// CHECK-INST: pext    { p5.s, p6.s }, pn10[1]
+// CHECK-ENCODING: [0x55,0x75,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a07555 <unknown>
+
+pext    {p7.s, p8.s}, pn13[1]  // 00100101-10100000-01110101-10110111
+// CHECK-INST: pext    { p7.s, p8.s }, pn13[1]
+// CHECK-ENCODING: [0xb7,0x75,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a075b7 <unknown>
+
+pext    {p15.s, p0.s}, pn15[1]  // 00100101-10100000-01110101-11111111
+// CHECK-INST: pext    { p15.s, p0.s }, pn15[1]
+// CHECK-ENCODING: [0xff,0x75,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a075ff <unknown>
+
+pext    {p0.d, p1.d}, pn8[0]  // 00100101-11100000-01110100-00010000
+// CHECK-INST: pext    { p0.d, p1.d }, pn8[0]
+// CHECK-ENCODING: [0x10,0x74,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e07410 <unknown>
+
+pext    {p5.d, p6.d}, pn10[1]  // 00100101-11100000-01110101-01010101
+// CHECK-INST: pext    { p5.d, p6.d }, pn10[1]
+// CHECK-ENCODING: [0x55,0x75,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e07555 <unknown>
+
+pext    {p7.d, p8.d}, pn13[1]  // 00100101-11100000-01110101-10110111
+// CHECK-INST: pext    { p7.d, p8.d }, pn13[1]
+// CHECK-ENCODING: [0xb7,0x75,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e075b7 <unknown>
+
+pext    {p15.d, p0.d}, pn15[1]  // 00100101-11100000-01110101-11111111
+// CHECK-INST: pext    { p15.d, p0.d }, pn15[1]
+// CHECK-ENCODING: [0xff,0x75,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e075ff <unknown>
+
+pext    {p7.b, p8.b}, pn13[1]  // 00100101-00100000-01110101-10110111
+// CHECK-INST: pext    { p7.b, p8.b }, pn13[1]
+// CHECK-ENCODING: [0xb7,0x75,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252075b7 <unknown>
+
+pext    {p15.b, p0.b}, pn15[1]  // 00100101-00100000-01110101-11111111
+// CHECK-INST: pext    { p15.b, p0.b }, pn15[1]
+// CHECK-ENCODING: [0xff,0x75,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252075ff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilege-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilege-diagnostics.s
index 908fe56cdc8dc..44584b31e2df8 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilege-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilege-diagnostics.s
@@ -28,3 +28,13 @@ whilege pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilege pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilege { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilege { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilege { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilege { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilege.s b/llvm/test/MC/AArch64/SVE2p1/whilege.s
index 8ebe63660fdd7..f1acef11f69c6 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilege.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilege.s
@@ -37,6 +37,30 @@ whilege pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01100011-11110111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f63f7 <unknown>
 
+whilege {p0.h, p1.h}, x0, x0  // 00100101-01100000-01010000-00010000
+// CHECK-INST: whilege { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x10,0x50,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605010 <unknown>
+
+whilege {p4.h, p5.h}, x10, x21  // 00100101-01110101-01010001-01010100
+// CHECK-INST: whilege { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x54,0x51,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755154 <unknown>
+
+whilege {p6.h, p7.h}, x13, x8  // 00100101-01101000-01010001-10110110
+// CHECK-INST: whilege { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb6,0x51,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256851b6 <unknown>
+
+whilege {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01010011-11111110
+// CHECK-INST: whilege { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x53,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f53fe <unknown>
+
 whilege pn8.s, x0, x0, vlx2  // 00100101-10100000-01000000-00010000
 // CHECK-INST: whilege pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x40,0xa0,0x25]
@@ -61,6 +85,31 @@ whilege pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01100011-11110111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf63f7 <unknown>
 
+whilege {p0.s, p1.s}, x0, x0  // 00100101-10100000-01010000-00010000
+// CHECK-INST: whilege { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x10,0x50,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05010 <unknown>
+
+whilege {p4.s, p5.s}, x10, x21  // 00100101-10110101-01010001-01010100
+// CHECK-INST: whilege { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x54,0x51,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55154 <unknown>
+
+whilege {p6.s, p7.s}, x13, x8  // 00100101-10101000-01010001-10110110
+// CHECK-INST: whilege { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb6,0x51,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a851b6 <unknown>
+
+whilege {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01010011-11111110
+// CHECK-INST: whilege { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x53,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf53fe <unknown>
+
+
 whilege pn8.d, x0, x0, vlx2  // 00100101-11100000-01000000-00010000
 // CHECK-INST: whilege pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x40,0xe0,0x25]
@@ -85,6 +134,31 @@ whilege pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01100011-11110111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff63f7 <unknown>
 
+whilege {p0.d, p1.d}, x0, x0  // 00100101-11100000-01010000-00010000
+// CHECK-INST: whilege { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x10,0x50,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05010 <unknown>
+
+whilege {p4.d, p5.d}, x10, x21  // 00100101-11110101-01010001-01010100
+// CHECK-INST: whilege { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x54,0x51,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55154 <unknown>
+
+whilege {p6.d, p7.d}, x13, x8  // 00100101-11101000-01010001-10110110
+// CHECK-INST: whilege { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb6,0x51,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e851b6 <unknown>
+
+whilege {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01010011-11111110
+// CHECK-INST: whilege { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x53,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff53fe <unknown>
+
+
 whilege pn8.b, x0, x0, vlx2  // 00100101-00100000-01000000-00010000
 // CHECK-INST: whilege pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x40,0x20,0x25]
@@ -108,3 +182,27 @@ whilege pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01100011-11110111
 // CHECK-ENCODING: [0xf7,0x63,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f63f7 <unknown>
+
+whilege {p0.b, p1.b}, x0, x0  // 00100101-00100000-01010000-00010000
+// CHECK-INST: whilege { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x10,0x50,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205010 <unknown>
+
+whilege {p4.b, p5.b}, x10, x21  // 00100101-00110101-01010001-01010100
+// CHECK-INST: whilege { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x54,0x51,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355154 <unknown>
+
+whilege {p6.b, p7.b}, x13, x8  // 00100101-00101000-01010001-10110110
+// CHECK-INST: whilege { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb6,0x51,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252851b6 <unknown>
+
+whilege {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01010011-11111110
+// CHECK-INST: whilege { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x53,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f53fe <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilegt-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilegt-diagnostics.s
index 5735ac79b903d..cc70efb62a40a 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilegt-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilegt-diagnostics.s
@@ -28,3 +28,13 @@ whilegt pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilegt pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilegt { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilegt { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilegt { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilegt { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilegt.s b/llvm/test/MC/AArch64/SVE2p1/whilegt.s
index c3f4d5ec8cd1d..69e3bc93c0c7a 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilegt.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilegt.s
@@ -37,6 +37,30 @@ whilegt pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01100011-11111111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f63ff <unknown>
 
+whilegt {p0.h, p1.h}, x0, x0  // 00100101-01100000-01010000-00010001
+// CHECK-INST: whilegt { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x11,0x50,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605011 <unknown>
+
+whilegt {p4.h, p5.h}, x10, x21  // 00100101-01110101-01010001-01010101
+// CHECK-INST: whilegt { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x55,0x51,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755155 <unknown>
+
+whilegt {p6.h, p7.h}, x13, x8  // 00100101-01101000-01010001-10110111
+// CHECK-INST: whilegt { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb7,0x51,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256851b7 <unknown>
+
+whilegt {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01010011-11111111
+// CHECK-INST: whilegt { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x53,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f53ff <unknown>
+
 whilegt pn8.s, x0, x0, vlx2  // 00100101-10100000-01000000-00011000
 // CHECK-INST: whilegt pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x40,0xa0,0x25]
@@ -61,6 +85,30 @@ whilegt pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01100011-11111111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf63ff <unknown>
 
+whilegt {p0.s, p1.s}, x0, x0  // 00100101-10100000-01010000-00010001
+// CHECK-INST: whilegt { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x11,0x50,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05011 <unknown>
+
+whilegt {p4.s, p5.s}, x10, x21  // 00100101-10110101-01010001-01010101
+// CHECK-INST: whilegt { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x55,0x51,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55155 <unknown>
+
+whilegt {p6.s, p7.s}, x13, x8  // 00100101-10101000-01010001-10110111
+// CHECK-INST: whilegt { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb7,0x51,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a851b7 <unknown>
+
+whilegt {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01010011-11111111
+// CHECK-INST: whilegt { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x53,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf53ff <unknown>
+
 whilegt pn8.d, x0, x0, vlx2  // 00100101-11100000-01000000-00011000
 // CHECK-INST: whilegt pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x40,0xe0,0x25]
@@ -85,6 +133,30 @@ whilegt pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01100011-11111111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff63ff <unknown>
 
+whilegt {p0.d, p1.d}, x0, x0  // 00100101-11100000-01010000-00010001
+// CHECK-INST: whilegt { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x11,0x50,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05011 <unknown>
+
+whilegt {p4.d, p5.d}, x10, x21  // 00100101-11110101-01010001-01010101
+// CHECK-INST: whilegt { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x55,0x51,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55155 <unknown>
+
+whilegt {p6.d, p7.d}, x13, x8  // 00100101-11101000-01010001-10110111
+// CHECK-INST: whilegt { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb7,0x51,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e851b7 <unknown>
+
+whilegt {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01010011-11111111
+// CHECK-INST: whilegt { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x53,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff53ff <unknown>
+
 whilegt pn8.b, x0, x0, vlx2  // 00100101-00100000-01000000-00011000
 // CHECK-INST: whilegt pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x40,0x20,0x25]
@@ -108,3 +180,27 @@ whilegt pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01100011-11111111
 // CHECK-ENCODING: [0xff,0x63,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f63ff <unknown>
+
+whilegt {p0.b, p1.b}, x0, x0  // 00100101-00100000-01010000-00010001
+// CHECK-INST: whilegt { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x11,0x50,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205011 <unknown>
+
+whilegt {p4.b, p5.b}, x10, x21  // 00100101-00110101-01010001-01010101
+// CHECK-INST: whilegt { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x55,0x51,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355155 <unknown>
+
+whilegt {p6.b, p7.b}, x13, x8  // 00100101-00101000-01010001-10110111
+// CHECK-INST: whilegt { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb7,0x51,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252851b7 <unknown>
+
+whilegt {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01010011-11111111
+// CHECK-INST: whilegt { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x53,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f53ff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilehi-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilehi-diagnostics.s
index 382646e48cc42..6ddf086b88665 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilehi-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilehi-diagnostics.s
@@ -28,3 +28,13 @@ whilehi pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilehi pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilehi { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilehi { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilehi { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilehi { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilehi.s b/llvm/test/MC/AArch64/SVE2p1/whilehi.s
index b3e6426996f36..ddb7a6829c920 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilehi.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilehi.s
@@ -37,6 +37,30 @@ whilehi pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01101011-11111111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f6bff <unknown>
 
+whilehi {p0.h, p1.h}, x0, x0  // 00100101-01100000-01011000-00010001
+// CHECK-INST: whilehi { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x11,0x58,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605811 <unknown>
+
+whilehi {p4.h, p5.h}, x10, x21  // 00100101-01110101-01011001-01010101
+// CHECK-INST: whilehi { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x55,0x59,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755955 <unknown>
+
+whilehi {p6.h, p7.h}, x13, x8  // 00100101-01101000-01011001-10110111
+// CHECK-INST: whilehi { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb7,0x59,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256859b7 <unknown>
+
+whilehi {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01011011-11111111
+// CHECK-INST: whilehi { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5b,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f5bff <unknown>
+
 whilehi pn8.s, x0, x0, vlx2  // 00100101-10100000-01001000-00011000
 // CHECK-INST: whilehi pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x48,0xa0,0x25]
@@ -61,6 +85,30 @@ whilehi pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01101011-11111111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf6bff <unknown>
 
+whilehi {p0.s, p1.s}, x0, x0  // 00100101-10100000-01011000-00010001
+// CHECK-INST: whilehi { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x11,0x58,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05811 <unknown>
+
+whilehi {p4.s, p5.s}, x10, x21  // 00100101-10110101-01011001-01010101
+// CHECK-INST: whilehi { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x55,0x59,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55955 <unknown>
+
+whilehi {p6.s, p7.s}, x13, x8  // 00100101-10101000-01011001-10110111
+// CHECK-INST: whilehi { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb7,0x59,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a859b7 <unknown>
+
+whilehi {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01011011-11111111
+// CHECK-INST: whilehi { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5b,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf5bff <unknown>
+
 whilehi pn8.d, x0, x0, vlx2  // 00100101-11100000-01001000-00011000
 // CHECK-INST: whilehi pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x48,0xe0,0x25]
@@ -85,6 +133,30 @@ whilehi pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01101011-11111111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff6bff <unknown>
 
+whilehi {p0.d, p1.d}, x0, x0  // 00100101-11100000-01011000-00010001
+// CHECK-INST: whilehi { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x11,0x58,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05811 <unknown>
+
+whilehi {p4.d, p5.d}, x10, x21  // 00100101-11110101-01011001-01010101
+// CHECK-INST: whilehi { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x55,0x59,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55955 <unknown>
+
+whilehi {p6.d, p7.d}, x13, x8  // 00100101-11101000-01011001-10110111
+// CHECK-INST: whilehi { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb7,0x59,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e859b7 <unknown>
+
+whilehi {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01011011-11111111
+// CHECK-INST: whilehi { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5b,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff5bff <unknown>
+
 whilehi pn8.b, x0, x0, vlx2  // 00100101-00100000-01001000-00011000
 // CHECK-INST: whilehi pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x48,0x20,0x25]
@@ -108,3 +180,27 @@ whilehi pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01101011-11111111
 // CHECK-ENCODING: [0xff,0x6b,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f6bff <unknown>
+
+whilehi {p0.b, p1.b}, x0, x0  // 00100101-00100000-01011000-00010001
+// CHECK-INST: whilehi { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x11,0x58,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205811 <unknown>
+
+whilehi {p4.b, p5.b}, x10, x21  // 00100101-00110101-01011001-01010101
+// CHECK-INST: whilehi { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x55,0x59,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355955 <unknown>
+
+whilehi {p6.b, p7.b}, x13, x8  // 00100101-00101000-01011001-10110111
+// CHECK-INST: whilehi { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb7,0x59,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252859b7 <unknown>
+
+whilehi {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01011011-11111111
+// CHECK-INST: whilehi { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5b,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f5bff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilehs-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilehs-diagnostics.s
index d799f940ec9f9..3f0e7a83a7c3b 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilehs-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilehs-diagnostics.s
@@ -28,3 +28,13 @@ whilehs pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilehs pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilehs { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilehs { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilehs { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilehs { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilehs.s b/llvm/test/MC/AArch64/SVE2p1/whilehs.s
index 68c58191f2185..0a4c50da6d4c1 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilehs.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilehs.s
@@ -37,6 +37,30 @@ whilehs pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01101011-11110111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f6bf7 <unknown>
 
+whilehs {p0.h, p1.h}, x0, x0  // 00100101-01100000-01011000-00010000
+// CHECK-INST: whilehs { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x10,0x58,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605810 <unknown>
+
+whilehs {p4.h, p5.h}, x10, x21  // 00100101-01110101-01011001-01010100
+// CHECK-INST: whilehs { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x54,0x59,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755954 <unknown>
+
+whilehs {p6.h, p7.h}, x13, x8  // 00100101-01101000-01011001-10110110
+// CHECK-INST: whilehs { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb6,0x59,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256859b6 <unknown>
+
+whilehs {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01011011-11111110
+// CHECK-INST: whilehs { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5b,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f5bfe <unknown>
+
 whilehs pn8.s, x0, x0, vlx2  // 00100101-10100000-01001000-00010000
 // CHECK-INST: whilehs pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x48,0xa0,0x25]
@@ -61,6 +85,30 @@ whilehs pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01101011-11110111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf6bf7 <unknown>
 
+whilehs {p0.s, p1.s}, x0, x0  // 00100101-10100000-01011000-00010000
+// CHECK-INST: whilehs { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x10,0x58,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05810 <unknown>
+
+whilehs {p4.s, p5.s}, x10, x21  // 00100101-10110101-01011001-01010100
+// CHECK-INST: whilehs { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x54,0x59,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55954 <unknown>
+
+whilehs {p6.s, p7.s}, x13, x8  // 00100101-10101000-01011001-10110110
+// CHECK-INST: whilehs { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb6,0x59,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a859b6 <unknown>
+
+whilehs {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01011011-11111110
+// CHECK-INST: whilehs { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5b,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf5bfe <unknown>
+
 whilehs pn8.d, x0, x0, vlx2  // 00100101-11100000-01001000-00010000
 // CHECK-INST: whilehs pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x48,0xe0,0x25]
@@ -85,6 +133,30 @@ whilehs pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01101011-11110111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff6bf7 <unknown>
 
+whilehs {p0.d, p1.d}, x0, x0  // 00100101-11100000-01011000-00010000
+// CHECK-INST: whilehs { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x10,0x58,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05810 <unknown>
+
+whilehs {p4.d, p5.d}, x10, x21  // 00100101-11110101-01011001-01010100
+// CHECK-INST: whilehs { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x54,0x59,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55954 <unknown>
+
+whilehs {p6.d, p7.d}, x13, x8  // 00100101-11101000-01011001-10110110
+// CHECK-INST: whilehs { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb6,0x59,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e859b6 <unknown>
+
+whilehs {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01011011-11111110
+// CHECK-INST: whilehs { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5b,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff5bfe <unknown>
+
 whilehs pn8.b, x0, x0, vlx2  // 00100101-00100000-01001000-00010000
 // CHECK-INST: whilehs pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x48,0x20,0x25]
@@ -108,3 +180,27 @@ whilehs pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01101011-11110111
 // CHECK-ENCODING: [0xf7,0x6b,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f6bf7 <unknown>
+
+whilehs {p0.b, p1.b}, x0, x0  // 00100101-00100000-01011000-00010000
+// CHECK-INST: whilehs { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x10,0x58,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205810 <unknown>
+
+whilehs {p4.b, p5.b}, x10, x21  // 00100101-00110101-01011001-01010100
+// CHECK-INST: whilehs { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x54,0x59,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355954 <unknown>
+
+whilehs {p6.b, p7.b}, x13, x8  // 00100101-00101000-01011001-10110110
+// CHECK-INST: whilehs { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb6,0x59,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252859b6 <unknown>
+
+whilehs {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01011011-11111110
+// CHECK-INST: whilehs { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5b,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f5bfe <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilele-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilele-diagnostics.s
index 666ce7de3074a..da140286f5358 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilele-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilele-diagnostics.s
@@ -28,3 +28,13 @@ whilele pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilele pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilele { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilele { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilele { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilele { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilele.s b/llvm/test/MC/AArch64/SVE2p1/whilele.s
index 0e00c508700eb..f1824ecc8a411 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilele.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilele.s
@@ -37,6 +37,30 @@ whilele pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01100111-11111111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f67ff <unknown>
 
+whilele {p0.h, p1.h}, x0, x0  // 00100101-01100000-01010100-00010001
+// CHECK-INST: whilele { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x11,0x54,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605411 <unknown>
+
+whilele {p4.h, p5.h}, x10, x21  // 00100101-01110101-01010101-01010101
+// CHECK-INST: whilele { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x55,0x55,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755555 <unknown>
+
+whilele {p6.h, p7.h}, x13, x8  // 00100101-01101000-01010101-10110111
+// CHECK-INST: whilele { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb7,0x55,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256855b7 <unknown>
+
+whilele {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01010111-11111111
+// CHECK-INST: whilele { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x57,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f57ff <unknown>
+
 whilele pn8.s, x0, x0, vlx2  // 00100101-10100000-01000100-00011000
 // CHECK-INST: whilele pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x44,0xa0,0x25]
@@ -61,6 +85,30 @@ whilele pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01100111-11111111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf67ff <unknown>
 
+whilele {p0.s, p1.s}, x0, x0  // 00100101-10100000-01010100-00010001
+// CHECK-INST: whilele { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x11,0x54,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05411 <unknown>
+
+whilele {p4.s, p5.s}, x10, x21  // 00100101-10110101-01010101-01010101
+// CHECK-INST: whilele { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x55,0x55,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55555 <unknown>
+
+whilele {p6.s, p7.s}, x13, x8  // 00100101-10101000-01010101-10110111
+// CHECK-INST: whilele { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb7,0x55,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a855b7 <unknown>
+
+whilele {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01010111-11111111
+// CHECK-INST: whilele { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x57,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf57ff <unknown>
+
 whilele pn8.d, x0, x0, vlx2  // 00100101-11100000-01000100-00011000
 // CHECK-INST: whilele pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x44,0xe0,0x25]
@@ -85,6 +133,30 @@ whilele pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01100111-11111111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff67ff <unknown>
 
+whilele {p0.d, p1.d}, x0, x0  // 00100101-11100000-01010100-00010001
+// CHECK-INST: whilele { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x11,0x54,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05411 <unknown>
+
+whilele {p4.d, p5.d}, x10, x21  // 00100101-11110101-01010101-01010101
+// CHECK-INST: whilele { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x55,0x55,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55555 <unknown>
+
+whilele {p6.d, p7.d}, x13, x8  // 00100101-11101000-01010101-10110111
+// CHECK-INST: whilele { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb7,0x55,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e855b7 <unknown>
+
+whilele {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01010111-11111111
+// CHECK-INST: whilele { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x57,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff57ff <unknown>
+
 whilele pn8.b, x0, x0, vlx2  // 00100101-00100000-01000100-00011000
 // CHECK-INST: whilele pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x44,0x20,0x25]
@@ -108,3 +180,27 @@ whilele pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01100111-11111111
 // CHECK-ENCODING: [0xff,0x67,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f67ff <unknown>
+
+whilele {p0.b, p1.b}, x0, x0  // 00100101-00100000-01010100-00010001
+// CHECK-INST: whilele { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x11,0x54,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205411 <unknown>
+
+whilele {p4.b, p5.b}, x10, x21  // 00100101-00110101-01010101-01010101
+// CHECK-INST: whilele { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x55,0x55,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355555 <unknown>
+
+whilele {p6.b, p7.b}, x13, x8  // 00100101-00101000-01010101-10110111
+// CHECK-INST: whilele { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb7,0x55,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252855b7 <unknown>
+
+whilele {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01010111-11111111
+// CHECK-INST: whilele { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x57,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f57ff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilelo-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilelo-diagnostics.s
index 4258893a4a01a..99ff3bce4063b 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilelo-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilelo-diagnostics.s
@@ -28,3 +28,13 @@ whilelo pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilelo pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilelo { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilelo { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilelo { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilelo { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilelo.s b/llvm/test/MC/AArch64/SVE2p1/whilelo.s
index 094747151bd58..5be4b66fc8c09 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilelo.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilelo.s
@@ -37,6 +37,30 @@ whilelo pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01101111-11110111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f6ff7 <unknown>
 
+whilelo {p0.h, p1.h}, x0, x0  // 00100101-01100000-01011100-00010000
+// CHECK-INST: whilelo { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x10,0x5c,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605c10 <unknown>
+
+whilelo {p4.h, p5.h}, x10, x21  // 00100101-01110101-01011101-01010100
+// CHECK-INST: whilelo { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x54,0x5d,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755d54 <unknown>
+
+whilelo {p6.h, p7.h}, x13, x8  // 00100101-01101000-01011101-10110110
+// CHECK-INST: whilelo { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb6,0x5d,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25685db6 <unknown>
+
+whilelo {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01011111-11111110
+// CHECK-INST: whilelo { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5f,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f5ffe <unknown>
+
 whilelo pn8.s, x0, x0, vlx2  // 00100101-10100000-01001100-00010000
 // CHECK-INST: whilelo pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x4c,0xa0,0x25]
@@ -61,6 +85,30 @@ whilelo pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01101111-11110111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf6ff7 <unknown>
 
+whilelo {p0.s, p1.s}, x0, x0  // 00100101-10100000-01011100-00010000
+// CHECK-INST: whilelo { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x10,0x5c,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05c10 <unknown>
+
+whilelo {p4.s, p5.s}, x10, x21  // 00100101-10110101-01011101-01010100
+// CHECK-INST: whilelo { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x54,0x5d,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55d54 <unknown>
+
+whilelo {p6.s, p7.s}, x13, x8  // 00100101-10101000-01011101-10110110
+// CHECK-INST: whilelo { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb6,0x5d,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a85db6 <unknown>
+
+whilelo {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01011111-11111110
+// CHECK-INST: whilelo { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5f,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf5ffe <unknown>
+
 whilelo pn8.d, x0, x0, vlx2  // 00100101-11100000-01001100-00010000
 // CHECK-INST: whilelo pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x4c,0xe0,0x25]
@@ -85,6 +133,30 @@ whilelo pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01101111-11110111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff6ff7 <unknown>
 
+whilelo {p0.d, p1.d}, x0, x0  // 00100101-11100000-01011100-00010000
+// CHECK-INST: whilelo { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x10,0x5c,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05c10 <unknown>
+
+whilelo {p4.d, p5.d}, x10, x21  // 00100101-11110101-01011101-01010100
+// CHECK-INST: whilelo { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x54,0x5d,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55d54 <unknown>
+
+whilelo {p6.d, p7.d}, x13, x8  // 00100101-11101000-01011101-10110110
+// CHECK-INST: whilelo { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb6,0x5d,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e85db6 <unknown>
+
+whilelo {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01011111-11111110
+// CHECK-INST: whilelo { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5f,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff5ffe <unknown>
+
 whilelo pn8.b, x0, x0, vlx2  // 00100101-00100000-01001100-00010000
 // CHECK-INST: whilelo pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x4c,0x20,0x25]
@@ -108,3 +180,27 @@ whilelo pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01101111-11110111
 // CHECK-ENCODING: [0xf7,0x6f,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f6ff7 <unknown>
+
+whilelo {p0.b, p1.b}, x0, x0  // 00100101-00100000-01011100-00010000
+// CHECK-INST: whilelo { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x10,0x5c,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205c10 <unknown>
+
+whilelo {p4.b, p5.b}, x10, x21  // 00100101-00110101-01011101-01010100
+// CHECK-INST: whilelo { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x54,0x5d,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355d54 <unknown>
+
+whilelo {p6.b, p7.b}, x13, x8  // 00100101-00101000-01011101-10110110
+// CHECK-INST: whilelo { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb6,0x5d,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25285db6 <unknown>
+
+whilelo {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01011111-11111110
+// CHECK-INST: whilelo { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5f,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f5ffe <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilels-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilels-diagnostics.s
index 765c3555c801b..b57bfff82d1d5 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilels-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilels-diagnostics.s
@@ -28,3 +28,13 @@ whilels pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilels pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilels { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilels { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilels { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilels { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilels.s b/llvm/test/MC/AArch64/SVE2p1/whilels.s
index 608f48483ab25..89d98517cd498 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilels.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilels.s
@@ -37,6 +37,30 @@ whilels pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01101111-11111111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f6fff <unknown>
 
+whilels {p0.h, p1.h}, x0, x0  // 00100101-01100000-01011100-00010001
+// CHECK-INST: whilels { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x11,0x5c,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605c11 <unknown>
+
+whilels {p4.h, p5.h}, x10, x21  // 00100101-01110101-01011101-01010101
+// CHECK-INST: whilels { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x55,0x5d,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755d55 <unknown>
+
+whilels {p6.h, p7.h}, x13, x8  // 00100101-01101000-01011101-10110111
+// CHECK-INST: whilels { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb7,0x5d,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25685db7 <unknown>
+
+whilels {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01011111-11111111
+// CHECK-INST: whilels { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5f,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f5fff <unknown>
+
 whilels pn8.s, x0, x0, vlx2  // 00100101-10100000-01001100-00011000
 // CHECK-INST: whilels pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x4c,0xa0,0x25]
@@ -61,6 +85,30 @@ whilels pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01101111-11111111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf6fff <unknown>
 
+whilels {p0.s, p1.s}, x0, x0  // 00100101-10100000-01011100-00010001
+// CHECK-INST: whilels { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x11,0x5c,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05c11 <unknown>
+
+whilels {p4.s, p5.s}, x10, x21  // 00100101-10110101-01011101-01010101
+// CHECK-INST: whilels { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x55,0x5d,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55d55 <unknown>
+
+whilels {p6.s, p7.s}, x13, x8  // 00100101-10101000-01011101-10110111
+// CHECK-INST: whilels { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb7,0x5d,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a85db7 <unknown>
+
+whilels {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01011111-11111111
+// CHECK-INST: whilels { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5f,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf5fff <unknown>
+
 whilels pn8.d, x0, x0, vlx2  // 00100101-11100000-01001100-00011000
 // CHECK-INST: whilels pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x4c,0xe0,0x25]
@@ -85,6 +133,30 @@ whilels pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01101111-11111111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff6fff <unknown>
 
+whilels {p0.d, p1.d}, x0, x0  // 00100101-11100000-01011100-00010001
+// CHECK-INST: whilels { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x11,0x5c,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05c11 <unknown>
+
+whilels {p4.d, p5.d}, x10, x21  // 00100101-11110101-01011101-01010101
+// CHECK-INST: whilels { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x55,0x5d,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55d55 <unknown>
+
+whilels {p6.d, p7.d}, x13, x8  // 00100101-11101000-01011101-10110111
+// CHECK-INST: whilels { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb7,0x5d,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e85db7 <unknown>
+
+whilels {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01011111-11111111
+// CHECK-INST: whilels { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5f,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff5fff <unknown>
+
 whilels pn8.b, x0, x0, vlx2  // 00100101-00100000-01001100-00011000
 // CHECK-INST: whilels pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x4c,0x20,0x25]
@@ -108,3 +180,27 @@ whilels pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01101111-11111111
 // CHECK-ENCODING: [0xff,0x6f,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f6fff <unknown>
+
+whilels {p0.b, p1.b}, x0, x0  // 00100101-00100000-01011100-00010001
+// CHECK-INST: whilels { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x11,0x5c,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205c11 <unknown>
+
+whilels {p4.b, p5.b}, x10, x21  // 00100101-00110101-01011101-01010101
+// CHECK-INST: whilels { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x55,0x5d,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355d55 <unknown>
+
+whilels {p6.b, p7.b}, x13, x8  // 00100101-00101000-01011101-10110111
+// CHECK-INST: whilels { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb7,0x5d,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25285db7 <unknown>
+
+whilels {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01011111-11111111
+// CHECK-INST: whilels { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5f,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f5fff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilelt-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilelt-diagnostics.s
index 54c2c05d43cde..97a50da6e7b79 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilelt-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilelt-diagnostics.s
@@ -28,3 +28,13 @@ whilelt pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilelt pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilelt { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilelt { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilelt { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilelt { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/whilelt.s b/llvm/test/MC/AArch64/SVE2p1/whilelt.s
index fe67c928146d9..dd0d3b77f00ae 100644
--- a/llvm/test/MC/AArch64/SVE2p1/whilelt.s
+++ b/llvm/test/MC/AArch64/SVE2p1/whilelt.s
@@ -37,6 +37,30 @@ whilelt pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01100111-11110111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f67f7 <unknown>
 
+whilelt {p0.h, p1.h}, x0, x0  // 00100101-01100000-01010100-00010000
+// CHECK-INST: whilelt { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x10,0x54,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605410 <unknown>
+
+whilelt {p4.h, p5.h}, x10, x21  // 00100101-01110101-01010101-01010100
+// CHECK-INST: whilelt { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x54,0x55,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755554 <unknown>
+
+whilelt {p6.h, p7.h}, x13, x8  // 00100101-01101000-01010101-10110110
+// CHECK-INST: whilelt { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb6,0x55,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256855b6 <unknown>
+
+whilelt {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01010111-11111110
+// CHECK-INST: whilelt { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x57,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f57fe <unknown>
+
 whilelt pn8.s, x0, x0, vlx2  // 00100101-10100000-01000100-00010000
 // CHECK-INST: whilelt pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x44,0xa0,0x25]
@@ -61,6 +85,30 @@ whilelt pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01100111-11110111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf67f7 <unknown>
 
+whilelt {p0.s, p1.s}, x0, x0  // 00100101-10100000-01010100-00010000
+// CHECK-INST: whilelt { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x10,0x54,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05410 <unknown>
+
+whilelt {p4.s, p5.s}, x10, x21  // 00100101-10110101-01010101-01010100
+// CHECK-INST: whilelt { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x54,0x55,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55554 <unknown>
+
+whilelt {p6.s, p7.s}, x13, x8  // 00100101-10101000-01010101-10110110
+// CHECK-INST: whilelt { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb6,0x55,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a855b6 <unknown>
+
+whilelt {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01010111-11111110
+// CHECK-INST: whilelt { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x57,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf57fe <unknown>
+
 whilelt pn8.d, x0, x0, vlx2  // 00100101-11100000-01000100-00010000
 // CHECK-INST: whilelt pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x44,0xe0,0x25]
@@ -85,6 +133,30 @@ whilelt pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01100111-11110111
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff67f7 <unknown>
 
+whilelt {p0.d, p1.d}, x0, x0  // 00100101-11100000-01010100-00010000
+// CHECK-INST: whilelt { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x10,0x54,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05410 <unknown>
+
+whilelt {p4.d, p5.d}, x10, x21  // 00100101-11110101-01010101-01010100
+// CHECK-INST: whilelt { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x54,0x55,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55554 <unknown>
+
+whilelt {p6.d, p7.d}, x13, x8  // 00100101-11101000-01010101-10110110
+// CHECK-INST: whilelt { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb6,0x55,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e855b6 <unknown>
+
+whilelt {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01010111-11111110
+// CHECK-INST: whilelt { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x57,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff57fe <unknown>
+
 whilelt pn8.b, x0, x0, vlx2  // 00100101-00100000-01000100-00010000
 // CHECK-INST: whilelt pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x44,0x20,0x25]
@@ -108,3 +180,27 @@ whilelt pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01100111-11110111
 // CHECK-ENCODING: [0xf7,0x67,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f67f7 <unknown>
+
+whilelt {p0.b, p1.b}, x0, x0  // 00100101-00100000-01010100-00010000
+// CHECK-INST: whilelt { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x10,0x54,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205410 <unknown>
+
+whilelt {p4.b, p5.b}, x10, x21  // 00100101-00110101-01010101-01010100
+// CHECK-INST: whilelt { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x54,0x55,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355554 <unknown>
+
+whilelt {p6.b, p7.b}, x13, x8  // 00100101-00101000-01010101-10110110
+// CHECK-INST: whilelt { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb6,0x55,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252855b6 <unknown>
+
+whilelt {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01010111-11111110
+// CHECK-INST: whilelt { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x57,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f57fe <unknown>