diff --git a/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll b/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll index b719f9f4d23543..6dbce9ec068d11 100644 --- a/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll +++ b/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null -%struct.layer_data = type { i32, [2048 x i8], i8*, [16 x i8], i32, i8*, i32, i32, [64 x i32], [64 x i32], [64 x i32], [64 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [12 x [64 x i16]] } -@ld = external global %struct.layer_data* ; <%struct.layer_data**> [#uses=1] +%struct.layer_data = type { i32, [2048 x i8], ptr, [16 x i8], i32, ptr, i32, i32, [64 x i32], [64 x i32], [64 x i32], [64 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [12 x [64 x i16]] } +@ld = external global ptr ; [#uses=1] define void @main() { entry: @@ -11,10 +11,10 @@ bb169.i: ; preds = %entry ret void cond_true11: ; preds = %entry - %tmp.i32 = load %struct.layer_data*, %struct.layer_data** @ld ; <%struct.layer_data*> [#uses=2] - %tmp3.i35 = getelementptr %struct.layer_data, %struct.layer_data* %tmp.i32, i32 0, i32 1, i32 2048; [#uses=2] - %tmp.i36 = getelementptr %struct.layer_data, %struct.layer_data* %tmp.i32, i32 0, i32 2 ; [#uses=1] - store i8* %tmp3.i35, i8** %tmp.i36 - store i8* %tmp3.i35, i8** null + %tmp.i32 = load ptr, ptr @ld ; [#uses=2] + %tmp3.i35 = getelementptr %struct.layer_data, ptr %tmp.i32, i32 0, i32 1, i32 2048; [#uses=2] + %tmp.i36 = getelementptr %struct.layer_data, ptr %tmp.i32, i32 0, i32 2 ; [#uses=1] + store ptr %tmp3.i35, ptr %tmp.i36 + store ptr %tmp3.i35, ptr null ret void } diff --git a/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll index a35ded5b545765..c41921b589eba8 100644 --- a/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll +++ b/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll @@ -4,30 +4,30 @@ ; The execution domain checking code would translate vmovs to vorr whether or not ; we had NEON instructions. Verify we don't if we're not compiled with NEON. ; DOMAIN-NOT: vorr -@quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] -@dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] -@A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1] +@quant_coef = external global [6 x [4 x [4 x i32]]] ; [#uses=1] +@dequant_coef = external global [6 x [4 x [4 x i32]]] ; [#uses=1] +@A = external global [4 x [4 x i32]] ; [#uses=1] ; CHECK-LABEL: dct_luma_sp: -define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) "frame-pointer"="all" { +define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, ptr %coeff_cost) "frame-pointer"="all" { entry: ; Make sure to use base-updating stores for saving callee-saved registers. ; CHECK: push ; CHECK-NOT: sub sp ; CHECK: push - %predicted_block = alloca [4 x [4 x i32]], align 4 ; <[4 x [4 x i32]]*> [#uses=1] + %predicted_block = alloca [4 x [4 x i32]], align 4 ; [#uses=1] br label %cond_next489 cond_next489: ; preds = %cond_false, %bb471 - %j.7.in = load i8, i8* null ; [#uses=1] - %i.8.in = load i8, i8* null ; [#uses=1] + %j.7.in = load i8, ptr null ; [#uses=1] + %i.8.in = load i8, ptr null ; [#uses=1] %i.8 = zext i8 %i.8.in to i32 ; [#uses=4] %j.7 = zext i8 %j.7.in to i32 ; [#uses=4] - %tmp495 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* %predicted_block, i32 0, i32 %i.8, i32 %j.7 ; [#uses=2] - %tmp496 = load i32, i32* %tmp495 ; [#uses=2] - %tmp502 = load i32, i32* null ; [#uses=1] - %tmp542 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; [#uses=1] - %tmp543 = load i32, i32* %tmp542 ; [#uses=1] + %tmp495 = getelementptr [4 x [4 x i32]], ptr %predicted_block, i32 0, i32 %i.8, i32 %j.7 ; [#uses=2] + %tmp496 = load i32, ptr %tmp495 ; [#uses=2] + %tmp502 = load i32, ptr null ; [#uses=1] + %tmp542 = getelementptr [6 x [4 x [4 x i32]]], ptr @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; [#uses=1] + %tmp543 = load i32, ptr %tmp542 ; [#uses=1] %tmp548 = ashr i32 0, 0 ; [#uses=3] %tmp561 = sub i32 0, %tmp496 ; [#uses=3] %abscond563 = icmp sgt i32 %tmp561, -1 ; [#uses=1] @@ -39,10 +39,10 @@ cond_next489: ; preds = %cond_false, %bb471 br i1 %tmp579, label %bb712, label %cond_next589 cond_next589: ; preds = %cond_next489 - %tmp605 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @dequant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; [#uses=1] - %tmp606 = load i32, i32* %tmp605 ; [#uses=1] - %tmp612 = load i32, i32* null ; [#uses=1] - %tmp629 = load i32, i32* null ; [#uses=1] + %tmp605 = getelementptr [6 x [4 x [4 x i32]]], ptr @dequant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; [#uses=1] + %tmp606 = load i32, ptr %tmp605 ; [#uses=1] + %tmp612 = load i32, ptr null ; [#uses=1] + %tmp629 = load i32, ptr null ; [#uses=1] %tmp629a = sitofp i32 %tmp629 to double ; [#uses=1] %tmp631 = fmul double %tmp629a, 0.000000e+00 ; [#uses=1] %tmp632 = fadd double 0.000000e+00, %tmp631 ; [#uses=1] @@ -54,7 +54,7 @@ cond_next589: ; preds = %cond_next489 %tmp660 = sub i32 0, %tmp659 ; [#uses=1] %tmp666 = sub i32 %tmp660, %tmp496 ; [#uses=1] %tmp667 = sitofp i32 %tmp666 to double ; [#uses=2] - call void @levrun_linfo_inter( i32 %tmp576, i32 0, i32* null, i32* null ) + call void @levrun_linfo_inter( i32 %tmp576, i32 0, ptr null, ptr null ) %tmp671 = fmul double %tmp667, %tmp667 ; [#uses=1] %tmp675 = fadd double %tmp671, 0.000000e+00 ; [#uses=1] %tmp678 = fcmp oeq double %tmp632, %tmp675 ; [#uses=1] @@ -89,9 +89,9 @@ bb737: ; preds = %cond_false689 cond_true740: ; preds = %bb737 %tmp761 = call fastcc i32 @sign( i32 %tmp576, i32 0 ) ; [#uses=1] - %tmp780 = load i32, i32* null ; [#uses=1] - %tmp785 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* @A, i32 0, i32 %i.8, i32 %j.7 ; [#uses=1] - %tmp786 = load i32, i32* %tmp785 ; [#uses=1] + %tmp780 = load i32, ptr null ; [#uses=1] + %tmp785 = getelementptr [4 x [4 x i32]], ptr @A, i32 0, i32 %i.8, i32 %j.7 ; [#uses=1] + %tmp786 = load i32, ptr %tmp785 ; [#uses=1] %tmp781 = mul i32 %tmp780, %tmp761 ; [#uses=1] %tmp787 = mul i32 %tmp781, %tmp786 ; [#uses=1] %tmp789 = shl i32 %tmp787, 0 ; [#uses=1] @@ -100,7 +100,7 @@ cond_true740: ; preds = %bb737 cond_next791: ; preds = %cond_true740, %bb737 %ilev.1 = phi i32 [ %tmp790, %cond_true740 ], [ 0, %bb737 ] ; [#uses=1] - %tmp796 = load i32, i32* %tmp495 ; [#uses=1] + %tmp796 = load i32, ptr %tmp495 ; [#uses=1] %tmp798 = add i32 %tmp796, %ilev.1 ; [#uses=1] %tmp812 = mul i32 0, %tmp502 ; [#uses=0] %tmp818 = call fastcc i32 @sign( i32 0, i32 %tmp798 ) ; [#uses=0] @@ -109,4 +109,4 @@ cond_next791: ; preds = %cond_true740, %bb737 declare i32 @sign(i32, i32) -declare void @levrun_linfo_inter(i32, i32, i32*, i32*) +declare void @levrun_linfo_inter(i32, i32, ptr, ptr) diff --git a/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll b/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll index 472a345a0d71c5..c549553fd399ae 100644 --- a/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll +++ b/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll @@ -1,13 +1,13 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 -define fastcc i8* @read_sleb128(i8* %p, i32* %val) { +define fastcc ptr @read_sleb128(ptr %p, ptr %val) { br label %bb bb: ; preds = %bb, %0 - %p_addr.0 = getelementptr i8, i8* %p, i32 0 ; [#uses=1] - %tmp2 = load i8, i8* %p_addr.0 ; [#uses=2] + %p_addr.0 = getelementptr i8, ptr %p, i32 0 ; [#uses=1] + %tmp2 = load i8, ptr %p_addr.0 ; [#uses=2] %tmp4.rec = add i32 0, 1 ; [#uses=1] - %tmp4 = getelementptr i8, i8* %p, i32 %tmp4.rec ; [#uses=1] + %tmp4 = getelementptr i8, ptr %p, i32 %tmp4.rec ; [#uses=1] %tmp56 = zext i8 %tmp2 to i32 ; [#uses=1] %tmp7 = and i32 %tmp56, 127 ; [#uses=1] %tmp9 = shl i32 %tmp7, 0 ; [#uses=1] @@ -16,6 +16,6 @@ bb: ; preds = %bb, %0 br i1 %1, label %bb, label %cond_next28 cond_next28: ; preds = %bb - store i32 %tmp11, i32* %val - ret i8* %tmp4 + store i32 %tmp11, ptr %val + ret ptr %tmp4 } diff --git a/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll b/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll index a379f63ab8bf55..58158b1b678a78 100644 --- a/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll +++ b/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll @@ -2,49 +2,49 @@ ; RUN: llc -mtriple arm-apple-darwin -relocation-model pic -mattr=+v6 -filetype asm -o - %s | FileCheck -check-prefix CHECK-R9 %s ; RUN: llc -mtriple arm-apple-darwin -relocation-model pic -mattr=+v6,+reserve-r9 -ifcvt-limit=0 -stats -o /dev/null %s 2>&1 | FileCheck -check-prefix CHECK-ASM-PRINTER %s -define void @test(i32 %tmp56222, i32 %tmp36224, i32 %tmp46223, i32 %i.0196.0.ph, i32 %tmp8, i32* %tmp1011, i32** %tmp1, i32* %d2.1.out, i32* %d3.1.out, i32* %d0.1.out, i32* %d1.1.out) { +define void @test(i32 %tmp56222, i32 %tmp36224, i32 %tmp46223, i32 %i.0196.0.ph, i32 %tmp8, ptr %tmp1011, ptr %tmp1, ptr %d2.1.out, ptr %d3.1.out, ptr %d0.1.out, ptr %d1.1.out) { newFuncRoot: br label %bb74 bb78.exitStub: - store i32 %d2.1, i32* %d2.1.out - store i32 %d3.1, i32* %d3.1.out - store i32 %d0.1, i32* %d0.1.out - store i32 %d1.1, i32* %d1.1.out + store i32 %d2.1, ptr %d2.1.out + store i32 %d3.1, ptr %d3.1.out + store i32 %d0.1, ptr %d0.1.out + store i32 %d1.1, ptr %d1.1.out ret void bb74: %fp.1.rec = phi i32 [ 0, %newFuncRoot ], [ %tmp71.rec, %bb26 ] - %fm.1.in = phi i32* [ %tmp71, %bb26 ], [ %tmp1011, %newFuncRoot ] + %fm.1.in = phi ptr [ %tmp71, %bb26 ], [ %tmp1011, %newFuncRoot ] %d0.1 = phi i32 [ %tmp44, %bb26 ], [ 8192, %newFuncRoot ] %d1.1 = phi i32 [ %tmp54, %bb26 ], [ 8192, %newFuncRoot ] %d2.1 = phi i32 [ %tmp64, %bb26 ], [ 8192, %newFuncRoot ] %d3.1 = phi i32 [ %tmp69, %bb26 ], [ 8192, %newFuncRoot ] - %fm.1 = load i32, i32* %fm.1.in + %fm.1 = load i32, ptr %fm.1.in icmp eq i32 %fp.1.rec, %tmp8 br i1 %0, label %bb78.exitStub, label %bb26 bb26: - %tmp28 = getelementptr i32*, i32** %tmp1, i32 %fp.1.rec - %tmp30 = load i32*, i32** %tmp28 - %tmp33 = getelementptr i32, i32* %tmp30, i32 %i.0196.0.ph - %tmp34 = load i32, i32* %tmp33 - %tmp38 = getelementptr i32, i32* %tmp30, i32 %tmp36224 - %tmp39 = load i32, i32* %tmp38 + %tmp28 = getelementptr ptr, ptr %tmp1, i32 %fp.1.rec + %tmp30 = load ptr, ptr %tmp28 + %tmp33 = getelementptr i32, ptr %tmp30, i32 %i.0196.0.ph + %tmp34 = load i32, ptr %tmp33 + %tmp38 = getelementptr i32, ptr %tmp30, i32 %tmp36224 + %tmp39 = load i32, ptr %tmp38 %tmp42 = mul i32 %tmp34, %fm.1 %tmp44 = add i32 %tmp42, %d0.1 - %tmp48 = getelementptr i32, i32* %tmp30, i32 %tmp46223 - %tmp49 = load i32, i32* %tmp48 + %tmp48 = getelementptr i32, ptr %tmp30, i32 %tmp46223 + %tmp49 = load i32, ptr %tmp48 %tmp52 = mul i32 %tmp39, %fm.1 %tmp54 = add i32 %tmp52, %d1.1 - %tmp58 = getelementptr i32, i32* %tmp30, i32 %tmp56222 - %tmp59 = load i32, i32* %tmp58 + %tmp58 = getelementptr i32, ptr %tmp30, i32 %tmp56222 + %tmp59 = load i32, ptr %tmp58 %tmp62 = mul i32 %tmp49, %fm.1 %tmp64 = add i32 %tmp62, %d2.1 %tmp67 = mul i32 %tmp59, %fm.1 %tmp69 = add i32 %tmp67, %d3.1 %tmp71.rec = add i32 %fp.1.rec, 1 - %tmp71 = getelementptr i32, i32* %tmp1011, i32 %tmp71.rec + %tmp71 = getelementptr i32, ptr %tmp1011, i32 %tmp71.rec br label %bb74 } diff --git a/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll b/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll index 7c425961958ca6..6ecca2f0672071 100644 --- a/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll +++ b/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll @@ -3,32 +3,32 @@ %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32 } %struct.arm_stack_offsets = type { i32, i32, i32, i32, i32 } - %struct.c_arg_info = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i8 } + %struct.c_arg_info = type { ptr, ptr, ptr, ptr, i8 } %struct.c_language_function = type { %struct.stmt_tree_s } %struct.c_switch = type opaque %struct.eh_status = type opaque - %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** } - %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* } - %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, i8, i8, i8 } - %struct.ht_identifier = type { i8*, i32, i32 } + %struct.emit_status = type { i32, i32, ptr, ptr, ptr, i32, %struct.location_t, i32, ptr, ptr } + %struct.expr_status = type { i32, i32, i32, ptr, ptr, ptr } + %struct.function = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, i32, ptr, %struct.CUMULATIVE_ARGS, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i8, i32, i64, ptr, ptr, ptr, ptr, ptr, i32, ptr, i32, i32, ptr, ptr, i32, i32, i32, ptr, i32, i32, i8, i8, ptr, ptr, i32, i32, i32, i32, %struct.location_t, ptr, ptr, i8, i8, i8 } + %struct.ht_identifier = type { ptr, i32, i32 } %struct.initial_value_struct = type opaque %struct.lang_decl = type { i8 } - %struct.language_function = type { %struct.c_language_function, %struct.tree_node*, %struct.tree_node*, %struct.c_switch*, %struct.c_arg_info*, i32, i32, i32, i32 } - %struct.location_t = type { i8*, i32 } - %struct.machine_function = type { %struct.rtx_def*, i32, i32, i32, %struct.arm_stack_offsets, i32, i32, i32, [14 x %struct.rtx_def*] } - %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] } + %struct.language_function = type { %struct.c_language_function, ptr, ptr, ptr, ptr, i32, i32, i32, i32 } + %struct.location_t = type { ptr, i32 } + %struct.machine_function = type { ptr, i32, i32, i32, %struct.arm_stack_offsets, i32, i32, i32, [14 x ptr] } + %struct.rtvec_def = type { i32, [1 x ptr] } %struct.rtx_def = type { i16, i8, i8, %struct.u } - %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* } - %struct.stmt_tree_s = type { %struct.tree_node*, i32 } + %struct.sequence_stack = type { ptr, ptr, ptr } + %struct.stmt_tree_s = type { ptr, i32 } %struct.temp_slot = type opaque - %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 } - %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* } + %struct.tree_common = type { ptr, ptr, ptr, i8, i8, i8, i8, i8 } + %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, ptr, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, %struct.tree_decl_u2, ptr, ptr, i64, ptr } %struct.tree_decl_u1 = type { i64 } - %struct.tree_decl_u2 = type { %struct.function* } + %struct.tree_decl_u2 = type { ptr } %struct.tree_identifier = type { %struct.tree_common, %struct.ht_identifier } %struct.tree_node = type { %struct.tree_decl } %struct.u = type { [1 x i64] } - %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* } + %struct.var_refs_queue = type { ptr, i32, i32, ptr } %struct.varasm_status = type opaque %struct.varray_head_tag = type opaque %union.tree_ann_d = type opaque @@ -40,9 +40,8 @@ entry: %spec.1961.adj = shl i64 %spec.1961, 32 ; [#uses=1] %spec.1961.adj.ins = or i64 %spec.1961.adj, 0 ; [#uses=2] %tmp10959 = lshr i64 %spec.1961.adj.ins, 32 ; [#uses=2] - %tmp1920 = inttoptr i64 %tmp10959 to %struct.tree_common* ; <%struct.tree_common*> [#uses=1] - %tmp21 = getelementptr %struct.tree_common, %struct.tree_common* %tmp1920, i32 0, i32 3 ; [#uses=1] - %tmp2122 = bitcast i8* %tmp21 to i32* ; [#uses=1] + %tmp1920 = inttoptr i64 %tmp10959 to ptr ; [#uses=1] + %tmp21 = getelementptr %struct.tree_common, ptr %tmp1920, i32 0, i32 3 ; [#uses=1] br i1 false, label %cond_next53, label %cond_true cond_true: ; preds = %entry @@ -71,7 +70,7 @@ cond_next856: ; preds = %cond_true851 ret void bb866: ; preds = %cond_true851 - %tmp874 = load i32, i32* %tmp2122 ; [#uses=1] + %tmp874 = load i32, ptr %tmp21 ; [#uses=1] %tmp876877 = trunc i32 %tmp874 to i8 ; [#uses=1] icmp eq i8 %tmp876877, 1 ; :0 [#uses=1] br i1 %0, label %cond_next881, label %cond_true878 @@ -80,10 +79,10 @@ cond_true878: ; preds = %bb866 unreachable cond_next881: ; preds = %bb866 - %tmp884885 = inttoptr i64 %tmp10959 to %struct.tree_identifier* ; <%struct.tree_identifier*> [#uses=1] - %tmp887 = getelementptr %struct.tree_identifier, %struct.tree_identifier* %tmp884885, i32 0, i32 1, i32 0 ; [#uses=1] - %tmp888 = load i8*, i8** %tmp887 ; [#uses=1] - tail call void (i32, ...) @error( i32 undef, i8* %tmp888 ) + %tmp884885 = inttoptr i64 %tmp10959 to ptr ; [#uses=1] + %tmp887 = getelementptr %struct.tree_identifier, ptr %tmp884885, i32 0, i32 1, i32 0 ; [#uses=1] + %tmp888 = load ptr, ptr %tmp887 ; [#uses=1] + tail call void (i32, ...) @error( i32 undef, ptr %tmp888 ) ret void cond_true918: ; preds = %cond_false841 diff --git a/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll index 14bb313185bc54..586dffd763ece4 100644 --- a/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll @@ -4,16 +4,16 @@ %struct.rtx_def = type { i16, i8, i8, %struct.u } %struct.u = type { [1 x i64] } -define fastcc void @find_reloads_address(%struct.rtx_def** %loc) { +define fastcc void @find_reloads_address(ptr %loc) { entry: - %ad_addr = alloca %struct.rtx_def* ; <%struct.rtx_def**> [#uses=2] + %ad_addr = alloca ptr ; [#uses=2] br i1 false, label %cond_next416, label %cond_true340 cond_true340: ; preds = %entry ret void cond_next416: ; preds = %entry - %tmp1085 = load %struct.rtx_def*, %struct.rtx_def** %ad_addr ; <%struct.rtx_def*> [#uses=1] + %tmp1085 = load ptr, ptr %ad_addr ; [#uses=1] br i1 false, label %bb1084, label %cond_true418 cond_true418: ; preds = %cond_next416 @@ -23,13 +23,12 @@ bb1084: ; preds = %cond_next416 br i1 false, label %cond_true1092, label %cond_next1102 cond_true1092: ; preds = %bb1084 - %tmp1094 = getelementptr %struct.rtx_def, %struct.rtx_def* %tmp1085, i32 0, i32 3 ; <%struct.u*> [#uses=1] - %tmp10981099 = bitcast %struct.u* %tmp1094 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=2] - %tmp1101 = load %struct.rtx_def*, %struct.rtx_def** %tmp10981099 ; <%struct.rtx_def*> [#uses=1] - store %struct.rtx_def* %tmp1101, %struct.rtx_def** %ad_addr + %tmp1094 = getelementptr %struct.rtx_def, ptr %tmp1085, i32 0, i32 3 ; [#uses=1] + %tmp1101 = load ptr, ptr %tmp1094 ; [#uses=1] + store ptr %tmp1101, ptr %ad_addr br label %cond_next1102 cond_next1102: ; preds = %cond_true1092, %bb1084 - %loc_addr.0 = phi %struct.rtx_def** [ %tmp10981099, %cond_true1092 ], [ %loc, %bb1084 ] ; <%struct.rtx_def**> [#uses=0] + %loc_addr.0 = phi ptr [ %tmp1094, %cond_true1092 ], [ %loc, %bb1084 ] ; [#uses=0] ret void } diff --git a/llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll index 8a62669708553a..5efa284a356ca1 100644 --- a/llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll @@ -4,30 +4,30 @@ %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32 } %struct.arm_stack_offsets = type { i32, i32, i32, i32, i32 } %struct.eh_status = type opaque - %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** } - %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* } - %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, i8, i8, i8 } + %struct.emit_status = type { i32, i32, ptr, ptr, ptr, i32, %struct.location_t, i32, ptr, ptr } + %struct.expr_status = type { i32, i32, i32, ptr, ptr, ptr } + %struct.function = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, i32, ptr, %struct.CUMULATIVE_ARGS, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i8, i32, i64, ptr, ptr, ptr, ptr, ptr, i32, ptr, i32, i32, ptr, ptr, i32, i32, i32, ptr, i32, i32, i8, i8, ptr, ptr, i32, i32, i32, i32, %struct.location_t, ptr, ptr, i8, i8, i8 } %struct.initial_value_struct = type opaque %struct.lang_decl = type opaque %struct.language_function = type opaque - %struct.location_t = type { i8*, i32 } - %struct.machine_function = type { %struct.rtx_def*, i32, i32, i32, %struct.arm_stack_offsets, i32, i32, i32, [14 x %struct.rtx_def*] } - %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] } + %struct.location_t = type { ptr, i32 } + %struct.machine_function = type { ptr, i32, i32, i32, %struct.arm_stack_offsets, i32, i32, i32, [14 x ptr] } + %struct.rtvec_def = type { i32, [1 x ptr] } %struct.rtx_def = type { i16, i8, i8, %struct.u } - %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* } + %struct.sequence_stack = type { ptr, ptr, ptr } %struct.temp_slot = type opaque - %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 } - %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* } + %struct.tree_common = type { ptr, ptr, ptr, i8, i8, i8, i8, i8 } + %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, ptr, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, %struct.tree_decl_u2, ptr, ptr, i64, ptr } %struct.tree_decl_u1 = type { i64 } - %struct.tree_decl_u2 = type { %struct.function* } + %struct.tree_decl_u2 = type { ptr } %struct.tree_node = type { %struct.tree_decl } %struct.u = type { [1 x i64] } - %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* } + %struct.var_refs_queue = type { ptr, i32, i32, ptr } %struct.varasm_status = type opaque - %struct.varray_head_tag = type { i32, i32, i32, i8*, %struct.u } + %struct.varray_head_tag = type { i32, i32, i32, ptr, %struct.u } %union.tree_ann_d = type opaque -@str469 = external global [42 x i8] ; <[42 x i8]*> [#uses=0] -@__FUNCTION__.24265 = external global [19 x i8] ; <[19 x i8]*> [#uses=0] +@str469 = external global [42 x i8] ; [#uses=0] +@__FUNCTION__.24265 = external global [19 x i8] ; [#uses=0] declare void @fancy_abort() diff --git a/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll index cf913536b3553c..4cea5400980ea0 100644 --- a/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll @@ -3,36 +3,36 @@ %struct.H_TBL = type { [17 x i8], [256 x i8], i32 } %struct.Q_TBL = type { [64 x i16], i32 } %struct.anon = type { [80 x i8] } - %struct.X_c_coef_ccler = type { void (%struct.X_Y*, i32)*, i32 (%struct.X_Y*, i8***)* } - %struct.X_c_main_ccler = type { void (%struct.X_Y*, i32)*, void (%struct.X_Y*, i8**, i32*, i32)* } - %struct.X_c_prep_ccler = type { void (%struct.X_Y*, i32)*, void (%struct.X_Y*, i8**, i32*, i32, i8***, i32*, i32)* } - %struct.X_color_converter = type { void (%struct.X_Y*)*, void (%struct.X_Y*, i8**, i8***, i32, i32)* } - %struct.X_common_struct = type { %struct.X_error_mgr*, %struct.X_memory_mgr*, %struct.X_progress_mgr*, i8*, i32, i32 } - %struct.X_comp_main = type { void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, i32, i32 } - %struct.X_component_info = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.Q_TBL*, i8* } - %struct.X_Y = type { %struct.X_error_mgr*, %struct.X_memory_mgr*, %struct.X_progress_mgr*, i8*, i32, i32, %struct.X_destination_mgr*, i32, i32, i32, i32, double, i32, i32, i32, %struct.X_component_info*, [4 x %struct.Q_TBL*], [4 x %struct.H_TBL*], [4 x %struct.H_TBL*], [16 x i8], [16 x i8], [16 x i8], i32, %struct.X_scan_info*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i16, i16, i32, i32, i32, i32, i32, i32, i32, [4 x %struct.X_component_info*], i32, i32, i32, [10 x i32], i32, i32, i32, i32, %struct.X_comp_main*, %struct.X_c_main_ccler*, %struct.X_c_prep_ccler*, %struct.X_c_coef_ccler*, %struct.X_marker_writer*, %struct.X_color_converter*, %struct.X_downssr*, %struct.X_forward_D*, %struct.X_entropy_en*, %struct.X_scan_info*, i32 } - %struct.X_destination_mgr = type { i8*, i32, void (%struct.X_Y*)*, i32 (%struct.X_Y*)*, void (%struct.X_Y*)* } - %struct.X_downssr = type { void (%struct.X_Y*)*, void (%struct.X_Y*, i8***, i32, i8***, i32)*, i32 } - %struct.X_entropy_en = type { void (%struct.X_Y*, i32)*, i32 (%struct.X_Y*, [64 x i16]**)*, void (%struct.X_Y*)* } - %struct.X_error_mgr = type { void (%struct.X_common_struct*)*, void (%struct.X_common_struct*, i32)*, void (%struct.X_common_struct*)*, void (%struct.X_common_struct*, i8*)*, void (%struct.X_common_struct*)*, i32, %struct.anon, i32, i32, i8**, i32, i8**, i32, i32 } - %struct.X_forward_D = type { void (%struct.X_Y*)*, void (%struct.X_Y*, %struct.X_component_info*, i8**, [64 x i16]*, i32, i32, i32)* } - %struct.X_marker_writer = type { void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*, i32, i32)*, void (%struct.X_Y*, i32)* } - %struct.X_memory_mgr = type { i8* (%struct.X_common_struct*, i32, i32)*, i8* (%struct.X_common_struct*, i32, i32)*, i8** (%struct.X_common_struct*, i32, i32, i32)*, [64 x i16]** (%struct.X_common_struct*, i32, i32, i32)*, %struct.jvirt_sAY_cc* (%struct.X_common_struct*, i32, i32, i32, i32, i32)*, %struct.jvirt_bAY_cc* (%struct.X_common_struct*, i32, i32, i32, i32, i32)*, void (%struct.X_common_struct*)*, i8** (%struct.X_common_struct*, %struct.jvirt_sAY_cc*, i32, i32, i32)*, [64 x i16]** (%struct.X_common_struct*, %struct.jvirt_bAY_cc*, i32, i32, i32)*, void (%struct.X_common_struct*, i32)*, void (%struct.X_common_struct*)*, i32, i32 } - %struct.X_progress_mgr = type { void (%struct.X_common_struct*)*, i32, i32, i32, i32 } + %struct.X_c_coef_ccler = type { ptr, ptr } + %struct.X_c_main_ccler = type { ptr, ptr } + %struct.X_c_prep_ccler = type { ptr, ptr } + %struct.X_color_converter = type { ptr, ptr } + %struct.X_common_struct = type { ptr, ptr, ptr, ptr, i32, i32 } + %struct.X_comp_main = type { ptr, ptr, ptr, i32, i32 } + %struct.X_component_info = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, ptr } + %struct.X_Y = type { ptr, ptr, ptr, ptr, i32, i32, ptr, i32, i32, i32, i32, double, i32, i32, i32, ptr, [4 x ptr], [4 x ptr], [4 x ptr], [16 x i8], [16 x i8], [16 x i8], i32, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i16, i16, i32, i32, i32, i32, i32, i32, i32, [4 x ptr], i32, i32, i32, [10 x i32], i32, i32, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32 } + %struct.X_destination_mgr = type { ptr, i32, ptr, ptr, ptr } + %struct.X_downssr = type { ptr, ptr, i32 } + %struct.X_entropy_en = type { ptr, ptr, ptr } + %struct.X_error_mgr = type { ptr, ptr, ptr, ptr, ptr, i32, %struct.anon, i32, i32, ptr, i32, ptr, i32, i32 } + %struct.X_forward_D = type { ptr, ptr } + %struct.X_marker_writer = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr } + %struct.X_memory_mgr = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32 } + %struct.X_progress_mgr = type { ptr, i32, i32, i32, i32 } %struct.X_scan_info = type { i32, [4 x i32], i32, i32, i32, i32 } %struct.jvirt_bAY_cc = type opaque %struct.jvirt_sAY_cc = type opaque -define void @test(%struct.X_Y* %cinfo) { +define void @test(ptr %cinfo) { entry: br i1 false, label %bb.preheader, label %return bb.preheader: ; preds = %entry - %tbl.014.us = load i32, i32* null ; [#uses=1] + %tbl.014.us = load i32, ptr null ; [#uses=1] br i1 false, label %cond_next.us, label %bb cond_next51.us: ; preds = %cond_next.us, %cond_true33.us.cond_true46.us_crit_edge - %htblptr.019.1.us = phi %struct.H_TBL** [ %tmp37.us, %cond_true33.us.cond_true46.us_crit_edge ], [ %tmp37.us, %cond_next.us ] ; <%struct.H_TBL**> [#uses=0] + %htblptr.019.1.us = phi ptr [ %tmp37.us, %cond_true33.us.cond_true46.us_crit_edge ], [ %tmp37.us, %cond_next.us ] ; [#uses=0] ret void cond_true33.us.cond_true46.us_crit_edge: ; preds = %cond_next.us @@ -40,9 +40,9 @@ cond_true33.us.cond_true46.us_crit_edge: ; preds = %cond_next.us br label %cond_next51.us cond_next.us: ; preds = %bb.preheader - %tmp37.us = getelementptr %struct.X_Y, %struct.X_Y* %cinfo, i32 0, i32 17, i32 %tbl.014.us ; <%struct.H_TBL**> [#uses=3] - %tmp4524.us = load %struct.H_TBL*, %struct.H_TBL** %tmp37.us ; <%struct.H_TBL*> [#uses=1] - icmp eq %struct.H_TBL* %tmp4524.us, null ; :0 [#uses=1] + %tmp37.us = getelementptr %struct.X_Y, ptr %cinfo, i32 0, i32 17, i32 %tbl.014.us ; [#uses=3] + %tmp4524.us = load ptr, ptr %tmp37.us ; [#uses=1] + icmp eq ptr %tmp4524.us, null ; :0 [#uses=1] br i1 %0, label %cond_true33.us.cond_true46.us_crit_edge, label %cond_next51.us bb: ; preds = %bb.preheader diff --git a/llvm/test/CodeGen/ARM/2007-04-03-PEIBug.ll b/llvm/test/CodeGen/ARM/2007-04-03-PEIBug.ll index 87863bd3ec15d6..d8acdb91be5d8e 100644 --- a/llvm/test/CodeGen/ARM/2007-04-03-PEIBug.ll +++ b/llvm/test/CodeGen/ARM/2007-04-03-PEIBug.ll @@ -2,10 +2,10 @@ define i32 @foo() { entry: - %A = alloca [1123 x i32], align 16 ; <[1123 x i32]*> [#uses=1] - %B = alloca [3123 x i32], align 16 ; <[3123 x i32]*> [#uses=1] - %C = alloca [12312 x i32], align 16 ; <[12312 x i32]*> [#uses=1] - %tmp = call i32 (...) @bar( [3123 x i32]* %B, [1123 x i32]* %A, [12312 x i32]* %C ) ; [#uses=0] + %A = alloca [1123 x i32], align 16 ; [#uses=1] + %B = alloca [3123 x i32], align 16 ; [#uses=1] + %C = alloca [12312 x i32], align 16 ; [#uses=1] + %tmp = call i32 (...) @bar( ptr %B, ptr %A, ptr %C ) ; [#uses=0] ret i32 undef } diff --git a/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll b/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll index 1703bdc0228f4b..e0143e029d086b 100644 --- a/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll +++ b/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll @@ -1,25 +1,23 @@ ; RUN: llc -mtriple arm-apple-darwin -relocation-model pic -filetype asm -o - %s | FileCheck %s %struct.B = type { i32 } -%struct.anon = type { void (%struct.B*)*, i32 } +%struct.anon = type { ptr, i32 } @str = internal constant [7 x i8] c"i, %d\0A\00" @str1 = internal constant [7 x i8] c"j, %d\0A\00" -define internal void @_ZN1B1iEv(%struct.B* %this) { +define internal void @_ZN1B1iEv(ptr %this) { entry: - %tmp1 = getelementptr %struct.B, %struct.B* %this, i32 0, i32 0 - %tmp2 = load i32, i32* %tmp1 - %tmp4 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([7 x i8], [7 x i8]* @str, i32 0, i32 0), i32 %tmp2) + %tmp2 = load i32, ptr %this + %tmp4 = tail call i32 (ptr, ...) @printf(ptr @str, i32 %tmp2) ret void } -declare i32 @printf(i8*, ...) +declare i32 @printf(ptr, ...) -define internal void @_ZN1B1jEv(%struct.B* %this) { +define internal void @_ZN1B1jEv(ptr %this) { entry: - %tmp1 = getelementptr %struct.B, %struct.B* %this, i32 0, i32 0 - %tmp2 = load i32, i32* %tmp1 - %tmp4 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([7 x i8], [7 x i8]* @str1, i32 0, i32 0), i32 %tmp2) + %tmp2 = load i32, ptr %this + %tmp4 = tail call i32 (ptr, ...) @printf(ptr @str1, i32 %tmp2) ret void } @@ -28,72 +26,48 @@ entry: %b.i29 = alloca %struct.B, align 4 %b.i1 = alloca %struct.B, align 4 %b.i = alloca %struct.B, align 4 - %tmp2.i = getelementptr %struct.B, %struct.B* %b.i, i32 0, i32 0 - store i32 4, i32* %tmp2.i - br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit, label %cond_true.i + store i32 4, ptr %b.i + br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit, label %cond_true.i cond_true.i: - %b2.i = bitcast %struct.B* %b.i to i8* - %ctg23.i = getelementptr i8, i8* %b2.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) - %tmp121314.i = bitcast i8* %ctg23.i to i32 (...)*** - %tmp15.i = load i32 (...)**, i32 (...)*** %tmp121314.i - %tmp151.i = bitcast i32 (...)** %tmp15.i to i8* - %ctg2.i = getelementptr i8, i8* %tmp151.i, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) - %tmp2021.i = bitcast i8* %ctg2.i to i32 (...)** - %tmp22.i = load i32 (...)*, i32 (...)** %tmp2021.i - %tmp2223.i = bitcast i32 (...)* %tmp22.i to void (%struct.B*)* + %ctg23.i = getelementptr i8, ptr %b.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) + %tmp15.i = load ptr, ptr %ctg23.i + %ctg2.i = getelementptr i8, ptr %tmp15.i, i32 ptrtoint (ptr @_ZN1B1iEv to i32) + %tmp22.i = load ptr, ptr %ctg2.i br label %_Z3fooiM1BFvvE.exit _Z3fooiM1BFvvE.exit: - %iftmp.2.0.i = phi void (%struct.B*)* [ %tmp2223.i, %cond_true.i ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to void (%struct.B*)*), %entry ] - %b4.i = bitcast %struct.B* %b.i to i8* - %ctg25.i = getelementptr i8, i8* %b4.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) - %tmp3031.i = bitcast i8* %ctg25.i to %struct.B* - call void %iftmp.2.0.i(%struct.B* %tmp3031.i) - %tmp2.i30 = getelementptr %struct.B, %struct.B* %b.i29, i32 0, i32 0 - store i32 6, i32* %tmp2.i30 - br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit56, label %cond_true.i46 + %iftmp.2.0.i = phi ptr [ %tmp22.i, %cond_true.i ], [ inttoptr (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to ptr), %entry ] + %ctg25.i = getelementptr i8, ptr %b.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) + call void %iftmp.2.0.i(ptr %ctg25.i) + store i32 6, ptr %b.i29 + br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (ptr @_ZN1B1jEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit56, label %cond_true.i46 cond_true.i46: - %b2.i35 = bitcast %struct.B* %b.i29 to i8* - %ctg23.i36 = getelementptr i8, i8* %b2.i35, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1) - %tmp121314.i37 = bitcast i8* %ctg23.i36 to i32 (...)*** - %tmp15.i38 = load i32 (...)**, i32 (...)*** %tmp121314.i37 - %tmp151.i41 = bitcast i32 (...)** %tmp15.i38 to i8* - %ctg2.i42 = getelementptr i8, i8* %tmp151.i41, i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) - %tmp2021.i43 = bitcast i8* %ctg2.i42 to i32 (...)** - %tmp22.i44 = load i32 (...)*, i32 (...)** %tmp2021.i43 - %tmp2223.i45 = bitcast i32 (...)* %tmp22.i44 to void (%struct.B*)* + %ctg23.i36 = getelementptr i8, ptr %b.i29, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (ptr @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1) + %tmp15.i38 = load ptr, ptr %ctg23.i36 + %ctg2.i42 = getelementptr i8, ptr %tmp15.i38, i32 ptrtoint (ptr @_ZN1B1jEv to i32) + %tmp22.i44 = load ptr, ptr %ctg2.i42 br label %_Z3fooiM1BFvvE.exit56 _Z3fooiM1BFvvE.exit56: - %iftmp.2.0.i49 = phi void (%struct.B*)* [ %tmp2223.i45, %cond_true.i46 ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to void (%struct.B*)*), %_Z3fooiM1BFvvE.exit ] - %b4.i53 = bitcast %struct.B* %b.i29 to i8* - %ctg25.i54 = getelementptr i8, i8* %b4.i53, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1) - %tmp3031.i55 = bitcast i8* %ctg25.i54 to %struct.B* - call void %iftmp.2.0.i49(%struct.B* %tmp3031.i55) - %tmp2.i2 = getelementptr %struct.B, %struct.B* %b.i1, i32 0, i32 0 - store i32 -1, i32* %tmp2.i2 - br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit28, label %cond_true.i18 + %iftmp.2.0.i49 = phi ptr [ %tmp22.i44, %cond_true.i46 ], [ inttoptr (i32 ptrtoint (ptr @_ZN1B1jEv to i32) to ptr), %_Z3fooiM1BFvvE.exit ] + %ctg25.i54 = getelementptr i8, ptr %b.i29, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (ptr @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1) + call void %iftmp.2.0.i49(ptr %ctg25.i54) + store i32 -1, ptr %b.i1 + br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit28, label %cond_true.i18 cond_true.i18: - %b2.i7 = bitcast %struct.B* %b.i1 to i8* - %ctg23.i8 = getelementptr i8, i8* %b2.i7, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) - %tmp121314.i9 = bitcast i8* %ctg23.i8 to i32 (...)*** - %tmp15.i10 = load i32 (...)**, i32 (...)*** %tmp121314.i9 - %tmp151.i13 = bitcast i32 (...)** %tmp15.i10 to i8* - %ctg2.i14 = getelementptr i8, i8* %tmp151.i13, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) - %tmp2021.i15 = bitcast i8* %ctg2.i14 to i32 (...)** - %tmp22.i16 = load i32 (...)*, i32 (...)** %tmp2021.i15 - %tmp2223.i17 = bitcast i32 (...)* %tmp22.i16 to void (%struct.B*)* + %ctg23.i8 = getelementptr i8, ptr %b.i1, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) + %tmp15.i10 = load ptr, ptr %ctg23.i8 + %ctg2.i14 = getelementptr i8, ptr %tmp15.i10, i32 ptrtoint (ptr @_ZN1B1iEv to i32) + %tmp22.i16 = load ptr, ptr %ctg2.i14 br label %_Z3fooiM1BFvvE.exit28 _Z3fooiM1BFvvE.exit28: - %iftmp.2.0.i21 = phi void (%struct.B*)* [ %tmp2223.i17, %cond_true.i18 ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to void (%struct.B*)*), %_Z3fooiM1BFvvE.exit56 ] - %b4.i25 = bitcast %struct.B* %b.i1 to i8* - %ctg25.i26 = getelementptr i8, i8* %b4.i25, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) - %tmp3031.i27 = bitcast i8* %ctg25.i26 to %struct.B* - call void %iftmp.2.0.i21(%struct.B* %tmp3031.i27) + %iftmp.2.0.i21 = phi ptr [ %tmp22.i16, %cond_true.i18 ], [ inttoptr (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to ptr), %_Z3fooiM1BFvvE.exit56 ] + %ctg25.i26 = getelementptr i8, ptr %b.i1, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) + call void %iftmp.2.0.i21(ptr %ctg25.i26) ret i32 0 } diff --git a/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll b/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll index 05c2ff4f7ca2c0..5e817af8058eef 100644 --- a/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll +++ b/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll @@ -3,21 +3,21 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target triple = "arm-apple-darwin8" %struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 } -@search = external global %struct.CHESS_POSITION ; <%struct.CHESS_POSITION*> [#uses=3] -@file_mask = external global [8 x i64] ; <[8 x i64]*> [#uses=1] -@rank_mask.1.b = external global i1 ; [#uses=1] +@search = external global %struct.CHESS_POSITION ; [#uses=3] +@file_mask = external global [8 x i64] ; [#uses=1] +@rank_mask.1.b = external global i1 ; [#uses=1] define fastcc void @EvaluateDevelopment() { entry: - %tmp7 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 7) ; [#uses=1] - %tmp50 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 0) ; [#uses=1] - %tmp52 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 1) ; [#uses=1] + %tmp7 = load i64, ptr getelementptr (%struct.CHESS_POSITION, ptr @search, i32 0, i32 7) ; [#uses=1] + %tmp50 = load i64, ptr @search ; [#uses=1] + %tmp52 = load i64, ptr getelementptr (%struct.CHESS_POSITION, ptr @search, i32 0, i32 1) ; [#uses=1] %tmp53 = or i64 %tmp52, %tmp50 ; [#uses=1] - %tmp57.b = load i1, i1* @rank_mask.1.b ; [#uses=1] + %tmp57.b = load i1, ptr @rank_mask.1.b ; [#uses=1] %tmp57 = select i1 %tmp57.b, i64 71776119061217280, i64 0 ; [#uses=1] %tmp58 = and i64 %tmp57, %tmp7 ; [#uses=1] %tmp59 = lshr i64 %tmp58, 8 ; [#uses=1] - %tmp63 = load i64, i64* getelementptr ([8 x i64], [8 x i64]* @file_mask, i32 0, i32 4) ; [#uses=1] + %tmp63 = load i64, ptr getelementptr ([8 x i64], ptr @file_mask, i32 0, i32 4) ; [#uses=1] %tmp64 = or i64 %tmp63, 0 ; [#uses=1] %tmp65 = and i64 %tmp59, %tmp53 ; [#uses=1] %tmp66 = and i64 %tmp65, %tmp64 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll b/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll index 50573b457c3775..fc349bfb8c8e00 100644 --- a/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll +++ b/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll @@ -1,20 +1,20 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin %struct.Connection = type { i32, [10 x i8], i32 } - %struct.IntChunk = type { %struct.cppobjtype, i32, i32*, i32 } - %struct.Point = type { i8*, %struct.cppobjtype, i16 (%struct.Point*) *, i16 (%struct.Point*) *, double (%struct.Point*)*, double (%struct.Point*)* } - %struct.RefPoint = type { %struct.Point*, %struct.cppobjtype } - %struct.ShortArray = type { %struct.cppobjtype, i32, i16* } - %struct.TestObj = type { i8*, %struct.cppobjtype, i8, [32 x i8], i8*, i8**, i16, i16, i32, i32, i32, i32, float, double, %struct.cppobjtype, i32, i16*, i16**, i8**, i32, %struct.XyPoint, [3 x %struct.Connection], %struct.Point*, %struct.XyPoint*, i32, i8*, i8*, i16*, %struct.ShortArray, %struct.IntChunk, %struct.cppobjtype, %struct.cppobjtype, %struct.RefPoint, i32, %struct.cppobjtype, %struct.cppobjtype } + %struct.IntChunk = type { %struct.cppobjtype, i32, ptr, i32 } + %struct.Point = type { ptr, %struct.cppobjtype, ptr, ptr, ptr, ptr } + %struct.RefPoint = type { ptr, %struct.cppobjtype } + %struct.ShortArray = type { %struct.cppobjtype, i32, ptr } + %struct.TestObj = type { ptr, %struct.cppobjtype, i8, [32 x i8], ptr, ptr, i16, i16, i32, i32, i32, i32, float, double, %struct.cppobjtype, i32, ptr, ptr, ptr, i32, %struct.XyPoint, [3 x %struct.Connection], ptr, ptr, i32, ptr, ptr, ptr, %struct.ShortArray, %struct.IntChunk, %struct.cppobjtype, %struct.cppobjtype, %struct.RefPoint, i32, %struct.cppobjtype, %struct.cppobjtype } %struct.XyPoint = type { i16, i16 } %struct.cppobjtype = type { i32, i16, i16 } -@Msg = external global [256 x i8] ; <[256 x i8]*> [#uses=1] -@.str53615 = external constant [48 x i8] ; <[48 x i8]*> [#uses=1] -@FirstTime.4637.b = external global i1 ; [#uses=1] +@Msg = external global [256 x i8] ; [#uses=1] +@.str53615 = external constant [48 x i8] ; [#uses=1] +@FirstTime.4637.b = external global i1 ; [#uses=1] -define fastcc void @Draw7(i32 %Option, i32* %Status) { +define fastcc void @Draw7(i32 %Option, ptr %Status) { entry: - %tmp115.b = load i1, i1* @FirstTime.4637.b ; [#uses=1] + %tmp115.b = load i1, ptr @FirstTime.4637.b ; [#uses=1] br i1 %tmp115.b, label %cond_next239, label %cond_next.i cond_next.i: ; preds = %entry @@ -88,19 +88,19 @@ cond_next1267: ; preds = %cond_next1235 br i1 %tmp1148, label %cond_next1275, label %cond_true1272 cond_true1272: ; preds = %cond_next1267 - %tmp1273 = load %struct.TestObj*, %struct.TestObj** null ; <%struct.TestObj*> [#uses=2] - %tmp2930.i = ptrtoint %struct.TestObj* %tmp1273 to i32 ; [#uses=1] + %tmp1273 = load ptr, ptr null ; [#uses=2] + %tmp2930.i = ptrtoint ptr %tmp1273 to i32 ; [#uses=1] %tmp42.i348 = sub i32 0, %tmp2930.i ; [#uses=1] - %tmp45.i = getelementptr %struct.TestObj, %struct.TestObj* %tmp1273, i32 0, i32 0 ; [#uses=2] - %tmp48.i = load i8*, i8** %tmp45.i ; [#uses=1] - %tmp50.i350 = call i32 (i8*, i8*, ...) @sprintf( i8* getelementptr ([256 x i8], [256 x i8]* @Msg, i32 0, i32 0), i8* getelementptr ([48 x i8], [48 x i8]* @.str53615, i32 0, i32 0), i8* null, i8** %tmp45.i, i8* %tmp48.i ) ; [#uses=0] + %tmp45.i = getelementptr %struct.TestObj, ptr %tmp1273, i32 0, i32 0 ; [#uses=2] + %tmp48.i = load ptr, ptr %tmp45.i ; [#uses=1] + %tmp50.i350 = call i32 (ptr, ptr, ...) @sprintf( ptr @Msg, ptr @.str53615, ptr null, ptr %tmp45.i, ptr %tmp48.i ) ; [#uses=0] br i1 false, label %cond_true.i632.i, label %Ut_TraceMsg.exit648.i cond_true.i632.i: ; preds = %cond_true1272 ret void Ut_TraceMsg.exit648.i: ; preds = %cond_true1272 - %tmp57.i = getelementptr i8, i8* null, i32 %tmp42.i348 ; [#uses=0] + %tmp57.i = getelementptr i8, ptr null, i32 %tmp42.i348 ; [#uses=0] ret void cond_next1275: ; preds = %cond_next1267 @@ -110,4 +110,4 @@ bb1326: ; preds = %cond_next315, %cond_next253 ret void } -declare i32 @sprintf(i8*, i8*, ...) +declare i32 @sprintf(ptr, ptr, ...) diff --git a/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll b/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll index f49c805469a04a..ac50bdfaf78cec 100644 --- a/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll +++ b/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll @@ -12,12 +12,12 @@ target triple = "arm-apple-darwin8" define i32 @f(i32 %i, i32 %q) { entry: - %i_addr = alloca i32 ; [#uses=2] - %q_addr = alloca i32 ; [#uses=2] - %retval = alloca i32, align 4 ; [#uses=1] - store i32 %i, i32* %i_addr - store i32 %q, i32* %q_addr - %tmp = load i32, i32* %i_addr ; [#uses=1] + %i_addr = alloca i32 ; [#uses=2] + %q_addr = alloca i32 ; [#uses=2] + %retval = alloca i32, align 4 ; [#uses=1] + store i32 %i, ptr %i_addr + store i32 %q, ptr %q_addr + %tmp = load i32, ptr %i_addr ; [#uses=1] %tmp1 = icmp ne i32 %tmp, 0 ; [#uses=1] %tmp12 = zext i1 %tmp1 to i8 ; [#uses=1] %toBool = icmp ne i8 %tmp12, 0 ; [#uses=1] @@ -34,7 +34,7 @@ cond_false: ; preds = %entry br label %cond_next cond_next: ; preds = %cond_false, %cond_true - %tmp7 = load i32, i32* %q_addr ; [#uses=1] + %tmp7 = load i32, ptr %q_addr ; [#uses=1] %tmp8 = icmp ne i32 %tmp7, 0 ; [#uses=1] %tmp89 = zext i1 %tmp8 to i8 ; [#uses=1] %toBool10 = icmp ne i8 %tmp89, 0 ; [#uses=1] @@ -55,7 +55,7 @@ cond_next18: ; preds = %cond_false15, %cond_true11 br label %return return: ; preds = %cond_next18 - %retval20 = load i32, i32* %retval ; [#uses=1] + %retval20 = load i32, ptr %retval ; [#uses=1] ret i32 %retval20 } diff --git a/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll b/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll index 21e2169aca335d..f9804c204c59c2 100644 --- a/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll +++ b/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll @@ -14,12 +14,12 @@ target triple = "arm-apple-darwin8" define i32 @f(i32 %i, i32 %q) { entry: - %i_addr = alloca i32 ; [#uses=2] - %q_addr = alloca i32 ; [#uses=2] - %retval = alloca i32, align 4 ; [#uses=1] - store i32 %i, i32* %i_addr - store i32 %q, i32* %q_addr - %tmp = load i32, i32* %i_addr ; [#uses=1] + %i_addr = alloca i32 ; [#uses=2] + %q_addr = alloca i32 ; [#uses=2] + %retval = alloca i32, align 4 ; [#uses=1] + store i32 %i, ptr %i_addr + store i32 %q, ptr %q_addr + %tmp = load i32, ptr %i_addr ; [#uses=1] %tmp1 = icmp ne i32 %tmp, 0 ; [#uses=1] %tmp12 = zext i1 %tmp1 to i8 ; [#uses=1] %toBool = icmp ne i8 %tmp12, 0 ; [#uses=1] @@ -28,7 +28,7 @@ entry: cond_true: ; preds = %entry %tmp3 = call i32 (...) @bar( ) ; [#uses=0] %tmp4 = call i32 (...) @baz( i32 5, i32 6 ) ; [#uses=0] - %tmp7 = load i32, i32* %q_addr ; [#uses=1] + %tmp7 = load i32, ptr %q_addr ; [#uses=1] %tmp8 = icmp ne i32 %tmp7, 0 ; [#uses=1] %tmp89 = zext i1 %tmp8 to i8 ; [#uses=1] %toBool10 = icmp ne i8 %tmp89, 0 ; [#uses=1] @@ -37,7 +37,7 @@ cond_true: ; preds = %entry cond_false: ; preds = %entry %tmp5 = call i32 (...) @foo( ) ; [#uses=0] %tmp6 = call i32 (...) @baz( i32 5, i32 6 ) ; [#uses=0] - %tmp27 = load i32, i32* %q_addr ; [#uses=1] + %tmp27 = load i32, ptr %q_addr ; [#uses=1] %tmp28 = icmp ne i32 %tmp27, 0 ; [#uses=1] %tmp289 = zext i1 %tmp28 to i8 ; [#uses=1] %toBool210 = icmp ne i8 %tmp289, 0 ; [#uses=1] @@ -58,7 +58,7 @@ cond_next18: ; preds = %cond_false15, %cond_true11 br label %return return: ; preds = %cond_next18 - %retval20 = load i32, i32* %retval ; [#uses=1] + %retval20 = load i32, ptr %retval ; [#uses=1] ret i32 %retval20 } diff --git a/llvm/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll index 78e132e1ecce40..18510c4343aa58 100644 --- a/llvm/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll @@ -1,17 +1,17 @@ ; RUN: llc < %s -mtriple=arm-linux-gnueabi ; PR1406 - %struct.AVClass = type { i8*, i8* (i8*)*, %struct.AVOption* } - %struct.AVCodec = type { i8*, i32, i32, i32, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32, i8*)*, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32*, i8*, i32)*, i32, %struct.AVCodec*, void (%struct.AVCodecContext*)*, %struct.AVRational*, i32* } - %struct.AVCodecContext = type { %struct.AVClass*, i32, i32, i32, i32, i32, i8*, i32, %struct.AVRational, i32, i32, i32, i32, i32, void (%struct.AVCodecContext*, %struct.AVFrame*, i32*, i32, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, float, float, i32, i32, i32, i32, float, i32, i32, i32, %struct.AVCodec*, i8*, i32, i32, void (%struct.AVCodecContext*, i8*, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, [32 x i8], i32, i32, i32, i32, i32, i32, i32, float, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, void (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i8*, i8*, float, float, i32, %struct.RcOverride*, i32, i8*, i32, i32, i32, float, float, float, float, i32, float, float, float, float, float, i32, i32, i32, i32*, i32, i32, i32, i32, %struct.AVRational, %struct.AVFrame*, i32, i32, [4 x i64], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32*)*, i32, i32, i32, i32, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i16*, i16*, i32, i32, i32, i32, %struct.AVPaletteControl*, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32 (%struct.AVCodecContext*, i8*)*, i8**, i32*, i32)*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64 } - %struct.AVFrame = type { [4 x i8*], [4 x i32], [4 x i8*], i32, i32, i64, i32, i32, i32, i32, i32, i8*, i32, i8*, [2 x [2 x i16]*], i32*, i8, i8*, [4 x i64], i32, i32, i32, i32, i32, %struct.AVPanScan*, i32, i32, i16*, [2 x i8*] } + %struct.AVClass = type { ptr, ptr, ptr } + %struct.AVCodec = type { ptr, i32, i32, i32, ptr, ptr, ptr, ptr, i32, ptr, ptr, ptr, ptr } + %struct.AVCodecContext = type { ptr, i32, i32, i32, i32, i32, ptr, i32, %struct.AVRational, i32, i32, i32, i32, i32, ptr, i32, i32, i32, i32, i32, i32, i32, float, float, i32, i32, i32, i32, float, i32, i32, i32, ptr, ptr, i32, i32, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, [32 x i8], i32, i32, i32, i32, i32, i32, i32, float, i32, ptr, ptr, i32, i32, i32, i32, ptr, ptr, float, float, i32, ptr, i32, ptr, i32, i32, i32, float, float, float, float, i32, float, float, float, float, float, i32, i32, i32, ptr, i32, i32, i32, i32, %struct.AVRational, ptr, i32, i32, [4 x i64], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, i32, i32, i32, i32, i32, i32, ptr, i32, i32, i32, i32, i32, i32, ptr, ptr, i32, i32, i32, i32, ptr, i32, ptr, i32, i32, i32, i32, i32, i32, i32, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64 } + %struct.AVFrame = type { [4 x ptr], [4 x i32], [4 x ptr], i32, i32, i64, i32, i32, i32, i32, i32, ptr, i32, ptr, [2 x ptr], ptr, i8, ptr, [4 x i64], i32, i32, i32, i32, i32, ptr, i32, i32, ptr, [2 x ptr] } %struct.AVOption = type opaque %struct.AVPaletteControl = type { i32, [256 x i32] } %struct.AVPanScan = type { i32, i32, i32, [3 x [2 x i16]] } %struct.AVRational = type { i32, i32 } %struct.RcOverride = type { i32, i32, i32, float } -define i32 @decode_init(%struct.AVCodecContext* %avctx) { +define i32 @decode_init(ptr %avctx) { entry: br i1 false, label %bb, label %cond_next789 @@ -21,8 +21,8 @@ bb: ; preds = %bb, %entry bb59: ; preds = %bb %tmp68 = sdiv i64 0, 0 ; [#uses=1] %tmp6869 = trunc i64 %tmp68 to i32 ; [#uses=2] - %tmp81 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, $1, lsl $5\0A\09", "=&r,=*&r,r,r,i,i"( i32* elementtype( i32) null, i32 %tmp6869, i32 13316085, i32 23, i32 9 ) ; [#uses=0] - %tmp90 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, $1, lsl $5\0A\09", "=&r,=*&r,r,r,i,i"( i32* elementtype( i32) null, i32 %tmp6869, i32 10568984, i32 23, i32 9 ) ; [#uses=0] + %tmp81 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, $1, lsl $5\0A\09", "=&r,=*&r,r,r,i,i"( ptr elementtype( i32) null, i32 %tmp6869, i32 13316085, i32 23, i32 9 ) ; [#uses=0] + %tmp90 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, $1, lsl $5\0A\09", "=&r,=*&r,r,r,i,i"( ptr elementtype( i32) null, i32 %tmp6869, i32 10568984, i32 23, i32 9 ) ; [#uses=0] unreachable cond_next789: ; preds = %entry diff --git a/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll b/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll index 7669a03c969a35..7fa6dd3ebec3a4 100644 --- a/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll +++ b/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll @@ -23,12 +23,12 @@ target triple = "arm-apple-darwin8" define i32 @f(i32 %i, i32 %q) { entry: - %i_addr = alloca i32 ; [#uses=2] - %q_addr = alloca i32 ; [#uses=2] - %retval = alloca i32, align 4 ; [#uses=1] - store i32 %i, i32* %i_addr - store i32 %q, i32* %q_addr - %tmp = load i32, i32* %i_addr ; [#uses=1] + %i_addr = alloca i32 ; [#uses=2] + %q_addr = alloca i32 ; [#uses=2] + %retval = alloca i32, align 4 ; [#uses=1] + store i32 %i, ptr %i_addr + store i32 %q, ptr %q_addr + %tmp = load i32, ptr %i_addr ; [#uses=1] %tmp1 = icmp ne i32 %tmp, 0 ; [#uses=1] %tmp12 = zext i1 %tmp1 to i8 ; [#uses=1] %toBool = icmp ne i8 %tmp12, 0 ; [#uses=1] @@ -37,7 +37,7 @@ entry: cond_true: ; preds = %entry %tmp3 = call i32 (...) @bar( ) ; [#uses=0] %tmp4 = call i32 (...) @baz( i32 5, i32 6 ) ; [#uses=0] - %tmp7 = load i32, i32* %q_addr ; [#uses=1] + %tmp7 = load i32, ptr %q_addr ; [#uses=1] %tmp8 = icmp ne i32 %tmp7, 0 ; [#uses=1] %tmp89 = zext i1 %tmp8 to i8 ; [#uses=1] %toBool10 = icmp ne i8 %tmp89, 0 ; [#uses=1] @@ -46,7 +46,7 @@ cond_true: ; preds = %entry cond_false: ; preds = %entry %tmp5 = call i32 (...) @foo( ) ; [#uses=0] %tmp6 = call i32 (...) @baz( i32 5, i32 6 ) ; [#uses=0] - %tmp27 = load i32, i32* %q_addr ; [#uses=1] + %tmp27 = load i32, ptr %q_addr ; [#uses=1] %tmp28 = icmp ne i32 %tmp27, 0 ; [#uses=1] %tmp289 = zext i1 %tmp28 to i8 ; [#uses=1] %toBool210 = icmp ne i8 %tmp289, 0 ; [#uses=1] @@ -67,7 +67,7 @@ cond_next18: ; preds = %cond_false15, %cond_true11 br label %return return: ; preds = %cond_next18 - %retval20 = load i32, i32* %retval ; [#uses=1] + %retval20 = load i32, ptr %retval ; [#uses=1] ret i32 %retval20 } diff --git a/llvm/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll b/llvm/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll index e0b28e874b9007..0b5f2cd39dae79 100644 --- a/llvm/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll +++ b/llvm/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll @@ -1,15 +1,15 @@ ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s - %struct.shape_edge_t = type { %struct.shape_edge_t*, %struct.shape_edge_t*, i32, i32, i32, i32 } - %struct.shape_path_t = type { %struct.shape_edge_t*, %struct.shape_edge_t*, i32, i32, i32, i32, i32, i32 } - %struct.shape_pool_t = type { i8* (%struct.shape_pool_t*, i8*, i32)*, i8* (%struct.shape_pool_t*, i32)*, void (%struct.shape_pool_t*, i8*)* } + %struct.shape_edge_t = type { ptr, ptr, i32, i32, i32, i32 } + %struct.shape_path_t = type { ptr, ptr, i32, i32, i32, i32, i32, i32 } + %struct.shape_pool_t = type { ptr, ptr, ptr } -define %struct.shape_path_t* @shape_path_alloc(%struct.shape_pool_t* %pool, i32* %shape) { +define ptr @shape_path_alloc(ptr %pool, ptr %shape) { entry: br i1 false, label %cond_false, label %bb45 bb45: ; preds = %entry - ret %struct.shape_path_t* null + ret ptr null cond_false: ; preds = %entry br i1 false, label %bb140, label %bb174 @@ -17,12 +17,12 @@ cond_false: ; preds = %entry bb140: ; preds = %bb140, %cond_false %indvar = phi i32 [ 0, %cond_false ], [ %indvar.next, %bb140 ] ; [#uses=2] %edge.230.0.rec = shl i32 %indvar, 1 ; [#uses=3] - %edge.230.0 = getelementptr %struct.shape_edge_t, %struct.shape_edge_t* null, i32 %edge.230.0.rec ; <%struct.shape_edge_t*> [#uses=1] + %edge.230.0 = getelementptr %struct.shape_edge_t, ptr null, i32 %edge.230.0.rec ; [#uses=1] %edge.230.0.sum6970 = or i32 %edge.230.0.rec, 1 ; [#uses=2] - %tmp154 = getelementptr %struct.shape_edge_t, %struct.shape_edge_t* null, i32 %edge.230.0.sum6970 ; <%struct.shape_edge_t*> [#uses=1] - %tmp11.i5 = getelementptr %struct.shape_edge_t, %struct.shape_edge_t* null, i32 %edge.230.0.sum6970, i32 0 ; <%struct.shape_edge_t**> [#uses=1] - store %struct.shape_edge_t* %edge.230.0, %struct.shape_edge_t** %tmp11.i5 - store %struct.shape_edge_t* %tmp154, %struct.shape_edge_t** null + %tmp154 = getelementptr %struct.shape_edge_t, ptr null, i32 %edge.230.0.sum6970 ; [#uses=1] + %tmp11.i5 = getelementptr %struct.shape_edge_t, ptr null, i32 %edge.230.0.sum6970, i32 0 ; [#uses=1] + store ptr %edge.230.0, ptr %tmp11.i5 + store ptr %tmp154, ptr null %tmp16254.0.rec = add i32 %edge.230.0.rec, 2 ; [#uses=1] %xp.350.sum = add i32 0, %tmp16254.0.rec ; [#uses=1] %tmp168 = icmp slt i32 %xp.350.sum, 0 ; [#uses=1] @@ -30,7 +30,7 @@ bb140: ; preds = %bb140, %cond_false br i1 %tmp168, label %bb140, label %bb174 bb174: ; preds = %bb140, %cond_false - ret %struct.shape_path_t* null + ret ptr null } ; CHECK-NOT: str{{.*}}! diff --git a/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll b/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll index 76b6221d022290..547bb72d91cc0b 100644 --- a/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll +++ b/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll @@ -1,14 +1,14 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -mattr=+v6 ; PR1609 - %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } + %struct.FILE = type { ptr, i32, i32, i16, i16, %struct.__sbuf, i32, ptr, ptr, ptr, ptr, ptr, %struct.__sbuf, ptr, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } %struct.__sFILEX = type opaque - %struct.__sbuf = type { i8*, i32 } -@_C_nextcmd = external global i32 ; [#uses=2] -@_C_cmds = external global [100 x i8*] ; <[100 x i8*]*> [#uses=2] -@.str44 = external constant [2 x i8] ; <[2 x i8]*> [#uses=1] + %struct.__sbuf = type { ptr, i32 } +@_C_nextcmd = external global i32 ; [#uses=2] +@_C_cmds = external global [100 x ptr] ; [#uses=2] +@.str44 = external constant [2 x i8] ; [#uses=1] -define i32 @main(i32 %argc, i8** %argv) { +define i32 @main(i32 %argc, ptr %argv) { entry: br label %cond_next212.i @@ -44,27 +44,27 @@ bb102.i: ; preds = %cond_next212.i br i1 false, label %cond_true110.i, label %cond_next123.i cond_true110.i: ; preds = %bb102.i - %tmp116.i = getelementptr i8*, i8** %argv_addr.2321.0.i, i32 2 ; [#uses=1] - %tmp117.i = load i8*, i8** %tmp116.i ; [#uses=1] - %tmp126425.i = call %struct.FILE* @fopen( i8* %tmp117.i, i8* getelementptr ([2 x i8], [2 x i8]* @.str44, i32 0, i32 0) ) ; <%struct.FILE*> [#uses=0] + %tmp116.i = getelementptr ptr, ptr %argv_addr.2321.0.i, i32 2 ; [#uses=1] + %tmp117.i = load ptr, ptr %tmp116.i ; [#uses=1] + %tmp126425.i = call ptr @fopen( ptr %tmp117.i, ptr @.str44 ) ; [#uses=0] ret i32 0 cond_next123.i: ; preds = %bb102.i - %tmp122.i = getelementptr i8, i8* %tmp215.i, i32 2 ; [#uses=0] + %tmp122.i = getelementptr i8, ptr %tmp215.i, i32 2 ; [#uses=0] ret i32 0 bb162.i: ; preds = %cond_next212.i ret i32 0 C_addcmd.exit120.i: ; preds = %cond_next212.i - %tmp3.i.i.i.i105.i = call i8* @calloc( i32 15, i32 1 ) ; [#uses=1] - %tmp1.i108.i = getelementptr [100 x i8*], [100 x i8*]* @_C_cmds, i32 0, i32 0 ; [#uses=1] - store i8* %tmp3.i.i.i.i105.i, i8** %tmp1.i108.i, align 4 - %tmp.i91.i = load i32, i32* @_C_nextcmd, align 4 ; [#uses=1] - store i32 0, i32* @_C_nextcmd, align 4 - %tmp3.i.i.i.i95.i = call i8* @calloc( i32 15, i32 1 ) ; [#uses=1] - %tmp1.i98.i = getelementptr [100 x i8*], [100 x i8*]* @_C_cmds, i32 0, i32 %tmp.i91.i ; [#uses=1] - store i8* %tmp3.i.i.i.i95.i, i8** %tmp1.i98.i, align 4 + %tmp3.i.i.i.i105.i = call ptr @calloc( i32 15, i32 1 ) ; [#uses=1] + %tmp1.i108.i = getelementptr [100 x ptr], ptr @_C_cmds, i32 0, i32 0 ; [#uses=1] + store ptr %tmp3.i.i.i.i105.i, ptr %tmp1.i108.i, align 4 + %tmp.i91.i = load i32, ptr @_C_nextcmd, align 4 ; [#uses=1] + store i32 0, ptr @_C_nextcmd, align 4 + %tmp3.i.i.i.i95.i = call ptr @calloc( i32 15, i32 1 ) ; [#uses=1] + %tmp1.i98.i = getelementptr [100 x ptr], ptr @_C_cmds, i32 0, i32 %tmp.i91.i ; [#uses=1] + store ptr %tmp3.i.i.i.i95.i, ptr %tmp1.i98.i, align 4 br label %cond_next212.i bb174.i: ; preds = %cond_next212.i @@ -75,10 +75,10 @@ bb192.i: ; preds = %cond_next212.i cond_next212.i: ; preds = %cond_next212.i, %cond_next212.i, %cond_next212.i, %cond_next212.i, %bb192.i, %C_addcmd.exit120.i, %bb30.i, %bb21.i, %entry %max_d.3 = phi i32 [ -1, %entry ], [ %max_d.3, %bb30.i ], [ %max_d.3, %bb21.i ], [ %max_d.3, %C_addcmd.exit120.i ], [ 0, %bb192.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ] ; [#uses=7] - %argv_addr.2321.0.i = phi i8** [ %argv, %entry ], [ %tmp214.i, %bb192.i ], [ %tmp214.i, %C_addcmd.exit120.i ], [ %tmp214.i, %bb30.i ], [ %tmp214.i, %bb21.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ] ; [#uses=2] + %argv_addr.2321.0.i = phi ptr [ %argv, %entry ], [ %tmp214.i, %bb192.i ], [ %tmp214.i, %C_addcmd.exit120.i ], [ %tmp214.i, %bb30.i ], [ %tmp214.i, %bb21.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ] ; [#uses=2] %argc_addr.2358.0.i = phi i32 [ %argc, %entry ], [ %tmp205399.i, %bb30.i ], [ 0, %bb21.i ], [ 0, %C_addcmd.exit120.i ], [ 0, %bb192.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ] ; [#uses=1] - %tmp214.i = getelementptr i8*, i8** %argv_addr.2321.0.i, i32 1 ; [#uses=9] - %tmp215.i = load i8*, i8** %tmp214.i ; [#uses=1] + %tmp214.i = getelementptr ptr, ptr %argv_addr.2321.0.i, i32 1 ; [#uses=9] + %tmp215.i = load ptr, ptr %tmp214.i ; [#uses=1] %tmp1314.i = sext i8 0 to i32 ; [#uses=1] switch i32 %tmp1314.i, label %bb192.i [ i32 76, label %C_addcmd.exit120.i @@ -101,6 +101,6 @@ cond_next212.i: ; preds = %cond_next212.i, %cond_next212.i, %cond_next212.i, %c ] } -declare %struct.FILE* @fopen(i8*, i8*) +declare ptr @fopen(ptr, ptr) -declare i8* @calloc(i32, i32) +declare ptr @calloc(i32, i32) diff --git a/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll b/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll index 989410552f3f0a..4d9b7c6891d720 100644 --- a/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll +++ b/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll @@ -1,19 +1,19 @@ ; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=fast -optimize-regalloc=0 ; PR1925 - %struct.encode_aux_nearestmatch = type { i32*, i32*, i32*, i32*, i32, i32 } - %struct.encode_aux_pigeonhole = type { float, float, i32, i32, i32*, i32, i32*, i32*, i32* } - %struct.encode_aux_threshmatch = type { float*, i32*, i32, i32 } - %struct.oggpack_buffer = type { i32, i32, i8*, i8*, i32 } - %struct.static_codebook = type { i32, i32, i32*, i32, i32, i32, i32, i32, i32*, %struct.encode_aux_nearestmatch*, %struct.encode_aux_threshmatch*, %struct.encode_aux_pigeonhole*, i32 } + %struct.encode_aux_nearestmatch = type { ptr, ptr, ptr, ptr, i32, i32 } + %struct.encode_aux_pigeonhole = type { float, float, i32, i32, ptr, i32, ptr, ptr, ptr } + %struct.encode_aux_threshmatch = type { ptr, ptr, i32, i32 } + %struct.oggpack_buffer = type { i32, i32, ptr, ptr, i32 } + %struct.static_codebook = type { i32, i32, ptr, i32, i32, i32, i32, i32, ptr, ptr, ptr, ptr, i32 } -define i32 @vorbis_staticbook_pack(%struct.static_codebook* %c, %struct.oggpack_buffer* %opb) { +define i32 @vorbis_staticbook_pack(ptr %c, ptr %opb) { entry: - %opb_addr = alloca %struct.oggpack_buffer* ; <%struct.oggpack_buffer**> [#uses=1] - %tmp1 = load %struct.oggpack_buffer*, %struct.oggpack_buffer** %opb_addr, align 4 ; <%struct.oggpack_buffer*> [#uses=1] - call void @oggpack_write( %struct.oggpack_buffer* %tmp1, i32 5653314, i32 24 ) nounwind - call void @oggpack_write( %struct.oggpack_buffer* null, i32 0, i32 24 ) nounwind + %opb_addr = alloca ptr ; [#uses=1] + %tmp1 = load ptr, ptr %opb_addr, align 4 ; [#uses=1] + call void @oggpack_write( ptr %tmp1, i32 5653314, i32 24 ) nounwind + call void @oggpack_write( ptr null, i32 0, i32 24 ) nounwind unreachable } -declare void @oggpack_write(%struct.oggpack_buffer*, i32, i32) +declare void @oggpack_write(ptr, i32, i32) diff --git a/llvm/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll b/llvm/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll index 03b473a4658a6e..d22a3e53b3c899 100644 --- a/llvm/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll +++ b/llvm/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll @@ -2,20 +2,20 @@ ; PR1925 %"struct.kc::impl_Ccode_option" = type { %"struct.kc::impl_abstract_phylum" } - %"struct.kc::impl_ID" = type { %"struct.kc::impl_abstract_phylum", %"struct.kc::impl_Ccode_option"*, %"struct.kc::impl_casestring__Str"*, i32, %"struct.kc::impl_casestring__Str"* } - %"struct.kc::impl_abstract_phylum" = type { i32 (...)** } - %"struct.kc::impl_casestring__Str" = type { %"struct.kc::impl_abstract_phylum", i8* } + %"struct.kc::impl_ID" = type { %"struct.kc::impl_abstract_phylum", ptr, ptr, i32, ptr } + %"struct.kc::impl_abstract_phylum" = type { ptr } + %"struct.kc::impl_casestring__Str" = type { %"struct.kc::impl_abstract_phylum", ptr } -define %"struct.kc::impl_ID"* @_ZN2kc18f_typeofunpsubtermEPNS_15impl_unpsubtermEPNS_7impl_IDE(%"struct.kc::impl_Ccode_option"* %a_unpsubterm, %"struct.kc::impl_ID"* %a_operator) { +define ptr @_ZN2kc18f_typeofunpsubtermEPNS_15impl_unpsubtermEPNS_7impl_IDE(ptr %a_unpsubterm, ptr %a_operator) { entry: - %tmp8 = getelementptr %"struct.kc::impl_Ccode_option", %"struct.kc::impl_Ccode_option"* %a_unpsubterm, i32 0, i32 0, i32 0 ; [#uses=0] + %tmp8 = getelementptr %"struct.kc::impl_Ccode_option", ptr %a_unpsubterm, i32 0, i32 0, i32 0 ; [#uses=0] br i1 false, label %bb41, label %bb55 bb41: ; preds = %entry - ret %"struct.kc::impl_ID"* null + ret ptr null bb55: ; preds = %entry - %tmp67 = tail call i32 null( %"struct.kc::impl_abstract_phylum"* null ) ; [#uses=0] - %tmp97 = tail call i32 null( %"struct.kc::impl_abstract_phylum"* null ) ; [#uses=0] - ret %"struct.kc::impl_ID"* null + %tmp67 = tail call i32 null( ptr null ) ; [#uses=0] + %tmp97 = tail call i32 null( ptr null ) ; [#uses=0] + ret ptr null } diff --git a/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll b/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll index b0a50a49a76d3f..04f4e6945c0dff 100644 --- a/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll +++ b/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll @@ -1,10 +1,10 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s -define i32 @main(i32 %argc, i8** %argv) { +define i32 @main(i32 %argc, ptr %argv) { entry: br label %bb1 bb1: ; preds = %entry - %tmp3.i.i = load i8, i8* null, align 1 ; [#uses=1] + %tmp3.i.i = load i8, ptr null, align 1 ; [#uses=1] %tmp4.i.i = icmp slt i8 %tmp3.i.i, 0 ; [#uses=1] br i1 %tmp4.i.i, label %bb2, label %bb3 bb2: ; preds = %bb1 diff --git a/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll index 753f9e3d1331cb..80812a395995c5 100644 --- a/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 -@accum = external global { double, double } ; <{ double, double }*> [#uses=1] -@.str = external constant [4 x i8] ; <[4 x i8]*> [#uses=1] +@accum = external global { double, double } ; [#uses=1] +@.str = external constant [4 x i8] ; [#uses=1] define i32 @main() { entry: @@ -11,10 +11,10 @@ bb74.i: ; preds = %bb88.i, %bb74.i, %entry bb88.i: ; preds = %bb74.i br i1 false, label %mandel.exit, label %bb74.i mandel.exit: ; preds = %bb88.i - %tmp2 = load volatile double, double* getelementptr ({ double, double }, { double, double }* @accum, i32 0, i32 0), align 8 ; [#uses=1] + %tmp2 = load volatile double, ptr getelementptr ({ double, double }, ptr @accum, i32 0, i32 0), align 8 ; [#uses=1] %tmp23 = fptosi double %tmp2 to i32 ; [#uses=1] - %tmp5 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %tmp23 ) ; [#uses=0] + %tmp5 = tail call i32 (ptr, ...) @printf( ptr @.str, i32 %tmp23 ) ; [#uses=0] ret i32 0 } -declare i32 @printf(i8*, ...) +declare i32 @printf(ptr, ...) diff --git a/llvm/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll index 4b1aa19ef06733..02e1cee13448e6 100644 --- a/llvm/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll @@ -1,10 +1,10 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -@numBinsY = external global i32 ; [#uses=1] +@numBinsY = external global i32 ; [#uses=1] declare double @pow(double, double) -define void @main(i32 %argc, i8** %argv) noreturn nounwind { +define void @main(i32 %argc, ptr %argv) noreturn nounwind { entry: br i1 false, label %bb34.outer.i.i.i, label %cond_false674 bb34.outer.i.i.i: ; preds = %entry @@ -25,18 +25,18 @@ bb248.i.i.i: ; preds = %bb220.i.i.i cond_false256.i.i.i: ; preds = %bb248.i.i.i ret void bb300.i.i.i: ; preds = %bb248.i.i.i - store i32 undef, i32* @numBinsY, align 4 + store i32 undef, ptr @numBinsY, align 4 ret void cond_false674: ; preds = %entry ret void } - %struct.anon = type { %struct.rnode*, %struct.rnode* } - %struct.ch_set = type { { i8, i8 }*, %struct.ch_set* } - %struct.pat_list = type { i32, %struct.pat_list* } - %struct.rnode = type { i16, { %struct.anon }, i16, %struct.pat_list*, %struct.pat_list* } + %struct.anon = type { ptr, ptr } + %struct.ch_set = type { ptr, ptr } + %struct.pat_list = type { i32, ptr } + %struct.rnode = type { i16, { %struct.anon }, i16, ptr, ptr } -define fastcc { i16, %struct.rnode* }* @get_token(i8** %s) nounwind { +define fastcc ptr @get_token(ptr %s) nounwind { entry: br i1 false, label %bb42, label %bb78 bb42: ; preds = %entry @@ -44,20 +44,19 @@ bb42: ; preds = %entry bb17.i: ; preds = %cond_next119.i br i1 false, label %cond_true53.i, label %cond_false99.i cond_true53.i: ; preds = %bb17.i - ret { i16, %struct.rnode* }* null + ret ptr null cond_false99.i: ; preds = %bb17.i - %malloccall = tail call i8* @malloc(i32 trunc (i64 mul nuw (i64 ptrtoint (i1** getelementptr (i1*, i1** null, i32 1) to i64), i64 2) to i32)) - %tmp106.i = bitcast i8* %malloccall to %struct.ch_set* + %malloccall = tail call ptr @malloc(i32 trunc (i64 mul nuw (i64 ptrtoint (ptr getelementptr (ptr, ptr null, i32 1) to i64), i64 2) to i32)) br i1 false, label %bb126.i, label %cond_next119.i cond_next119.i: ; preds = %cond_false99.i, %bb42 - %curr_ptr.0.reg2mem.0.i = phi %struct.ch_set* [ %tmp106.i, %cond_false99.i ], [ null, %bb42 ] ; <%struct.ch_set*> [#uses=2] - %prev_ptr.0.reg2mem.0.i = phi %struct.ch_set* [ %curr_ptr.0.reg2mem.0.i, %cond_false99.i ], [ undef, %bb42 ] ; <%struct.ch_set*> [#uses=1] + %curr_ptr.0.reg2mem.0.i = phi ptr [ %malloccall, %cond_false99.i ], [ null, %bb42 ] ; [#uses=2] + %prev_ptr.0.reg2mem.0.i = phi ptr [ %curr_ptr.0.reg2mem.0.i, %cond_false99.i ], [ undef, %bb42 ] ; [#uses=1] br i1 false, label %bb126.i, label %bb17.i bb126.i: ; preds = %cond_next119.i, %cond_false99.i - %prev_ptr.0.reg2mem.1.i = phi %struct.ch_set* [ %prev_ptr.0.reg2mem.0.i, %cond_next119.i ], [ %curr_ptr.0.reg2mem.0.i, %cond_false99.i ] ; <%struct.ch_set*> [#uses=0] - ret { i16, %struct.rnode* }* null + %prev_ptr.0.reg2mem.1.i = phi ptr [ %prev_ptr.0.reg2mem.0.i, %cond_next119.i ], [ %curr_ptr.0.reg2mem.0.i, %cond_false99.i ] ; [#uses=0] + ret ptr null bb78: ; preds = %entry - ret { i16, %struct.rnode* }* null + ret ptr null } -declare noalias i8* @malloc(i32) +declare noalias ptr @malloc(i32) diff --git a/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll index 1ededa3c387732..9c87fa2563a09e 100644 --- a/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll @@ -1,30 +1,30 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin %struct.CONTENTBOX = type { i32, i32, i32, i32, i32 } - %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } + %struct.FILE = type { ptr, i32, i32, i16, i16, %struct.__sbuf, i32, ptr, ptr, ptr, ptr, ptr, %struct.__sbuf, ptr, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } %struct.LOCBOX = type { i32, i32, i32, i32 } %struct.SIDEBOX = type { i32, i32 } %struct.UNCOMBOX = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.__sFILEX = type opaque - %struct.__sbuf = type { i8*, i32 } - %struct.cellbox = type { i8*, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, double, double, double, double, double, i32, i32, %struct.CONTENTBOX*, %struct.UNCOMBOX*, [8 x %struct.tilebox*], %struct.SIDEBOX* } - %struct.termbox = type { %struct.termbox*, i32, i32, i32, i32, i32 } - %struct.tilebox = type { %struct.tilebox*, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.termbox*, %struct.LOCBOX* } -@.str127 = external constant [2 x i8] ; <[2 x i8]*> [#uses=1] -@.str584 = external constant [5 x i8] ; <[5 x i8]*> [#uses=1] -@.str8115 = external constant [9 x i8] ; <[9 x i8]*> [#uses=1] + %struct.__sbuf = type { ptr, i32 } + %struct.cellbox = type { ptr, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, double, double, double, double, double, i32, i32, ptr, ptr, [8 x ptr], ptr } + %struct.termbox = type { ptr, i32, i32, i32, i32, i32 } + %struct.tilebox = type { ptr, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, ptr } +@.str127 = external constant [2 x i8] ; [#uses=1] +@.str584 = external constant [5 x i8] ; [#uses=1] +@.str8115 = external constant [9 x i8] ; [#uses=1] -declare %struct.FILE* @fopen(i8*, i8*) +declare ptr @fopen(ptr, ptr) -declare i32 @strcmp(i8*, i8*) +declare i32 @strcmp(ptr, ptr) -declare i32 @fscanf(%struct.FILE*, i8*, ...) +declare i32 @fscanf(ptr, ptr, ...) -define void @main(i32 %argc, i8** %argv) noreturn { +define void @main(i32 %argc, ptr %argv) noreturn { entry: br i1 false, label %cond_next48, label %cond_false674 cond_next48: ; preds = %entry - %tmp61 = call %struct.FILE* @fopen( i8* null, i8* getelementptr ([2 x i8], [2 x i8]* @.str127, i32 0, i32 0) ) ; <%struct.FILE*> [#uses=2] + %tmp61 = call ptr @fopen( ptr null, ptr @.str127 ) ; [#uses=2] br i1 false, label %bb220.i.i.i, label %bb62.preheader.i.i.i bb62.preheader.i.i.i: ; preds = %cond_next48 ret void @@ -53,11 +53,11 @@ bb177.i393.i: ; preds = %bb40.i.i bb192.i.i: ; preds = %bb177.i393.i ret void cond_false373.i.i: ; preds = %bb.i350.i - %tmp376.i.i = call i32 @strcmp( i8* null, i8* getelementptr ([9 x i8], [9 x i8]* @.str8115, i32 0, i32 0) ) ; [#uses=0] + %tmp376.i.i = call i32 @strcmp( ptr null, ptr @.str8115 ) ; [#uses=0] br i1 false, label %cond_true380.i.i, label %cond_next602.i.i cond_true380.i.i: ; preds = %cond_false373.i.i %tmp394.i418.i = add i32 %cell.0.i.i, 1 ; [#uses=1] - %tmp397.i420.i = load %struct.cellbox*, %struct.cellbox** null, align 4 ; <%struct.cellbox*> [#uses=1] + %tmp397.i420.i = load ptr, ptr null, align 4 ; [#uses=1] br label %bb398.i.i bb398.i.i: ; preds = %bb398.i.i, %cond_true380.i.i br i1 false, label %bb414.i.i, label %bb398.i.i @@ -73,10 +73,10 @@ bb609.i.i: ; preds = %cond_next602.i.i br label %bb620.i.i bb620.i.i: ; preds = %bb620.i.i, %bb609.i.i %indvar166.i465.i = phi i32 [ %indvar.next167.i.i, %bb620.i.i ], [ 0, %bb609.i.i ] ; [#uses=1] - %tmp640.i.i = call i32 (%struct.FILE*, i8*, ...) @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8], [5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; [#uses=0] - %tmp648.i.i = load i32, i32* null, align 4 ; [#uses=1] + %tmp640.i.i = call i32 (ptr, ptr, ...) @fscanf( ptr %tmp61, ptr @.str584, ptr null ) ; [#uses=0] + %tmp648.i.i = load i32, ptr null, align 4 ; [#uses=1] %tmp650.i468.i = icmp sgt i32 0, %tmp648.i.i ; [#uses=1] - %tmp624.i469.i = call i32 (%struct.FILE*, i8*, ...) @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8], [5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; [#uses=0] + %tmp624.i469.i = call i32 (ptr, ptr, ...) @fscanf( ptr %tmp61, ptr @.str584, ptr null ) ; [#uses=0] %indvar.next167.i.i = add i32 %indvar166.i465.i, 1 ; [#uses=1] br i1 %tmp650.i468.i, label %bb653.i.i.loopexit, label %bb620.i.i bb653.i.i.loopexit: ; preds = %bb620.i.i @@ -90,7 +90,7 @@ bb894.i.i: ; preds = %bb894.loopexit.i.i, %bb653.i.i.loopexit, %bb581.i.i, %bb1 %pinctr.0.i.i = phi i32 [ 0, %bb894.loopexit.i.i ], [ %tmp642.i466.i, %bb653.i.i.loopexit ], [ %pinctr.0.i.i, %bb177.i393.i ], [ %pinctr.0.i.i, %bb581.i.i ] ; [#uses=2] %soft.0.i.i = phi i32 [ undef, %bb894.loopexit.i.i ], [ %soft.0.i.i, %bb653.i.i.loopexit ], [ 0, %bb177.i393.i ], [ 1, %bb581.i.i ] ; [#uses=1] %cell.0.i.i = phi i32 [ 0, %bb894.loopexit.i.i ], [ %cell.0.i.i, %bb653.i.i.loopexit ], [ 0, %bb177.i393.i ], [ %tmp394.i418.i, %bb581.i.i ] ; [#uses=2] - %ptr.0.i.i = phi %struct.cellbox* [ undef, %bb894.loopexit.i.i ], [ %ptr.0.i.i, %bb653.i.i.loopexit ], [ null, %bb177.i393.i ], [ %tmp397.i420.i, %bb581.i.i ] ; <%struct.cellbox*> [#uses=1] + %ptr.0.i.i = phi ptr [ undef, %bb894.loopexit.i.i ], [ %ptr.0.i.i, %bb653.i.i.loopexit ], [ null, %bb177.i393.i ], [ %tmp397.i420.i, %bb581.i.i ] ; [#uses=1] br i1 false, label %bb.i350.i, label %bb902.i502.i bb902.i502.i: ; preds = %bb894.i.i ret void @@ -100,15 +100,15 @@ cond_false674: ; preds = %entry %struct.III_psy_xmin = type { [22 x double], [13 x [3 x double]] } %struct.III_scalefac_t = type { [22 x i32], [13 x [3 x i32]] } - %struct.gr_info = type { i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32*, [4 x i32] } - %struct.lame_global_flags = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, float, float, float, float, i32, i32, i32, i32, i32, i32, i32, i32 } -@scalefac_band.1 = external global [14 x i32] ; <[14 x i32]*> [#uses=2] + %struct.gr_info = type { i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, [4 x i32] } + %struct.lame_global_flags = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, ptr, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, float, float, float, float, i32, i32, i32, i32, i32, i32, i32, i32 } +@scalefac_band.1 = external global [14 x i32] ; [#uses=2] -declare fastcc i32 @init_outer_loop(%struct.lame_global_flags*, double*, %struct.gr_info*) +declare fastcc i32 @init_outer_loop(ptr, ptr, ptr) -define fastcc void @outer_loop(%struct.lame_global_flags* %gfp, double* %xr, i32 %targ_bits, double* %best_noise, %struct.III_psy_xmin* %l3_xmin, i32* %l3_enc, %struct.III_scalefac_t* %scalefac, %struct.gr_info* %cod_info, i32 %ch) { +define fastcc void @outer_loop(ptr %gfp, ptr %xr, i32 %targ_bits, ptr %best_noise, ptr %l3_xmin, ptr %l3_enc, ptr %scalefac, ptr %cod_info, i32 %ch) { entry: - %cod_info.182 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 1 ; [#uses=1] + %cod_info.182 = getelementptr %struct.gr_info, ptr %cod_info, i32 0, i32 1 ; [#uses=1] br label %bb bb: ; preds = %bb226, %entry %save_cod_info.1.1 = phi i32 [ undef, %entry ], [ %save_cod_info.1.1, %bb226 ] ; [#uses=2] @@ -126,7 +126,7 @@ cond_true163: ; preds = %cond_next144 bb.i53: ; preds = %cond_true163 ret void bb34.i: ; preds = %cond_true163 - %tmp37.i55 = load i32, i32* null, align 4 ; [#uses=1] + %tmp37.i55 = load i32, ptr null, align 4 ; [#uses=1] br i1 false, label %bb65.preheader.i, label %bb78.i bb65.preheader.i: ; preds = %bb34.i br label %bb65.outer.us.i @@ -148,16 +148,16 @@ bb226.backedge.i: ; preds = %cond_next215.i, %bb151.i bb155.i: ; preds = %cond_next215.i, %bb151.i %indvar90.i = phi i32 [ %indvar.next91.i, %cond_next215.i ], [ 0, %bb151.i ] ; [#uses=2] %sfb.3.reg2mem.0.i = add i32 %indvar90.i, %tmp37.i55 ; [#uses=4] - %tmp161.i = getelementptr [4 x [21 x double]], [4 x [21 x double]]* null, i32 0, i32 %tmp15747.i, i32 %sfb.3.reg2mem.0.i ; [#uses=1] - %tmp162.i74 = load double, double* %tmp161.i, align 4 ; [#uses=0] + %tmp161.i = getelementptr [4 x [21 x double]], ptr null, i32 0, i32 %tmp15747.i, i32 %sfb.3.reg2mem.0.i ; [#uses=1] + %tmp162.i74 = load double, ptr %tmp161.i, align 4 ; [#uses=0] br i1 false, label %cond_true167.i, label %cond_next215.i cond_true167.i: ; preds = %bb155.i - %tmp173.i = getelementptr %struct.III_scalefac_t, %struct.III_scalefac_t* null, i32 0, i32 1, i32 %sfb.3.reg2mem.0.i, i32 %i.154.i ; [#uses=1] - store i32 0, i32* %tmp173.i, align 4 - %tmp182.1.i = getelementptr [14 x i32], [14 x i32]* @scalefac_band.1, i32 0, i32 %sfb.3.reg2mem.0.i ; [#uses=0] + %tmp173.i = getelementptr %struct.III_scalefac_t, ptr null, i32 0, i32 1, i32 %sfb.3.reg2mem.0.i, i32 %i.154.i ; [#uses=1] + store i32 0, ptr %tmp173.i, align 4 + %tmp182.1.i = getelementptr [14 x i32], ptr @scalefac_band.1, i32 0, i32 %sfb.3.reg2mem.0.i ; [#uses=0] %tmp185.i78 = add i32 %sfb.3.reg2mem.0.i, 1 ; [#uses=1] - %tmp187.1.i = getelementptr [14 x i32], [14 x i32]* @scalefac_band.1, i32 0, i32 %tmp185.i78 ; [#uses=1] - %tmp188.i = load i32, i32* %tmp187.1.i, align 4 ; [#uses=1] + %tmp187.1.i = getelementptr [14 x i32], ptr @scalefac_band.1, i32 0, i32 %tmp185.i78 ; [#uses=1] + %tmp188.i = load i32, ptr %tmp187.1.i, align 4 ; [#uses=1] %tmp21153.i = icmp slt i32 0, %tmp188.i ; [#uses=1] br i1 %tmp21153.i, label %bb190.preheader.i, label %cond_next215.i bb190.preheader.i: ; preds = %cond_true167.i @@ -179,23 +179,23 @@ cond_next205: ; preds = %bb19.i, %cond_next144 cond_true210: ; preds = %cond_next205 br i1 false, label %bb226, label %cond_true217 cond_true217: ; preds = %cond_true210 - %tmp221 = call fastcc i32 @init_outer_loop( %struct.lame_global_flags* %gfp, double* %xr, %struct.gr_info* %cod_info ) ; [#uses=0] + %tmp221 = call fastcc i32 @init_outer_loop( ptr %gfp, ptr %xr, ptr %cod_info ) ; [#uses=0] ret void bb226: ; preds = %cond_true210, %cond_next205 br i1 false, label %bb231, label %bb bb231: ; preds = %bb226 - store i32 %save_cod_info.1.1, i32* %cod_info.182 + store i32 %save_cod_info.1.1, ptr %cod_info.182 ret void } -define fastcc void @outer_loop2(%struct.lame_global_flags* %gfp, double* %xr, i32 %targ_bits, double* %best_noise, %struct.III_psy_xmin* %l3_xmin, i32* %l3_enc, %struct.III_scalefac_t* %scalefac, %struct.gr_info* %cod_info, i32 %ch) { +define fastcc void @outer_loop2(ptr %gfp, ptr %xr, i32 %targ_bits, ptr %best_noise, ptr %l3_xmin, ptr %l3_enc, ptr %scalefac, ptr %cod_info, i32 %ch) { entry: - %cod_info.20128.1 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 20, i32 1 ; [#uses=1] - %cod_info.20128.2 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 20, i32 2 ; [#uses=1] - %cod_info.20128.3 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 20, i32 3 ; [#uses=1] + %cod_info.20128.1 = getelementptr %struct.gr_info, ptr %cod_info, i32 0, i32 20, i32 1 ; [#uses=1] + %cod_info.20128.2 = getelementptr %struct.gr_info, ptr %cod_info, i32 0, i32 20, i32 2 ; [#uses=1] + %cod_info.20128.3 = getelementptr %struct.gr_info, ptr %cod_info, i32 0, i32 20, i32 3 ; [#uses=1] br label %bb bb: ; preds = %bb226, %entry - %save_cod_info.19.1 = phi i32* [ undef, %entry ], [ %save_cod_info.19.0, %bb226 ] ; [#uses=1] + %save_cod_info.19.1 = phi ptr [ undef, %entry ], [ %save_cod_info.19.0, %bb226 ] ; [#uses=1] %save_cod_info.0.1 = phi i32 [ undef, %entry ], [ %save_cod_info.0.0, %bb226 ] ; [#uses=1] br i1 false, label %cond_next144, label %cond_false cond_false: ; preds = %bb @@ -215,7 +215,7 @@ cond_next104: ; preds = %inner_loop.exit cond_false110: ; preds = %cond_next104 ret void cond_next144: ; preds = %cond_next104, %bb - %save_cod_info.19.0 = phi i32* [ %save_cod_info.19.1, %bb ], [ null, %cond_next104 ] ; [#uses=1] + %save_cod_info.19.0 = phi ptr [ %save_cod_info.19.1, %bb ], [ null, %cond_next104 ] ; [#uses=1] %save_cod_info.4.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; [#uses=1] %save_cod_info.3.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; [#uses=1] %save_cod_info.2.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; [#uses=1] @@ -224,7 +224,7 @@ cond_next144: ; preds = %cond_next104, %bb %over.1 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; [#uses=1] %best_over.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; [#uses=1] %notdone.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; [#uses=1] - %tmp147 = load i32, i32* null, align 4 ; [#uses=1] + %tmp147 = load i32, ptr null, align 4 ; [#uses=1] %tmp148 = icmp eq i32 %tmp147, 0 ; [#uses=1] %tmp153 = icmp eq i32 %over.1, 0 ; [#uses=1] %bothcond = and i1 %tmp148, %tmp153 ; [#uses=1] @@ -240,14 +240,14 @@ bb226: ; preds = %cond_next205 %tmp228 = icmp eq i32 %notdone.2, 0 ; [#uses=1] br i1 %tmp228, label %bb231, label %bb bb231: ; preds = %bb226 - store i32 %save_cod_info.1.0, i32* null - store i32 %save_cod_info.2.0, i32* null - store i32 %save_cod_info.3.0, i32* null - store i32 %save_cod_info.4.0, i32* null - store i32 0, i32* %cod_info.20128.1 - store i32 0, i32* %cod_info.20128.2 - store i32 0, i32* %cod_info.20128.3 + store i32 %save_cod_info.1.0, ptr null + store i32 %save_cod_info.2.0, ptr null + store i32 %save_cod_info.3.0, ptr null + store i32 %save_cod_info.4.0, ptr null + store i32 0, ptr %cod_info.20128.1 + store i32 0, ptr %cod_info.20128.2 + store i32 0, ptr %cod_info.20128.3 %tmp244245 = sitofp i32 %best_over.0 to double ; [#uses=1] - store double %tmp244245, double* %best_noise, align 4 + store double %tmp244245, ptr %best_noise, align 4 ret void } diff --git a/llvm/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll b/llvm/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll index 33bd4def5b4958..1eeced4ba775d9 100644 --- a/llvm/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll +++ b/llvm/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -declare void @foo(i8*, i8*, i32, i32, i32, i32, i32, i32, i32) +declare void @foo(ptr, ptr, i32, i32, i32, i32, i32, i32, i32) define void @t() nounwind { br label %1 @@ -29,7 +29,7 @@ bb4498.i: ; preds = %bb4411.i ] bb4501.i: ; preds = %bb4498.i %sfComp4077.1.reg2mem.0.i = phi i32 [ %sfComp4077.1.i, %bb4498.i ] ; [#uses=1] - call void @foo( i8* null, i8* null, i32 %sfComp4077.1.reg2mem.0.i, i32 0, i32 8, i32 0, i32 0, i32 0, i32 0 ) nounwind + call void @foo( ptr null, ptr null, i32 %sfComp4077.1.reg2mem.0.i, i32 0, i32 8, i32 0, i32 0, i32 0, i32 0 ) nounwind br i1 false, label %UnifiedReturnBlock.i, label %bb4517.i bb4517.i: ; preds = %bb4501.i br label %t.exit diff --git a/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll b/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll index 85ef8302a18ab2..e90f7cf49fb958 100644 --- a/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll +++ b/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll @@ -1,19 +1,19 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin %struct.BiContextType = type { i16, i8, i32 } - %struct.Bitstream = type { i32, i32, i8, i32, i32, i8, i8, i32, i32, i8*, i32 } - %struct.DataPartition = type { %struct.Bitstream*, %struct.EncodingEnvironment, %struct.EncodingEnvironment } - %struct.DecRefPicMarking_t = type { i32, i32, i32, i32, i32, %struct.DecRefPicMarking_t* } - %struct.EncodingEnvironment = type { i32, i32, i32, i32, i32, i8*, i32*, i32, i32 } - %struct.ImageParameters = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8**, i8**, i32, i32***, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [9 x [16 x [16 x i16]]], [5 x [16 x [16 x i16]]], [9 x [8 x [8 x i16]]], [2 x [4 x [16 x [16 x i16]]]], [16 x [16 x i16]], [16 x [16 x i32]], i32****, i32***, i32***, i32***, i32****, i32****, %struct.Picture*, %struct.Slice*, %struct.Macroblock*, i32*, i32*, i32, i32, i32, i32, [4 x [4 x i32]], i32, i32, i32, i32, i32, double, i32, i32, i32, i32, i16******, i16******, i16******, i16******, [15 x i16], i32, i32, i32, i32, i32, i32, i32, i32, [6 x [32 x i32]], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [1 x i32], i32, i32, [2 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.DecRefPicMarking_t*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, double**, double***, i32***, double**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x [2 x i32]], [2 x i32], i32, i32, i16, i32, i32, i32, i32, i32 } - %struct.Macroblock = type { i32, i32, i32, [2 x i32], i32, [8 x i32], %struct.Macroblock*, %struct.Macroblock*, i32, [2 x [4 x [4 x [2 x i32]]]], [16 x i8], [16 x i8], i32, i64, [4 x i32], [4 x i32], i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, double, i32, i32, i32, i32, i32, i32, i32, i32, i32 } + %struct.Bitstream = type { i32, i32, i8, i32, i32, i8, i8, i32, i32, ptr, i32 } + %struct.DataPartition = type { ptr, %struct.EncodingEnvironment, %struct.EncodingEnvironment } + %struct.DecRefPicMarking_t = type { i32, i32, i32, i32, i32, ptr } + %struct.EncodingEnvironment = type { i32, i32, i32, i32, i32, ptr, ptr, i32, i32 } + %struct.ImageParameters = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, ptr, i32, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [9 x [16 x [16 x i16]]], [5 x [16 x [16 x i16]]], [9 x [8 x [8 x i16]]], [2 x [4 x [16 x [16 x i16]]]], [16 x [16 x i16]], [16 x [16 x i32]], ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, i32, [4 x [4 x i32]], i32, i32, i32, i32, i32, double, i32, i32, i32, i32, ptr, ptr, ptr, ptr, [15 x i16], i32, i32, i32, i32, i32, i32, i32, i32, [6 x [32 x i32]], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [1 x i32], i32, i32, [2 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, ptr, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x [2 x i32]], [2 x i32], i32, i32, i16, i32, i32, i32, i32, i32 } + %struct.Macroblock = type { i32, i32, i32, [2 x i32], i32, [8 x i32], ptr, ptr, i32, [2 x [4 x [4 x [2 x i32]]]], [16 x i8], [16 x i8], i32, i64, [4 x i32], [4 x i32], i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, double, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.MotionInfoContexts = type { [3 x [11 x %struct.BiContextType]], [2 x [9 x %struct.BiContextType]], [2 x [10 x %struct.BiContextType]], [2 x [6 x %struct.BiContextType]], [4 x %struct.BiContextType], [4 x %struct.BiContextType], [3 x %struct.BiContextType] } - %struct.Picture = type { i32, i32, [100 x %struct.Slice*], i32, float, float, float } - %struct.Slice = type { i32, i32, i32, i32, i32, i32, %struct.DataPartition*, %struct.MotionInfoContexts*, %struct.TextureInfoContexts*, i32, i32*, i32*, i32*, i32, i32*, i32*, i32*, i32 (i32)*, [3 x [2 x i32]] } + %struct.Picture = type { i32, i32, [100 x ptr], i32, float, float, float } + %struct.Slice = type { i32, i32, i32, i32, i32, i32, ptr, ptr, ptr, i32, ptr, ptr, ptr, i32, ptr, ptr, ptr, ptr, [3 x [2 x i32]] } %struct.TextureInfoContexts = type { [2 x %struct.BiContextType], [4 x %struct.BiContextType], [3 x [4 x %struct.BiContextType]], [10 x [4 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]], [10 x [5 x %struct.BiContextType]], [10 x [5 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]] } -@images = external global %struct.ImageParameters ; <%struct.ImageParameters*> [#uses=2] +@images = external global %struct.ImageParameters ; [#uses=2] -declare i8* @calloc(i32, i32) +declare ptr @calloc(i32, i32) define fastcc void @init_global_buffers() nounwind { entry: @@ -21,16 +21,16 @@ entry: br i1 false, label %init_orig_buffers.exit, label %cond_true.i29 cond_true.i29: ; preds = %entry - %tmp17.i = load i32, i32* getelementptr (%struct.ImageParameters, %struct.ImageParameters* @images, i32 0, i32 20), align 8 ; [#uses=1] - %tmp20.i27 = load i32, i32* getelementptr (%struct.ImageParameters, %struct.ImageParameters* @images, i32 0, i32 16), align 8 ; [#uses=1] + %tmp17.i = load i32, ptr getelementptr (%struct.ImageParameters, ptr @images, i32 0, i32 20), align 8 ; [#uses=1] + %tmp20.i27 = load i32, ptr getelementptr (%struct.ImageParameters, ptr @images, i32 0, i32 16), align 8 ; [#uses=1] %tmp8.i.i = select i1 false, i32 1, i32 0 ; [#uses=1] br label %bb.i8.us.i bb.i8.us.i: ; preds = %get_mem2Dpel.exit.i.us.i, %cond_true.i29 %j.04.i.us.i = phi i32 [ %indvar.next39.i, %get_mem2Dpel.exit.i.us.i ], [ 0, %cond_true.i29 ] ; [#uses=2] - %tmp13.i.us.i = getelementptr i16**, i16*** null, i32 %j.04.i.us.i ; [#uses=0] - %tmp15.i.i.us.i = tail call i8* @calloc( i32 0, i32 2 ) ; [#uses=0] - store i16* null, i16** null, align 4 + %tmp13.i.us.i = getelementptr ptr, ptr null, i32 %j.04.i.us.i ; [#uses=0] + %tmp15.i.i.us.i = tail call ptr @calloc( i32 0, i32 2 ) ; [#uses=0] + store ptr null, ptr null, align 4 br label %bb.i.i.us.i get_mem2Dpel.exit.i.us.i: ; preds = %bb.i.i.us.i diff --git a/llvm/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll index 3d69e4fefbc27e..bd437560860734 100644 --- a/llvm/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll @@ -1,16 +1,16 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin - %struct.Decoders = type { i32**, i16***, i16****, i16***, i16**, i8**, i8** } -@decoders = external global %struct.Decoders ; <%struct.Decoders*> [#uses=1] + %struct.Decoders = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr } +@decoders = external global %struct.Decoders ; [#uses=1] -declare i8* @calloc(i32, i32) +declare ptr @calloc(i32, i32) -declare fastcc i32 @get_mem2Dint(i32***, i32, i32) +declare fastcc i32 @get_mem2Dint(ptr, i32, i32) define fastcc void @init_global_buffers() nounwind { entry: - %tmp151 = tail call fastcc i32 @get_mem2Dint( i32*** getelementptr (%struct.Decoders, %struct.Decoders* @decoders, i32 0, i32 0), i32 16, i32 16 ) ; [#uses=1] - %tmp158 = tail call i8* @calloc( i32 0, i32 4 ) ; [#uses=0] + %tmp151 = tail call fastcc i32 @get_mem2Dint( ptr @decoders, i32 16, i32 16 ) ; [#uses=1] + %tmp158 = tail call ptr @calloc( i32 0, i32 4 ) ; [#uses=0] br i1 false, label %cond_true166, label %bb190.preheader bb190.preheader: ; preds = %entry diff --git a/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll b/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll index cf98d7f91df06f..5d014954f28591 100644 --- a/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll +++ b/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll @@ -1,9 +1,9 @@ ; RUN: llc -mtriple=arm-eabi %s -o /dev/null ; PR2589 -define void @main({ i32 }*) { +define void @main(ptr) { entry: - %sret1 = alloca { i32 } ; <{ i32 }*> [#uses=1] - load { i32 }, { i32 }* %sret1 ; <{ i32 }>:1 [#uses=0] + %sret1 = alloca { i32 } ; [#uses=1] + load { i32 }, ptr %sret1 ; <{ i32 }>:1 [#uses=0] ret void } diff --git a/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll b/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll index 99f3052114fd5b..af0658f87c3a8c 100644 --- a/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll +++ b/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll @@ -1,14 +1,14 @@ ; RUN: llc -mtriple arm-apple-darwin -mattr=+v6 -relocation-model pic -filetype asm -o - %s | FileCheck %s -%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } -%struct.__gcov_var = type { %struct.FILE*, i32, i32, i32, i32, i32, i32, [1025 x i32] } +%struct.FILE = type { ptr, i32, i32, i16, i16, %struct.__sbuf, i32, ptr, ptr, ptr, ptr, ptr, %struct.__sbuf, ptr, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } +%struct.__gcov_var = type { ptr, i32, i32, i32, i32, i32, i32, [1025 x i32] } %struct.__sFILEX = type opaque -%struct.__sbuf = type { i8*, i32 } +%struct.__sbuf = type { ptr, i32 } @__gcov_var = common global %struct.__gcov_var zeroinitializer define i32 @__gcov_close() nounwind { entry: - load i32, i32* getelementptr (%struct.__gcov_var, %struct.__gcov_var* @__gcov_var, i32 0, i32 5), align 4 + load i32, ptr getelementptr (%struct.__gcov_var, ptr @__gcov_var, i32 0, i32 5), align 4 ret i32 %0 } diff --git a/llvm/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll b/llvm/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll index d3bc3e1663bcf2..ec9fd5a244856e 100644 --- a/llvm/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll +++ b/llvm/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll @@ -8,10 +8,10 @@ bb24: ; preds = %entry br label %bb39 bb33.thread: ; preds = %entry - %0 = alloca i8, i32 0 ; [#uses=1] + %0 = alloca i8, i32 0 ; [#uses=1] br label %bb39 bb39: ; preds = %bb33.thread, %bb24 - %.reg2mem.0 = phi i8* [ %0, %bb33.thread ], [ null, %bb24 ] ; [#uses=0] + %.reg2mem.0 = phi ptr [ %0, %bb33.thread ], [ null, %bb24 ] ; [#uses=0] ret void } diff --git a/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll b/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll index bdb47fcc6ae3c0..8063e0fd671359 100644 --- a/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll +++ b/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll @@ -5,17 +5,17 @@ target triple = "arm-apple-darwin9" %struct.FIRST_UNION = type { %struct.FILE_POS } %struct.FOURTH_UNION = type { %struct.STYLE } %struct.GAP = type { i8, i8, i16 } - %struct.LIST = type { %struct.rec*, %struct.rec* } + %struct.LIST = type { ptr, ptr } %struct.SECOND_UNION = type { { i16, i8, i8 } } %struct.STYLE = type { { %struct.GAP }, { %struct.GAP }, i16, i16, i32 } %struct.THIRD_UNION = type { { [2 x i32], [2 x i32] } } - %struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, %struct.rec*, { %struct.rec* }, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i32 } + %struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, ptr, { ptr }, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32 } %struct.rec = type { %struct.head_type } -@no_file_pos = external global %struct.FILE_POS ; <%struct.FILE_POS*> [#uses=1] -@"\01LC13423" = external constant [23 x i8] ; <[23 x i8]*> [#uses=1] -@"\01LC18972" = external constant [13 x i8] ; <[13 x i8]*> [#uses=1] +@no_file_pos = external global %struct.FILE_POS ; [#uses=1] +@"\01LC13423" = external constant [23 x i8] ; [#uses=1] +@"\01LC18972" = external constant [13 x i8] ; [#uses=1] -define fastcc void @FlushGalley(%struct.rec* %hd) nounwind { +define fastcc void @FlushGalley(ptr %hd) nounwind { entry: br label %RESUME @@ -77,25 +77,25 @@ bb131: ; preds = %bb122 br label %bb396 bb244: ; preds = %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122 - %0 = icmp eq %struct.rec* %stop_link.3, null ; [#uses=1] + %0 = icmp eq ptr %stop_link.3, null ; [#uses=1] br i1 %0, label %bb435, label %bb433 bb394: ; preds = %bb122 - call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...) @Error(i32 1, i32 3, i8* getelementptr ([23 x i8], [23 x i8]* @"\01LC13423", i32 0, i32 0), i32 0, %struct.FILE_POS* @no_file_pos, i8* getelementptr ([13 x i8], [13 x i8]* @"\01LC18972", i32 0, i32 0), i8* null) nounwind + call void (i32, i32, ptr, i32, ptr, ...) @Error(i32 1, i32 3, ptr @"\01LC13423", i32 0, ptr @no_file_pos, ptr @"\01LC18972", ptr null) nounwind br label %bb396 bb396: ; preds = %bb394, %bb131, %bb122, %bb122, %bb122, %bb122, %RESUME - %stop_link.3 = phi %struct.rec* [ null, %RESUME ], [ %stop_link.3, %bb394 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %link.1, %bb131 ] ; <%struct.rec*> [#uses=7] + %stop_link.3 = phi ptr [ null, %RESUME ], [ %stop_link.3, %bb394 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %link.1, %bb131 ] ; [#uses=7] %headers_seen.1 = phi i32 [ 0, %RESUME ], [ %headers_seen.1, %bb394 ], [ 1, %bb122 ], [ 1, %bb122 ], [ 1, %bb122 ], [ 1, %bb122 ], [ %headers_seen.1, %bb131 ] ; [#uses=2] - %link.1 = load %struct.rec*, %struct.rec** null ; <%struct.rec*> [#uses=2] - %1 = icmp eq %struct.rec* %link.1, %hd ; [#uses=1] + %link.1 = load ptr, ptr null ; [#uses=2] + %1 = icmp eq ptr %link.1, %hd ; [#uses=1] br i1 %1, label %bb398, label %bb122 bb398: ; preds = %bb396 unreachable bb433: ; preds = %bb244 - call fastcc void @Promote(%struct.rec* %hd, %struct.rec* %stop_link.3, %struct.rec* null, i32 1) nounwind + call fastcc void @Promote(ptr %hd, ptr %stop_link.3, ptr null, i32 1) nounwind br label %bb435 bb435: ; preds = %bb433, %bb244 @@ -105,13 +105,13 @@ bb491: ; preds = %bb435 br label %bb499 bb499: ; preds = %bb499, %bb491, %bb435 - %2 = icmp eq %struct.rec* null, null ; [#uses=1] + %2 = icmp eq ptr null, null ; [#uses=1] br i1 %2, label %bb520.preheader, label %bb499 bb520.preheader: ; preds = %bb499 br label %RESUME } -declare fastcc void @Promote(%struct.rec*, %struct.rec*, %struct.rec* nocapture, i32) nounwind +declare fastcc void @Promote(ptr, ptr, ptr nocapture, i32) nounwind -declare void @Error(i32, i32, i8*, i32, %struct.FILE_POS*, ...) nounwind +declare void @Error(i32, i32, ptr, i32, ptr, ...) nounwind diff --git a/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll b/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll index a14589fa47d8fa..e4b8bfd5cebecb 100644 --- a/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll +++ b/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll @@ -3,18 +3,18 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-s0:0:64-f80:32:32" target triple = "arm-elf" -define i32 @main(i8*) nounwind { +define i32 @main(ptr) nounwind { entry: - %ap = alloca i8* ; [#uses=2] - store i8* %0, i8** %ap - %retval = alloca i32 ; [#uses=2] - store i32 0, i32* %retval - %tmp = alloca float ; [#uses=1] - %1 = va_arg i8** %ap, float ; [#uses=1] - store float %1, float* %tmp + %ap = alloca ptr ; [#uses=2] + store ptr %0, ptr %ap + %retval = alloca i32 ; [#uses=2] + store i32 0, ptr %retval + %tmp = alloca float ; [#uses=1] + %1 = va_arg ptr %ap, float ; [#uses=1] + store float %1, ptr %tmp br label %return return: ; preds = %entry - %2 = load i32, i32* %retval ; [#uses=1] + %2 = load i32, ptr %retval ; [#uses=1] ret i32 %2 } diff --git a/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll b/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll index 1584a88c763083..61014ec8dbc9d9 100644 --- a/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll +++ b/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll @@ -1,12 +1,12 @@ ; RUN: llc < %s -mattr=+v6,+vfp2 target triple = "arm-apple-darwin9" -@a = external global double ; [#uses=1] -@N = external global double ; [#uses=1] +@a = external global double ; [#uses=1] +@N = external global double ; [#uses=1] declare double @llvm.exp.f64(double) nounwind readonly -define fastcc void @findratio(double* nocapture %res1, double* nocapture %res2) nounwind { +define fastcc void @findratio(ptr nocapture %res1, ptr nocapture %res2) nounwind { bb.thread: br label %bb52 @@ -28,12 +28,12 @@ bb53: ; preds = %bb52 br i1 %phitmp, label %bb55, label %bb52 bb55: ; preds = %bb53 - %4 = load double, double* @a, align 4 ; [#uses=10] + %4 = load double, ptr @a, align 4 ; [#uses=10] %5 = fadd double %4, 0.000000e+00 ; [#uses=16] %6 = fcmp ogt double %k.4, 0.000000e+00 ; [#uses=1] %.pn404 = fmul double %4, %4 ; [#uses=4] %.pn402 = fmul double %5, %5 ; [#uses=5] - %.pn165.in = load double, double* @N ; [#uses=5] + %.pn165.in = load double, ptr @N ; [#uses=5] %.pn198 = fmul double 0.000000e+00, %5 ; [#uses=1] %.pn185 = fsub double -0.000000e+00, 0.000000e+00 ; [#uses=1] %.pn147 = fsub double -0.000000e+00, 0.000000e+00 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll b/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll index 62a9aa23f29f99..9acdb2a4dbf43a 100644 --- a/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll +++ b/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll @@ -2,7 +2,7 @@ ; rdar://6653182 -%struct.ggBRDF = type { i32 (...)** } +%struct.ggBRDF = type { ptr } %struct.ggPoint2 = type { [2 x double] } %struct.ggPoint3 = type { [3 x double] } %struct.ggSpectrum = type { [8 x float] } @@ -17,7 +17,7 @@ declare double @sin(double) nounwind readonly declare double @acos(double) nounwind readonly -define i32 @_ZNK34mrDiffuseSolidAngleSphereLuminaire18selectVisiblePointERK8ggPoint3RK9ggVector3RK8ggPoint2dRS0_Rd(%struct.mrDiffuseCosineSphereLuminaire* nocapture %this, %struct.ggPoint3* nocapture %x, %struct.ggPoint3* nocapture %unnamed_arg, %struct.ggPoint2* nocapture %uv, double %unnamed_arg2, %struct.ggPoint3* nocapture %on_light, double* nocapture %invProb) nounwind { +define i32 @_ZNK34mrDiffuseSolidAngleSphereLuminaire18selectVisiblePointERK8ggPoint3RK9ggVector3RK8ggPoint2dRS0_Rd(ptr nocapture %this, ptr nocapture %x, ptr nocapture %unnamed_arg, ptr nocapture %uv, double %unnamed_arg2, ptr nocapture %on_light, ptr nocapture %invProb) nounwind { entry: %0 = call double @llvm.sqrt.f64(double 0.000000e+00) nounwind %1 = fcmp ult double 0.000000e+00, %0 @@ -42,7 +42,7 @@ bb3: ; preds = %entry %17 = fdiv double %16, %0 %18 = fadd double 0.000000e+00, %17 %19 = call double @acos(double %18) nounwind readonly - %20 = load double, double* null, align 4 + %20 = load double, ptr null, align 4 %21 = fmul double %20, 0x401921FB54442D18 %22 = call double @sin(double %19) nounwind readonly %23 = fmul double %22, 0.000000e+00 @@ -58,22 +58,21 @@ bb3: ; preds = %entry %33 = fadd double %30, 0.000000e+00 %34 = fadd double %31, 0.000000e+00 %35 = fadd double %32, 0.000000e+00 - %36 = bitcast %struct.ggPoint3* %x to i8* - call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 null, i8* align 4 %36, i32 24, i1 false) - store double %33, double* null, align 8 + call void @llvm.memcpy.p0.p0.i32(ptr align 4 null, ptr align 4 %x, i32 24, i1 false) + store double %33, ptr null, align 8 br i1 false, label %_Z20ggRaySphereIntersectRK6ggRay3RK8ggSphereddRd.exit, label %bb5.i.i.i bb5.i.i.i: ; preds = %bb3 unreachable _Z20ggRaySphereIntersectRK6ggRay3RK8ggSphereddRd.exit: ; preds = %bb3 - %37 = fsub double %13, 0.000000e+00 - %38 = fsub double -0.000000e+00, %34 - %39 = fsub double -0.000000e+00, %35 + %36 = fsub double %13, 0.000000e+00 + %37 = fsub double -0.000000e+00, %34 + %38 = fsub double -0.000000e+00, %35 ret i32 1 bb7: ; preds = %entry ret i32 0 } -declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind +declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind diff --git a/llvm/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll b/llvm/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll index a9d5480e72c922..3937f9e9ac87bb 100644 --- a/llvm/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll +++ b/llvm/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll @@ -4,10 +4,9 @@ %struct.node_t = type { %struct.hit_t, %struct.hit_t, i32 } %struct.v_t = type { double, double, double } -define fastcc %struct.node_t* @_ZL6createP6node_tii3v_tS1_d(%struct.node_t* %n, i32 %lvl, i32 %dist, i64 %c.0.0, i64 %c.0.1, i64 %c.0.2, i64 %d.0.0, i64 %d.0.1, i64 %d.0.2, double %r) nounwind { +define fastcc ptr @_ZL6createP6node_tii3v_tS1_d(ptr %n, i32 %lvl, i32 %dist, i64 %c.0.0, i64 %c.0.1, i64 %c.0.2, i64 %d.0.0, i64 %d.0.1, i64 %d.0.2, double %r) nounwind { entry: - %0 = getelementptr %struct.node_t, %struct.node_t* %n, i32 0, i32 1 ; <%struct.hit_t*> [#uses=1] - %1 = bitcast %struct.hit_t* %0 to i256* ; [#uses=1] - store i256 0, i256* %1, align 4 + %0 = getelementptr %struct.node_t, ptr %n, i32 0, i32 1 ; [#uses=1] + store i256 0, ptr %0, align 4 unreachable } diff --git a/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll b/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll index bc7dbd4f695313..1ab71b214ca7d8 100644 --- a/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll +++ b/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll @@ -2,20 +2,20 @@ define i32 @_swilseek(i32) nounwind { entry: - %ptr = alloca i32 ; [#uses=2] - store i32 %0, i32* %ptr - %retval = alloca i32 ; [#uses=2] - store i32 0, i32* %retval - %res = alloca i32 ; [#uses=0] - %fh = alloca i32 ; [#uses=1] - %1 = load i32, i32* %fh ; [#uses=1] - %2 = load i32, i32* %ptr ; [#uses=1] + %ptr = alloca i32 ; [#uses=2] + store i32 %0, ptr %ptr + %retval = alloca i32 ; [#uses=2] + store i32 0, ptr %retval + %res = alloca i32 ; [#uses=0] + %fh = alloca i32 ; [#uses=1] + %1 = load i32, ptr %fh ; [#uses=1] + %2 = load i32, ptr %ptr ; [#uses=1] %3 = call i32 asm "mov r0, $2; mov r1, $3; swi ${1:a}; mov $0, r0", "=r,i,r,r,~{r0},~{r1}"(i32 107, i32 %1, i32 %2) nounwind ; [#uses=1] - store i32 %3, i32* %retval + store i32 %3, ptr %retval br label %return return: ; preds = %entry - %4 = load i32, i32* %retval ; [#uses=1] + %4 = load i32, ptr %retval ; [#uses=1] ret i32 %4 } diff --git a/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll b/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll index edeae9b88bcec3..8a8ab54d125487 100644 --- a/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll +++ b/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll @@ -1,18 +1,18 @@ ; RUN: llc -mtriple=arm-eabi %s -o /dev/null ; PR3795 -define fastcc void @_D3foo3fooFAriZv({ i32, { double, double }* } %d_arg, i32 %x_arg) { +define fastcc void @_D3foo3fooFAriZv({ i32, ptr } %d_arg, i32 %x_arg) { entry: - %d = alloca { i32, { double, double }* } ; <{ i32, { double, double }* }*> [#uses=2] - %x = alloca i32 ; [#uses=2] - %b = alloca { double, double } ; <{ double, double }*> [#uses=1] - store { i32, { double, double }* } %d_arg, { i32, { double, double }* }* %d - store i32 %x_arg, i32* %x - %tmp = load i32, i32* %x ; [#uses=1] - %tmp1 = getelementptr { i32, { double, double }* }, { i32, { double, double }* }* %d, i32 0, i32 1 ; <{ double, double }**> [#uses=1] - %.ptr = load { double, double }*, { double, double }** %tmp1 ; <{ double, double }*> [#uses=1] - %tmp2 = getelementptr { double, double }, { double, double }* %.ptr, i32 %tmp ; <{ double, double }*> [#uses=1] - %tmp3 = load { double, double }, { double, double }* %tmp2 ; <{ double, double }> [#uses=1] - store { double, double } %tmp3, { double, double }* %b + %d = alloca { i32, ptr } ; [#uses=2] + %x = alloca i32 ; [#uses=2] + %b = alloca { double, double } ; [#uses=1] + store { i32, ptr } %d_arg, ptr %d + store i32 %x_arg, ptr %x + %tmp = load i32, ptr %x ; [#uses=1] + %tmp1 = getelementptr { i32, ptr }, ptr %d, i32 0, i32 1 ; [#uses=1] + %.ptr = load ptr, ptr %tmp1 ; [#uses=1] + %tmp2 = getelementptr { double, double }, ptr %.ptr, i32 %tmp ; [#uses=1] + %tmp3 = load { double, double }, ptr %tmp2 ; <{ double, double }> [#uses=1] + store { double, double } %tmp3, ptr %b ret void } diff --git a/llvm/test/CodeGen/ARM/2009-04-08-FREM.ll b/llvm/test/CodeGen/ARM/2009-04-08-FREM.ll index e0f9485888d9e1..d7dca8e57b5993 100644 --- a/llvm/test/CodeGen/ARM/2009-04-08-FREM.ll +++ b/llvm/test/CodeGen/ARM/2009-04-08-FREM.ll @@ -1,9 +1,9 @@ ; RUN: llc -mtriple=arm-eabi %s -o /dev/null -declare i32 @printf(i8*, ...) +declare i32 @printf(ptr, ...) define i32 @main() { %rem_r = frem double 0.000000e+00, 0.000000e+00 ; [#uses=1] - %1 = call i32 (i8*, ...) @printf(i8* null, double %rem_r) ; [#uses=0] + %1 = call i32 (ptr, ...) @printf(ptr null, double %rem_r) ; [#uses=0] ret i32 0 } diff --git a/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll b/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll index 949e1072b2b6c7..a5f2ec2593e3ce 100644 --- a/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll +++ b/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll @@ -1,11 +1,11 @@ ; RUN: llc -mtriple=arm-eabi %s -o /dev/null -define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>* %CONST) { +define void @execute_shader(ptr %OUT, ptr %IN, ptr %CONST) { entry: - %input2 = load <4 x float>, <4 x float>* null, align 16 ; <<4 x float>> [#uses=2] + %input2 = load <4 x float>, ptr null, align 16 ; <<4 x float>> [#uses=2] %shuffle7 = shufflevector <4 x float> %input2, <4 x float> , <4 x i32> ; <<4 x float>> [#uses=1] %mul1 = fmul <4 x float> %shuffle7, zeroinitializer ; <<4 x float>> [#uses=1] %add2 = fadd <4 x float> %mul1, %input2 ; <<4 x float>> [#uses=1] - store <4 x float> %add2, <4 x float>* null, align 16 + store <4 x float> %add2, ptr null, align 16 ret void } diff --git a/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll b/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll index f2532d798f834b..cd512eb10cdcac 100644 --- a/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll +++ b/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll @@ -3,10 +3,10 @@ define void @foo(...) nounwind { entry: - %rr = alloca i32 ; [#uses=2] - %0 = load i32, i32* %rr ; [#uses=1] + %rr = alloca i32 ; [#uses=2] + %0 = load i32, ptr %rr ; [#uses=1] %1 = call i32 asm "nop", "=r,0"(i32 %0) nounwind ; [#uses=1] - store i32 %1, i32* %rr + store i32 %1, ptr %rr br label %return return: ; preds = %entry diff --git a/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll b/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll index c50aa4a018be4b..99ab064ef92174 100644 --- a/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll +++ b/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll @@ -1,11 +1,11 @@ ; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi -mattr=+v6 ; PR4166 - %"byte[]" = type { i32, i8* } + %"byte[]" = type { i32, ptr } %tango.time.Time.Time = type { i64 } define fastcc void @t() { entry: - %tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval(%tango.time.Time.Time) null) ; [#uses=0] + %tmp28 = call fastcc i1 null(ptr null, %"byte[]" undef, %"byte[]" undef, ptr byval(%tango.time.Time.Time) null) ; [#uses=0] ret void } diff --git a/llvm/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll b/llvm/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll index ac641f99dbf9e8..bd48dcf8e0889f 100644 --- a/llvm/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll +++ b/llvm/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll @@ -1,12 +1,12 @@ ; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=fast ; PR4100 -@.str = external constant [30 x i8] ; <[30 x i8]*> [#uses=1] +@.str = external constant [30 x i8] ; [#uses=1] define i16 @fn16(i16 %arg0.0, <2 x i16> %arg1, i16 %arg2.0) nounwind { entry: - store <2 x i16> %arg1, <2 x i16>* null - %0 = call i32 (i8*, ...) @printf(i8* getelementptr ([30 x i8], [30 x i8]* @.str, i32 0, i32 0), i32 0) nounwind ; [#uses=0] + store <2 x i16> %arg1, ptr null + %0 = call i32 (ptr, ...) @printf(ptr @.str, i32 0) nounwind ; [#uses=0] ret i16 0 } -declare i32 @printf(i8*, ...) nounwind +declare i32 @printf(ptr, ...) nounwind diff --git a/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll b/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll index ae005dbf4b1364..a07af6afba31cf 100644 --- a/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll +++ b/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll @@ -1,17 +1,17 @@ ; RUN: llc -mtriple=arm-eabi %s -o /dev/null - %struct.List = type { %struct.List*, i32 } -@Node5 = external constant %struct.List ; <%struct.List*> [#uses=1] -@"\01LC" = external constant [7 x i8] ; <[7 x i8]*> [#uses=1] + %struct.List = type { ptr, i32 } +@Node5 = external constant %struct.List ; [#uses=1] +@"\01LC" = external constant [7 x i8] ; [#uses=1] define i32 @main() nounwind { entry: br label %bb bb: ; preds = %bb3, %entry - %CurL.02 = phi %struct.List* [ @Node5, %entry ], [ %2, %bb3 ] ; <%struct.List*> [#uses=1] - %PrevL.01 = phi %struct.List* [ null, %entry ], [ %CurL.02, %bb3 ] ; <%struct.List*> [#uses=1] - %0 = icmp eq %struct.List* %PrevL.01, null ; [#uses=1] + %CurL.02 = phi ptr [ @Node5, %entry ], [ %2, %bb3 ] ; [#uses=1] + %PrevL.01 = phi ptr [ null, %entry ], [ %CurL.02, %bb3 ] ; [#uses=1] + %0 = icmp eq ptr %PrevL.01, null ; [#uses=1] br i1 %0, label %bb3, label %bb1 bb1: ; preds = %bb @@ -19,13 +19,13 @@ bb1: ; preds = %bb bb3: ; preds = %bb1, %bb %iftmp.0.0 = phi i32 [ 0, %bb1 ], [ -1, %bb ] ; [#uses=1] - %1 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([7 x i8], [7 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 %iftmp.0.0) nounwind ; [#uses=0] - %2 = load %struct.List*, %struct.List** null, align 4 ; <%struct.List*> [#uses=2] - %phitmp = icmp eq %struct.List* %2, null ; [#uses=1] + %1 = tail call i32 (ptr, ...) @printf(ptr @"\01LC", i32 0, i32 %iftmp.0.0) nounwind ; [#uses=0] + %2 = load ptr, ptr null, align 4 ; [#uses=2] + %phitmp = icmp eq ptr %2, null ; [#uses=1] br i1 %phitmp, label %bb5, label %bb bb5: ; preds = %bb3 ret i32 0 } -declare i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(ptr nocapture, ...) nounwind diff --git a/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll b/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll index 2672aa317ba1ab..ae57c3a7dc5576 100644 --- a/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll +++ b/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll @@ -1,8 +1,8 @@ ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s ; PR4091 -define void @foo(i32 %i, i32* %p) nounwind { +define void @foo(i32 %i, ptr %p) nounwind { ;CHECK: swp r2, r0, [r1] - %asmtmp = call i32 asm sideeffect "swp $0, $2, $3", "=&r,=*m,r,*m,~{memory}"(i32* elementtype(i32) %p, i32 %i, i32* elementtype(i32) %p) nounwind + %asmtmp = call i32 asm sideeffect "swp $0, $2, $3", "=&r,=*m,r,*m,~{memory}"(ptr elementtype(i32) %p, i32 %i, ptr elementtype(i32) %p) nounwind ret void } diff --git a/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll b/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll index 7bbb8090c84912..391cbb1fb09e6b 100644 --- a/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll +++ b/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -mattr=+v6,+vfp2 -@"\01LC" = external constant [15 x i8] ; <[15 x i8]*> [#uses=1] +@"\01LC" = external constant [15 x i8] ; [#uses=1] -declare i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(ptr nocapture, ...) nounwind define i32 @main() nounwind { entry: @@ -57,6 +57,6 @@ Fft.exit.i: ; preds = %bb7.i.i br i1 undef, label %bb5.i, label %bb1.outer2.i.i.outer bb5.i: ; preds = %Fft.exit.i - %0 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([15 x i8], [15 x i8]* @"\01LC", i32 0, i32 0), double undef, double undef) nounwind ; [#uses=0] + %0 = tail call i32 (ptr, ...) @printf(ptr @"\01LC", double undef, double undef) nounwind ; [#uses=0] unreachable } diff --git a/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll b/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll index 17beb3c2594715..b03bfd519b9377 100644 --- a/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll +++ b/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll @@ -1,16 +1,16 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 %struct.anon = type { i16, i16 } - %struct.cab_archive = type { i32, i16, i16, i16, i16, i8, %struct.cab_folder*, %struct.cab_file* } - %struct.cab_file = type { i32, i16, i64, i8*, i32, i32, i32, %struct.cab_folder*, %struct.cab_file*, %struct.cab_archive*, %struct.cab_state* } - %struct.cab_folder = type { i16, i16, %struct.cab_archive*, i64, %struct.cab_folder* } - %struct.cab_state = type { i8*, i8*, [38912 x i8], i16, i16, i8*, i16 } - %struct.qtm_model = type { i32, i32, %struct.anon* } - %struct.qtm_stream = type { i32, i32, i8, i8*, i32, i32, i32, i16, i16, i16, i8, i32, i8*, i8*, i8*, i8*, i8*, i32, i32, i8, [42 x i32], [42 x i8], [27 x i8], [27 x i8], %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [25 x %struct.anon], [37 x %struct.anon], [43 x %struct.anon], [28 x %struct.anon], [8 x %struct.anon], %struct.cab_file*, i32 (%struct.cab_file*, i8*, i32)* } + %struct.cab_archive = type { i32, i16, i16, i16, i16, i8, ptr, ptr } + %struct.cab_file = type { i32, i16, i64, ptr, i32, i32, i32, ptr, ptr, ptr, ptr } + %struct.cab_folder = type { i16, i16, ptr, i64, ptr } + %struct.cab_state = type { ptr, ptr, [38912 x i8], i16, i16, ptr, i16 } + %struct.qtm_model = type { i32, i32, ptr } + %struct.qtm_stream = type { i32, i32, i8, ptr, i32, i32, i32, i16, i16, i16, i8, i32, ptr, ptr, ptr, ptr, ptr, i32, i32, i8, [42 x i32], [42 x i8], [27 x i8], [27 x i8], %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [25 x %struct.anon], [37 x %struct.anon], [43 x %struct.anon], [28 x %struct.anon], [8 x %struct.anon], ptr, ptr } -declare fastcc i32 @qtm_read_input(%struct.qtm_stream* nocapture) nounwind +declare fastcc i32 @qtm_read_input(ptr nocapture) nounwind -define fastcc i32 @qtm_decompress(%struct.qtm_stream* %qtm, i64 %out_bytes) nounwind { +define fastcc i32 @qtm_decompress(ptr %qtm, i64 %out_bytes) nounwind { entry: br i1 undef, label %bb245, label %bb3 @@ -136,7 +136,7 @@ bb138: ; preds = %bb77 br label %bb141 bb139: ; preds = %bb141 - %scevgep441442881 = load i16, i16* undef ; [#uses=1] + %scevgep441442881 = load i16, ptr undef ; [#uses=1] %1 = icmp ugt i16 %scevgep441442881, %0 ; [#uses=1] br i1 %1, label %bb141, label %bb142 @@ -225,7 +225,7 @@ bb187: ; preds = %bb195 br i1 undef, label %bb193, label %bb189 bb189: ; preds = %bb187 - %2 = tail call fastcc i32 @qtm_read_input(%struct.qtm_stream* %qtm) nounwind ; [#uses=0] + %2 = tail call fastcc i32 @qtm_read_input(ptr %qtm) nounwind ; [#uses=0] ret i32 undef bb193: ; preds = %bb187 diff --git a/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll index a0f903b0bdf564..07bdff382e9715 100644 --- a/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll @@ -2,23 +2,23 @@ %struct.term = type { i32, i32, i32 } -declare fastcc i8* @memory_Malloc(i32) nounwind +declare fastcc ptr @memory_Malloc(i32) nounwind -define fastcc %struct.term* @t1() nounwind { +define fastcc ptr @t1() nounwind { entry: br i1 undef, label %bb, label %bb1 bb: ; preds = %entry - ret %struct.term* undef + ret ptr undef bb1: ; preds = %entry - %0 = tail call fastcc i8* @memory_Malloc(i32 12) nounwind ; [#uses=0] - %1 = tail call fastcc i8* @memory_Malloc(i32 12) nounwind ; [#uses=0] - ret %struct.term* undef + %0 = tail call fastcc ptr @memory_Malloc(i32 12) nounwind ; [#uses=0] + %1 = tail call fastcc ptr @memory_Malloc(i32 12) nounwind ; [#uses=0] + ret ptr undef } -define i32 @t2(i32 %argc, i8** nocapture %argv) nounwind { +define i32 @t2(i32 %argc, ptr nocapture %argv) nounwind { entry: br label %bb6.i8 @@ -30,10 +30,10 @@ bb.i.i9: ; preds = %bb6.i8 memory_CalculateRealBlockSize1374.exit.i: ; preds = %bb.i.i9, %bb6.i8 %0 = phi i32 [ undef, %bb.i.i9 ], [ undef, %bb6.i8 ] ; [#uses=2] - store i32 %0, i32* undef, align 4 + store i32 %0, ptr undef, align 4 %1 = urem i32 8184, %0 ; [#uses=1] %2 = sub i32 8188, %1 ; [#uses=1] - store i32 %2, i32* undef, align 4 + store i32 %2, ptr undef, align 4 br i1 undef, label %memory_Init.exit, label %bb6.i8 memory_Init.exit: ; preds = %memory_CalculateRealBlockSize1374.exit.i diff --git a/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll b/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll index 4ab54c2e8faf8e..ebff4c2f663eec 100644 --- a/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll +++ b/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll @@ -3,11 +3,11 @@ %struct.rtunion = type { i64 } %struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] } -define void @simplify_unary_real(i8* nocapture %p) nounwind { +define void @simplify_unary_real(ptr nocapture %p) nounwind { entry: - %tmp121 = load i64, i64* null, align 4 ; [#uses=1] - %0 = getelementptr %struct.rtx_def, %struct.rtx_def* null, i32 0, i32 3, i32 3, i32 0 ; [#uses=1] - %tmp122 = load i64, i64* %0, align 4 ; [#uses=1] + %tmp121 = load i64, ptr null, align 4 ; [#uses=1] + %0 = getelementptr %struct.rtx_def, ptr null, i32 0, i32 3, i32 3, i32 0 ; [#uses=1] + %tmp122 = load i64, ptr %0, align 4 ; [#uses=1] %1 = zext i64 undef to i192 ; [#uses=2] %2 = zext i64 %tmp121 to i192 ; [#uses=1] %3 = shl i192 %2, 64 ; [#uses=2] diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll index a0e44ed86e0b36..52e47334dbc22d 100644 --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll @@ -1,18 +1,18 @@ ; RUN: llc < %s -mtriple=armv6-apple-darwin9 -@nn = external global i32 ; [#uses=1] -@al_len = external global i32 ; [#uses=2] -@no_mat = external global i32 ; [#uses=2] -@no_mis = external global i32 ; [#uses=2] -@"\01LC12" = external constant [29 x i8], align 1 ; <[29 x i8]*> [#uses=1] -@"\01LC16" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] -@"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1] +@nn = external global i32 ; [#uses=1] +@al_len = external global i32 ; [#uses=2] +@no_mat = external global i32 ; [#uses=2] +@no_mis = external global i32 ; [#uses=2] +@"\01LC12" = external constant [29 x i8], align 1 ; [#uses=1] +@"\01LC16" = external constant [33 x i8], align 1 ; [#uses=1] +@"\01LC17" = external constant [47 x i8], align 1 ; [#uses=1] -declare i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(ptr nocapture, ...) nounwind -declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind +declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind -define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -35,26 +35,26 @@ bb10: ; preds = %bb9 unreachable bb11: ; preds = %bb9 - %0 = load i32, i32* undef, align 4 ; [#uses=2] + %0 = load i32, ptr undef, align 4 ; [#uses=2] %1 = add i32 %0, 1 ; [#uses=2] - store i32 %1, i32* undef, align 4 - %2 = load i32, i32* undef, align 4 ; [#uses=1] - store i32 %2, i32* @nn, align 4 - store i32 0, i32* @al_len, align 4 - store i32 0, i32* @no_mat, align 4 - store i32 0, i32* @no_mis, align 4 - %3 = getelementptr i8, i8* %B, i32 %0 ; [#uses=1] - tail call void @diff(i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind + store i32 %1, ptr undef, align 4 + %2 = load i32, ptr undef, align 4 ; [#uses=1] + store i32 %2, ptr @nn, align 4 + store i32 0, ptr @al_len, align 4 + store i32 0, ptr @no_mat, align 4 + store i32 0, ptr @no_mis, align 4 + %3 = getelementptr i8, ptr %B, i32 %0 ; [#uses=1] + tail call void @diff(ptr undef, ptr %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind %4 = sitofp i32 undef to double ; [#uses=1] %5 = fdiv double %4, 1.000000e+01 ; [#uses=1] - %6 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([29 x i8], [29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; [#uses=0] - %7 = load i32, i32* @al_len, align 4 ; [#uses=1] - %8 = load i32, i32* @no_mat, align 4 ; [#uses=1] - %9 = load i32, i32* @no_mis, align 4 ; [#uses=1] + %6 = tail call i32 (ptr, ...) @printf(ptr @"\01LC12", double %5) nounwind ; [#uses=0] + %7 = load i32, ptr @al_len, align 4 ; [#uses=1] + %8 = load i32, ptr @no_mat, align 4 ; [#uses=1] + %9 = load i32, ptr @no_mis, align 4 ; [#uses=1] %10 = sub i32 %7, %8 ; [#uses=1] %11 = sub i32 %10, %9 ; [#uses=1] - %12 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; [#uses=0] - %13 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([47 x i8], [47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; [#uses=0] + %12 = tail call i32 (ptr, ...) @printf(ptr @"\01LC16", i32 %11) nounwind ; [#uses=0] + %13 = tail call i32 (ptr, ...) @printf(ptr @"\01LC17", i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; [#uses=0] br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll index d47d968ce3a877..b23030ec577111 100644 --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll @@ -1,16 +1,16 @@ ; RUN: llc < %s -mtriple=armv6-apple-darwin9 -@no_mat = external global i32 ; [#uses=1] -@no_mis = external global i32 ; [#uses=2] -@"\01LC11" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] -@"\01LC15" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] -@"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1] +@no_mat = external global i32 ; [#uses=1] +@no_mis = external global i32 ; [#uses=2] +@"\01LC11" = external constant [33 x i8], align 1 ; [#uses=1] +@"\01LC15" = external constant [33 x i8], align 1 ; [#uses=1] +@"\01LC17" = external constant [47 x i8], align 1 ; [#uses=1] -declare i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(ptr nocapture, ...) nounwind -declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind +declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind -define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -33,19 +33,19 @@ bb10: ; preds = %bb9 unreachable bb11: ; preds = %bb9 - %0 = load i32, i32* undef, align 4 ; [#uses=3] + %0 = load i32, ptr undef, align 4 ; [#uses=3] %1 = add i32 %0, 1 ; [#uses=2] - store i32 %1, i32* undef, align 4 - %2 = load i32, i32* undef, align 4 ; [#uses=2] + store i32 %1, ptr undef, align 4 + %2 = load i32, ptr undef, align 4 ; [#uses=2] %3 = sub i32 %2, %0 ; [#uses=1] - store i32 0, i32* @no_mat, align 4 - store i32 0, i32* @no_mis, align 4 - %4 = getelementptr i8, i8* %B, i32 %0 ; [#uses=1] - tail call void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind - %5 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; [#uses=0] - %6 = load i32, i32* @no_mis, align 4 ; [#uses=1] - %7 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; [#uses=0] - %8 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([47 x i8], [47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; [#uses=0] + store i32 0, ptr @no_mat, align 4 + store i32 0, ptr @no_mis, align 4 + %4 = getelementptr i8, ptr %B, i32 %0 ; [#uses=1] + tail call void @diff(ptr undef, ptr %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind + %5 = tail call i32 (ptr, ...) @printf(ptr @"\01LC11", i32 %tmp13) nounwind ; [#uses=0] + %6 = load i32, ptr @no_mis, align 4 ; [#uses=1] + %7 = tail call i32 (ptr, ...) @printf(ptr @"\01LC15", i32 %6) nounwind ; [#uses=0] + %8 = tail call i32 (ptr, ...) @printf(ptr @"\01LC17", i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; [#uses=0] br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll index d71744a28910d0..727db4a322fbfd 100644 --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -mtriple=armv6-apple-darwin9 -@JJ = external global i32* ; [#uses=1] +@JJ = external global ptr ; [#uses=1] -define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -28,7 +28,7 @@ bb11: ; preds = %bb9 br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 - %0 = load i32*, i32** @JJ, align 4 ; [#uses=1] + %0 = load ptr, ptr @JJ, align 4 ; [#uses=1] br label %bb228.i bb74.i: ; preds = %bb228.i @@ -84,22 +84,22 @@ bb167.i: ; preds = %bb163.i bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i %fi.5.i = phi i32 [ undef, %bb167.i ], [ %ci.910.i, %bb158.i ], [ undef, %bb160.i ], [ %ci.910.i, %bb161.i ], [ undef, %bb163.i ] ; [#uses=1] %fj.4.i = phi i32 [ undef, %bb167.i ], [ undef, %bb158.i ], [ %fj.515.i, %bb160.i ], [ undef, %bb161.i ], [ %fj.515.i, %bb163.i ] ; [#uses=2] - %scevgep88.i = getelementptr i32, i32* null, i32 %i.121.i ; [#uses=3] - %4 = load i32, i32* %scevgep88.i, align 4 ; [#uses=2] - %scevgep89.i = getelementptr i32, i32* %0, i32 %i.121.i ; [#uses=3] - %5 = load i32, i32* %scevgep89.i, align 4 ; [#uses=1] + %scevgep88.i = getelementptr i32, ptr null, i32 %i.121.i ; [#uses=3] + %4 = load i32, ptr %scevgep88.i, align 4 ; [#uses=2] + %scevgep89.i = getelementptr i32, ptr %0, i32 %i.121.i ; [#uses=3] + %5 = load i32, ptr %scevgep89.i, align 4 ; [#uses=1] %ci.10.i = select i1 undef, i32 %pi.316.i, i32 %i.121.i ; [#uses=0] %cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef ; [#uses=0] %6 = icmp slt i32 undef, 0 ; [#uses=3] %ci.12.i = select i1 %6, i32 %fi.5.i, i32 %4 ; [#uses=2] %cj.11.i100 = select i1 %6, i32 %fj.4.i, i32 %5 ; [#uses=1] %c.14.i = select i1 %6, i32 0, i32 undef ; [#uses=2] - store i32 %c.14.i, i32* undef, align 4 - %7 = load i32, i32* %scevgep88.i, align 4 ; [#uses=1] - %8 = load i32, i32* %scevgep89.i, align 4 ; [#uses=1] - store i32 %ci.12.i, i32* %scevgep88.i, align 4 - store i32 %cj.11.i100, i32* %scevgep89.i, align 4 - store i32 %4, i32* undef, align 4 + store i32 %c.14.i, ptr undef, align 4 + %7 = load i32, ptr %scevgep88.i, align 4 ; [#uses=1] + %8 = load i32, ptr %scevgep89.i, align 4 ; [#uses=1] + store i32 %ci.12.i, ptr %scevgep88.i, align 4 + store i32 %cj.11.i100, ptr %scevgep89.i, align 4 + store i32 %4, ptr undef, align 4 br i1 undef, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll index 04cbc27aac25cf..601e0da365394e 100644 --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll @@ -1,14 +1,14 @@ ; RUN: llc < %s -mtriple=armv6-apple-darwin9 -@r = external global i32 ; [#uses=1] -@qr = external global i32 ; [#uses=1] -@II = external global i32* ; [#uses=1] -@no_mis = external global i32 ; [#uses=1] -@name1 = external global i8* ; [#uses=1] +@r = external global i32 ; [#uses=1] +@qr = external global i32 ; [#uses=1] +@II = external global ptr ; [#uses=1] +@no_mis = external global i32 ; [#uses=1] +@name1 = external global ptr ; [#uses=1] -declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind +declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind -define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -22,7 +22,7 @@ bb6: ; preds = %bb6, %bb5 br i1 undef, label %bb8, label %bb6 bb8: ; preds = %bb6, %bb5 - %0 = load i8*, i8** @name1, align 4 ; [#uses=0] + %0 = load ptr, ptr @name1, align 4 ; [#uses=0] br label %bb15 bb9: ; preds = %bb15 @@ -32,16 +32,16 @@ bb10: ; preds = %bb9 unreachable bb11: ; preds = %bb9 - store i32 0, i32* @no_mis, align 4 - %1 = getelementptr i8, i8* %A, i32 0 ; [#uses=1] - %2 = getelementptr i8, i8* %B, i32 0 ; [#uses=1] - tail call void @diff(i8* %1, i8* %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind + store i32 0, ptr @no_mis, align 4 + %1 = getelementptr i8, ptr %A, i32 0 ; [#uses=1] + %2 = getelementptr i8, ptr %B, i32 0 ; [#uses=1] + tail call void @diff(ptr %1, ptr %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 - %3 = load i32*, i32** @II, align 4 ; [#uses=1] - %4 = load i32, i32* @r, align 4 ; [#uses=1] - %5 = load i32, i32* @qr, align 4 ; [#uses=1] + %3 = load ptr, ptr @II, align 4 ; [#uses=1] + %4 = load i32, ptr @r, align 4 ; [#uses=1] + %5 = load i32, ptr @qr, align 4 ; [#uses=1] br label %bb228.i bb74.i: ; preds = %bb228.i @@ -95,12 +95,12 @@ bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i %fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; [#uses=2] %fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; [#uses=2] %f.5.i = phi i32 [ %7, %bb167.i ], [ %8, %bb158.i ], [ %7, %bb160.i ], [ %7, %bb161.i ], [ %7, %bb163.i ] ; [#uses=2] - %scevgep88.i = getelementptr i32, i32* %3, i32 undef ; [#uses=1] + %scevgep88.i = getelementptr i32, ptr %3, i32 undef ; [#uses=1] %ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; [#uses=0] %ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; [#uses=1] %cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; [#uses=1] %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; [#uses=1] - %10 = load i32, i32* %scevgep88.i, align 4 ; [#uses=1] + %10 = load i32, ptr %scevgep88.i, align 4 ; [#uses=1] br i1 undef, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i @@ -110,8 +110,8 @@ bb218.i: ; preds = %bb211.i, %bb168.i br i1 undef, label %bb220.i, label %bb158.i bb220.i: ; preds = %bb218.i, %bb153.i - %11 = getelementptr i32, i32* null, i32 %6 ; [#uses=1] - store i32 undef, i32* %11, align 4 + %11 = getelementptr i32, ptr null, i32 %6 ; [#uses=1] + store i32 undef, ptr %11, align 4 br i1 undef, label %bb221.i, label %bb228.i bb221.i: ; preds = %bb220.i diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll index 4306210bc5a3a8..bfed01b20ccaff 100644 --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -mtriple=armv6-apple-darwin9 -@XX = external global i32* ; [#uses=1] +@XX = external global ptr ; [#uses=1] -define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -28,7 +28,7 @@ bb11: ; preds = %bb9 br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 - %0 = load i32*, i32** @XX, align 4 ; [#uses=0] + %0 = load ptr, ptr @XX, align 4 ; [#uses=0] br label %bb228.i bb74.i: ; preds = %bb228.i @@ -72,8 +72,8 @@ bb167.i: ; preds = %bb163.i bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i %f.5.i = phi i32 [ %1, %bb167.i ], [ %2, %bb158.i ], [ %1, %bb160.i ], [ %1, %bb161.i ], [ %1, %bb163.i ] ; [#uses=1] %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; [#uses=1] - store i32 %c.14.i, i32* undef, align 4 - store i32 undef, i32* null, align 4 + store i32 %c.14.i, ptr undef, align 4 + store i32 undef, ptr null, align 4 br i1 undef, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i diff --git a/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll b/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll index 730d3a302ae27f..9e5ad950a98c2d 100644 --- a/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll +++ b/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll @@ -1,10 +1,10 @@ ; RUN: llc < %s -mtriple=armv6-apple-darwin9 -@qr = external global i32 ; [#uses=1] -@II = external global i32* ; [#uses=1] -@JJ = external global i32* ; [#uses=1] +@qr = external global i32 ; [#uses=1] +@II = external global ptr ; [#uses=1] +@JJ = external global ptr ; [#uses=1] -define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -30,9 +30,9 @@ bb11: ; preds = %bb9 br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 - %0 = load i32*, i32** @II, align 4 ; [#uses=1] - %1 = load i32*, i32** @JJ, align 4 ; [#uses=1] - %2 = load i32, i32* @qr, align 4 ; [#uses=1] + %0 = load ptr, ptr @II, align 4 ; [#uses=1] + %1 = load ptr, ptr @JJ, align 4 ; [#uses=1] + %2 = load i32, ptr @qr, align 4 ; [#uses=1] br label %bb228.i bb74.i: ; preds = %bb228.i @@ -90,17 +90,17 @@ bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i %fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; [#uses=2] %fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; [#uses=2] %f.5.i = phi i32 [ %3, %bb167.i ], [ %4, %bb158.i ], [ %3, %bb160.i ], [ %3, %bb161.i ], [ %3, %bb163.i ] ; [#uses=2] - %scevgep88.i = getelementptr i32, i32* %0, i32 undef ; [#uses=2] - %scevgep89.i = getelementptr i32, i32* %1, i32 undef ; [#uses=2] + %scevgep88.i = getelementptr i32, ptr %0, i32 undef ; [#uses=2] + %scevgep89.i = getelementptr i32, ptr %1, i32 undef ; [#uses=2] %ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; [#uses=0] %cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef ; [#uses=0] %ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; [#uses=2] %cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; [#uses=2] %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; [#uses=1] - %6 = load i32, i32* %scevgep88.i, align 4 ; [#uses=1] - %7 = load i32, i32* %scevgep89.i, align 4 ; [#uses=1] - store i32 %ci.12.i, i32* %scevgep88.i, align 4 - store i32 %cj.11.i100, i32* %scevgep89.i, align 4 + %6 = load i32, ptr %scevgep88.i, align 4 ; [#uses=1] + %7 = load i32, ptr %scevgep89.i, align 4 ; [#uses=1] + store i32 %ci.12.i, ptr %scevgep88.i, align 4 + store i32 %cj.11.i100, ptr %scevgep89.i, align 4 br i1 undef, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i diff --git a/llvm/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll b/llvm/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll index 3cef0aa546a5a4..a52b3fa3f900f6 100644 --- a/llvm/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll +++ b/llvm/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null -define void @test(i8* %x) nounwind { +define void @test(ptr %x) nounwind { entry: - call void asm sideeffect "pld\09${0:a}", "r,~{cc}"(i8* %x) nounwind + call void asm sideeffect "pld\09${0:a}", "r,~{cc}"(ptr %x) nounwind ret void } diff --git a/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll index d746b104baf8ef..3da7c470b2de23 100644 --- a/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll @@ -1,14 +1,14 @@ ; RUN: llc < %s -mtriple=armv6-apple-darwin10 - %struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* } - %struct.cli_ac_node = type { i8, i8, %struct.cli_ac_patt*, %struct.cli_ac_node**, %struct.cli_ac_node* } - %struct.cli_ac_patt = type { i16*, i16*, i16, i16, i8, i32, i32, i8*, i8*, i32, i16, i16, i16, i16, %struct.cli_ac_alt**, i8, i16, %struct.cli_ac_patt*, %struct.cli_ac_patt* } - %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 } - %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 } + %struct.cli_ac_alt = type { i8, ptr, i16, i16, ptr } + %struct.cli_ac_node = type { i8, i8, ptr, ptr, ptr } + %struct.cli_ac_patt = type { ptr, ptr, i16, i16, i8, i32, i32, ptr, ptr, i32, i16, i16, i16, i16, ptr, i8, i16, ptr, ptr } + %struct.cli_bm_patt = type { ptr, ptr, i16, i16, ptr, ptr, i8, ptr, i16 } + %struct.cli_matcher = type { i16, i8, ptr, ptr, ptr, i32, i8, i8, ptr, ptr, ptr, i32, i32, i32 } -declare i32 @strlen(i8* nocapture) nounwind readonly +declare i32 @strlen(ptr nocapture) nounwind readonly -define i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { +define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target) nounwind { entry: br i1 undef, label %bb126, label %bb1 @@ -19,7 +19,7 @@ cli_calloc.exit.thread: ; preds = %bb1 ret i32 -114 cli_calloc.exit: ; preds = %bb1 - store i16 %parts, i16* undef, align 4 + store i16 %parts, ptr undef, align 4 br i1 undef, label %bb52, label %bb4 bb4: ; preds = %cli_calloc.exit @@ -83,10 +83,10 @@ bb45: ; preds = %bb43.preheader, %cli_calloc.exit54 br i1 undef, label %cli_calloc.exit70.thread, label %cli_calloc.exit70 bb52: ; preds = %cli_calloc.exit - %0 = load i16, i16* undef, align 4 ; [#uses=1] + %0 = load i16, ptr undef, align 4 ; [#uses=1] %1 = icmp eq i16 %0, 0 ; [#uses=1] - %iftmp.20.0 = select i1 %1, i8* %hexsig, i8* null ; [#uses=1] - %2 = tail call i32 @strlen(i8* %iftmp.20.0) nounwind readonly ; [#uses=0] + %iftmp.20.0 = select i1 %1, ptr %hexsig, ptr null ; [#uses=1] + %2 = tail call i32 @strlen(ptr %iftmp.20.0) nounwind readonly ; [#uses=0] unreachable bb126: ; preds = %entry diff --git a/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll b/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll index 156fd8843bcf68..e2a284813ebc1a 100644 --- a/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll @@ -1,12 +1,12 @@ ; RUN: llc -mtriple=arm-eabi %s -o /dev/null - %struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* } - %struct.cli_ac_node = type { i8, i8, %struct.cli_ac_patt*, %struct.cli_ac_node**, %struct.cli_ac_node* } - %struct.cli_ac_patt = type { i16*, i16*, i16, i16, i8, i32, i32, i8*, i8*, i32, i16, i16, i16, i16, %struct.cli_ac_alt**, i8, i16, %struct.cli_ac_patt*, %struct.cli_ac_patt* } - %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 } - %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 } + %struct.cli_ac_alt = type { i8, ptr, i16, i16, ptr } + %struct.cli_ac_node = type { i8, i8, ptr, ptr, ptr } + %struct.cli_ac_patt = type { ptr, ptr, i16, i16, i8, i32, i32, ptr, ptr, i32, i16, i16, i16, i16, ptr, i8, i16, ptr, ptr } + %struct.cli_bm_patt = type { ptr, ptr, i16, i16, ptr, ptr, i8, ptr, i16 } + %struct.cli_matcher = type { i16, i8, ptr, ptr, ptr, i32, i8, i8, ptr, ptr, ptr, i32, i32, i32 } -define i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { +define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target) nounwind { entry: br i1 undef, label %bb126, label %bb1 @@ -65,15 +65,14 @@ bb18: ; preds = %bb18, %bb.nph br i1 undef, label %bb18, label %bb22 bb22: ; preds = %bb18, %bb17 - %0 = getelementptr i8, i8* null, i32 10 ; [#uses=1] - %1 = bitcast i8* %0 to i16* ; [#uses=1] - %2 = load i16, i16* %1, align 2 ; [#uses=1] - %3 = add i16 %2, 1 ; [#uses=1] - %4 = zext i16 %3 to i32 ; [#uses=1] - %5 = mul i32 %4, 3 ; [#uses=1] - %6 = add i32 %5, -1 ; [#uses=1] - %7 = icmp eq i32 %6, undef ; [#uses=1] - br i1 %7, label %bb25, label %bb43.preheader + %0 = getelementptr i8, ptr null, i32 10 ; [#uses=1] + %1 = load i16, ptr %0, align 2 ; [#uses=1] + %2 = add i16 %1, 1 ; [#uses=1] + %3 = zext i16 %2 to i32 ; [#uses=1] + %4 = mul i32 %3, 3 ; [#uses=1] + %5 = add i32 %4, -1 ; [#uses=1] + %6 = icmp eq i32 %5, undef ; [#uses=1] + br i1 %6, label %bb25, label %bb43.preheader bb43.preheader: ; preds = %bb22 br i1 undef, label %bb28, label %bb45 diff --git a/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll b/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll index 01591c80362dad..c44681ab130844 100644 --- a/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll +++ b/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll @@ -1,10 +1,10 @@ ; RUN: llc < %s -mtriple=armv7-apple-darwin10 -mattr=+vfp3 -@a = external global double ; [#uses=1] +@a = external global double ; [#uses=1] declare double @llvm.exp.f64(double) nounwind readonly -define void @findratio(double* nocapture %res1, double* nocapture %res2) nounwind { +define void @findratio(ptr nocapture %res1, ptr nocapture %res2) nounwind { entry: br label %bb @@ -12,7 +12,7 @@ bb: ; preds = %bb, %entry br i1 undef, label %bb28, label %bb bb28: ; preds = %bb - %0 = load double, double* @a, align 4 ; [#uses=2] + %0 = load double, ptr @a, align 4 ; [#uses=2] %1 = fadd double %0, undef ; [#uses=2] br i1 undef, label %bb59, label %bb60 diff --git a/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll b/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll index 8ead42d82c7c63..b87f4f86d67de2 100644 --- a/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll +++ b/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll @@ -6,24 +6,24 @@ target triple = "armv7-apple-darwin9" define <4 x i32> @scale(<4 x i32> %v, i32 %f) nounwind { entry: - %v_addr = alloca <4 x i32> ; <<4 x i32>*> [#uses=2] - %f_addr = alloca i32 ; [#uses=2] - %retval = alloca <4 x i32> ; <<4 x i32>*> [#uses=2] - %0 = alloca <4 x i32> ; <<4 x i32>*> [#uses=2] + %v_addr = alloca <4 x i32> ; [#uses=2] + %f_addr = alloca i32 ; [#uses=2] + %retval = alloca <4 x i32> ; [#uses=2] + %0 = alloca <4 x i32> ; [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - store <4 x i32> %v, <4 x i32>* %v_addr - store i32 %f, i32* %f_addr - %1 = load <4 x i32>, <4 x i32>* %v_addr, align 16 ; <<4 x i32>> [#uses=1] - %2 = load i32, i32* %f_addr, align 4 ; [#uses=1] + store <4 x i32> %v, ptr %v_addr + store i32 %f, ptr %f_addr + %1 = load <4 x i32>, ptr %v_addr, align 16 ; <<4 x i32>> [#uses=1] + %2 = load i32, ptr %f_addr, align 4 ; [#uses=1] %3 = insertelement <4 x i32> undef, i32 %2, i32 0 ; <<4 x i32>> [#uses=1] %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>> [#uses=1] %5 = mul <4 x i32> %1, %4 ; <<4 x i32>> [#uses=1] - store <4 x i32> %5, <4 x i32>* %0, align 16 - %6 = load <4 x i32>, <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1] - store <4 x i32> %6, <4 x i32>* %retval, align 16 + store <4 x i32> %5, ptr %0, align 16 + %6 = load <4 x i32>, ptr %0, align 16 ; <<4 x i32>> [#uses=1] + store <4 x i32> %6, ptr %retval, align 16 br label %return return: ; preds = %entry - %retval1 = load <4 x i32>, <4 x i32>* %retval ; <<4 x i32>> [#uses=1] + %retval1 = load <4 x i32>, ptr %retval ; <<4 x i32>> [#uses=1] ret <4 x i32> %retval1 } diff --git a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll index 30975225c3edac..22fe8ea7a47740 100644 --- a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll +++ b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target triple = "armv6-elf" -define i32 @file_read_actor(i32* nocapture %desc, i32* %page, i32 %offset, i32 %size) nounwind optsize { +define i32 @file_read_actor(ptr nocapture %desc, ptr %page, i32 %offset, i32 %size) nounwind optsize { entry: br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i @@ -26,8 +26,8 @@ bb2: ; preds = %fault_in_pages_writeable.exit unreachable bb3: ; preds = %fault_in_pages_writeable.exit - %1 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; [#uses=0] + %1 = tail call i32 @__copy_to_user(ptr undef, ptr undef, i32 undef) nounwind ; [#uses=0] unreachable } -declare i32 @__copy_to_user(i8*, i8*, i32) +declare i32 @__copy_to_user(ptr, ptr, i32) diff --git a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll index d666f12b86a401..9ee9ec48b03a55 100644 --- a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll @@ -18,8 +18,8 @@ bb2: ; preds = %fault_in_pages_writeable.exit unreachable bb3: ; preds = %fault_in_pages_writeable.exit - %2 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; [#uses=0] + %2 = tail call i32 @__copy_to_user(ptr undef, ptr undef, i32 undef) nounwind ; [#uses=0] unreachable } -declare i32 @__copy_to_user(i8*, i8*, i32) +declare i32 @__copy_to_user(ptr, ptr, i32) diff --git a/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll b/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll index a5e9692a0082d1..a23100a36eff14 100644 --- a/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll +++ b/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll @@ -4,9 +4,9 @@ ; Inline asm is allowed to contain operands "=&r", "0". %struct.device_dma_parameters = type { i32, i32 } -%struct.iovec = type { i8*, i32 } +%struct.iovec = type { ptr, i32 } -define i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize { +define i32 @generic_segment_checks(ptr nocapture %iov, ptr nocapture %nr_segs, ptr nocapture %count, i32 %access_flags) nounwind optsize { entry: br label %bb8 @@ -14,7 +14,7 @@ bb: ; preds = %bb8 br i1 undef, label %bb10, label %bb2 bb2: ; preds = %bb - %asmtmp = tail call %struct.device_dma_parameters asm "adds $1, $2, $3; sbcccs $1, $1, $0; movcc $0, #0", "=&r,=&r,r,Ir,0,~{cc}"(i8* undef, i32 undef, i32 0) nounwind; <%struct.device_dma_parameters> [#uses=1] + %asmtmp = tail call %struct.device_dma_parameters asm "adds $1, $2, $3; sbcccs $1, $1, $0; movcc $0, #0", "=&r,=&r,r,Ir,0,~{cc}"(ptr undef, i32 undef, i32 0) nounwind; <%struct.device_dma_parameters> [#uses=1] %asmresult = extractvalue %struct.device_dma_parameters %asmtmp, 0; [#uses=1] %0 = icmp eq i32 %asmresult, 0 ; [#uses=1] br i1 %0, label %bb7, label %bb4 @@ -28,13 +28,13 @@ bb7: ; preds = %bb2 bb8: ; preds = %bb7, %entry %2 = phi i32 [ 0, %entry ], [ %1, %bb7 ] ; [#uses=3] - %scevgep22 = getelementptr %struct.iovec, %struct.iovec* %iov, i32 %2, i32 0; [#uses=0] - %3 = load i32, i32* %nr_segs, align 4 ; [#uses=1] + %scevgep22 = getelementptr %struct.iovec, ptr %iov, i32 %2, i32 0; [#uses=0] + %3 = load i32, ptr %nr_segs, align 4 ; [#uses=1] %4 = icmp ult i32 %2, %3 ; [#uses=1] br i1 %4, label %bb, label %bb9 bb9: ; preds = %bb8, %bb4 - store i32 undef, i32* %count, align 4 + store i32 undef, ptr %count, align 4 ret i32 0 bb10: ; preds = %bb4, %bb diff --git a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll index dea582968e957a..c759fb07ed113b 100644 --- a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll +++ b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll @@ -4,23 +4,23 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target triple = "armv7-apple-darwin9" -%struct.tree = type { i32, double, double, %struct.tree*, %struct.tree*, %struct.tree*, %struct.tree* } -@g = common global %struct.tree* null +%struct.tree = type { i32, double, double, ptr, ptr, ptr, ptr } +@g = common global ptr null -define %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind { +define ptr @tsp(ptr %t, i32 %nproc) nounwind { entry: - %t.idx51.val.i = load double, double* null ; [#uses=1] + %t.idx51.val.i = load double, ptr null ; [#uses=1] br i1 undef, label %bb4.i, label %bb.i bb.i: ; preds = %entry unreachable bb4.i: ; preds = %entry - %0 = load %struct.tree*, %struct.tree** @g, align 4 ; <%struct.tree*> [#uses=2] - %.idx45.i = getelementptr %struct.tree, %struct.tree* %0, i32 0, i32 1 ; [#uses=1] - %.idx45.val.i = load double, double* %.idx45.i ; [#uses=1] - %.idx46.i = getelementptr %struct.tree, %struct.tree* %0, i32 0, i32 2 ; [#uses=1] - %.idx46.val.i = load double, double* %.idx46.i ; [#uses=1] + %0 = load ptr, ptr @g, align 4 ; [#uses=2] + %.idx45.i = getelementptr %struct.tree, ptr %0, i32 0, i32 1 ; [#uses=1] + %.idx45.val.i = load double, ptr %.idx45.i ; [#uses=1] + %.idx46.i = getelementptr %struct.tree, ptr %0, i32 0, i32 2 ; [#uses=1] + %.idx46.val.i = load double, ptr %.idx46.i ; [#uses=1] %1 = fsub double 0.000000e+00, %.idx45.val.i ; [#uses=2] %2 = fmul double %1, %1 ; [#uses=1] %3 = fsub double %t.idx51.val.i, %.idx46.val.i ; [#uses=2] diff --git a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll index 4aa46d0000ced2..9aad73c771ad55 100644 --- a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll +++ b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll @@ -4,14 +4,14 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target triple = "armv7-apple-darwin9" -%struct.anon = type { [3 x double], double, %struct.node*, [64 x %struct.bnode*], [64 x %struct.bnode*] } -%struct.bnode = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, %struct.bnode*, %struct.bnode* } +%struct.anon = type { [3 x double], double, ptr, [64 x ptr], [64 x ptr] } +%struct.bnode = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, ptr, ptr } %struct.icstruct = type { [3 x i32], i16 } %struct.node = type { i16, double, [3 x double], i32, i32 } declare double @floor(double) nounwind readnone -define void @intcoord(%struct.icstruct* noalias nocapture sret(%struct.icstruct) %agg.result, i1 %a, double %b) { +define void @intcoord(ptr noalias nocapture sret(%struct.icstruct) %agg.result, i1 %a, double %b) { entry: br i1 %a, label %bb3, label %bb1 @@ -32,7 +32,7 @@ bb9: ; preds = %bb7 br label %bb11 bb11: ; preds = %bb9, %bb7 - %1 = getelementptr %struct.icstruct, %struct.icstruct* %agg.result, i32 0, i32 0, i32 0 ; [#uses=1] - store i32 0, i32* %1 + %1 = getelementptr %struct.icstruct, ptr %agg.result, i32 0, i32 0, i32 0 ; [#uses=1] + store i32 0, ptr %1 ret void } diff --git a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll index b7a252beefbda3..88fcae29c09fa1 100644 --- a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll +++ b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll @@ -5,29 +5,28 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f3 target triple = "armv7-apple-darwin9" %struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List } -%struct.List = type { %struct.List*, %struct.Patient*, %struct.List* } -%struct.Patient = type { i32, i32, i32, %struct.Village* } -%struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 } +%struct.List = type { ptr, ptr, ptr } +%struct.Patient = type { i32, i32, i32, ptr } +%struct.Village = type { [4 x ptr], ptr, %struct.List, %struct.Hosp, i32, i32 } -define %struct.Village* @alloc_tree(i32 %level, i32 %label, %struct.Village* %back, i1 %p) nounwind { +define ptr @alloc_tree(i32 %level, i32 %label, ptr %back, i1 %p) nounwind { entry: br i1 %p, label %bb8, label %bb1 bb1: ; preds = %entry - %malloccall = tail call i8* @malloc(i32 ptrtoint (%struct.Village* getelementptr (%struct.Village, %struct.Village* null, i32 1) to i32)) - %0 = bitcast i8* %malloccall to %struct.Village* + %malloccall = tail call ptr @malloc(i32 ptrtoint (ptr getelementptr (%struct.Village, ptr null, i32 1) to i32)) %exp2 = call double @ldexp(double 1.000000e+00, i32 %level) nounwind ; [#uses=1] %.c = fptosi double %exp2 to i32 ; [#uses=1] - store i32 %.c, i32* null - %1 = getelementptr %struct.Village, %struct.Village* %0, i32 0, i32 3, i32 6, i32 0 ; <%struct.List**> [#uses=1] - store %struct.List* null, %struct.List** %1 - %2 = getelementptr %struct.Village, %struct.Village* %0, i32 0, i32 3, i32 6, i32 2 ; <%struct.List**> [#uses=1] - store %struct.List* null, %struct.List** %2 - ret %struct.Village* %0 + store i32 %.c, ptr null + %0 = getelementptr %struct.Village, ptr %malloccall, i32 0, i32 3, i32 6, i32 0 ; [#uses=1] + store ptr null, ptr %0 + %1 = getelementptr %struct.Village, ptr %malloccall, i32 0, i32 3, i32 6, i32 2 ; [#uses=1] + store ptr null, ptr %1 + ret ptr %malloccall bb8: ; preds = %entry - ret %struct.Village* null + ret ptr null } declare double @ldexp(double, i32) -declare noalias i8* @malloc(i32) +declare noalias ptr @malloc(i32) diff --git a/llvm/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll b/llvm/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll index 773f7c71e3b943..c9ac8f0e8032e7 100644 --- a/llvm/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll +++ b/llvm/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll @@ -6,12 +6,12 @@ target triple = "thumbv7-elf" %bar = type { float, float, float } %baz = type { i32, [16 x %bar], [16 x float], [16 x i32], i8 } %foo = type { <4 x float> } -%quux = type { i32 (...)**, %baz*, i32 } +%quux = type { ptr, ptr, i32 } %quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo } declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone -define void @_ZN6squish10ClusterFit9Compress3EPv(%quuz* %this, i8* %block) { +define void @_ZN6squish10ClusterFit9Compress3EPv(ptr %this, ptr %block) { entry: %0 = lshr <4 x i32> zeroinitializer, %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <2 x i32> diff --git a/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll b/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll index d3e8340808447c..8b0743ad390c19 100644 --- a/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll +++ b/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll @@ -6,10 +6,10 @@ target triple = "thumbv7-elf" %bar = type { float, float, float } %baz = type { i32, [16 x %bar], [16 x float], [16 x i32], i8 } %foo = type { <4 x float> } -%quux = type { i32 (...)**, %baz*, i32 } +%quux = type { ptr, ptr, i32 } %quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo } -define void @aaaa(%quuz* %this, i8* %block) { +define void @aaaa(ptr %this, ptr %block) { entry: br i1 undef, label %bb.nph269, label %bb201 diff --git a/llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll b/llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll index 54db3a8b9016fc..73859a8be57588 100644 --- a/llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll +++ b/llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll @@ -7,85 +7,81 @@ ; CHECK: [[LSDA_LABEL]]: ; CHECK: .byte 255 @ @LPStart Encoding = omit -%struct.A = type { i32* } +%struct.A = type { ptr } -define void @"\01-[MyFunction Name:]"() personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) { +define void @"\01-[MyFunction Name:]"() personality ptr @__gxx_personality_sj0 { entry: %save_filt.1 = alloca i32 - %save_eptr.0 = alloca i8* + %save_eptr.0 = alloca ptr %a = alloca %struct.A - %eh_exception = alloca i8* + %eh_exception = alloca ptr %eh_selector = alloca i32 %"alloca point" = bitcast i32 0 to i32 - call void @_ZN1AC1Ev(%struct.A* %a) + call void @_ZN1AC1Ev(ptr %a) invoke void @_Z3barv() to label %invcont unwind label %lpad invcont: ; preds = %entry - call void @_ZN1AD1Ev(%struct.A* %a) nounwind + call void @_ZN1AD1Ev(ptr %a) nounwind br label %return bb: ; preds = %ppad - %eh_select = load i32, i32* %eh_selector - store i32 %eh_select, i32* %save_filt.1, align 4 - %eh_value = load i8*, i8** %eh_exception - store i8* %eh_value, i8** %save_eptr.0, align 4 - call void @_ZN1AD1Ev(%struct.A* %a) nounwind - %0 = load i8*, i8** %save_eptr.0, align 4 - store i8* %0, i8** %eh_exception, align 4 - %1 = load i32, i32* %save_filt.1, align 4 - store i32 %1, i32* %eh_selector, align 4 + %eh_select = load i32, ptr %eh_selector + store i32 %eh_select, ptr %save_filt.1, align 4 + %eh_value = load ptr, ptr %eh_exception + store ptr %eh_value, ptr %save_eptr.0, align 4 + call void @_ZN1AD1Ev(ptr %a) nounwind + %0 = load ptr, ptr %save_eptr.0, align 4 + store ptr %0, ptr %eh_exception, align 4 + %1 = load i32, ptr %save_filt.1, align 4 + store i32 %1, ptr %eh_selector, align 4 br label %Unwind return: ; preds = %invcont ret void lpad: ; preds = %entry - %exn = landingpad {i8*, i32} + %exn = landingpad {ptr, i32} cleanup - %eh_ptr = extractvalue {i8*, i32} %exn, 0 - store i8* %eh_ptr, i8** %eh_exception - %eh_select2 = extractvalue {i8*, i32} %exn, 1 - store i32 %eh_select2, i32* %eh_selector + %eh_ptr = extractvalue {ptr, i32} %exn, 0 + store ptr %eh_ptr, ptr %eh_exception + %eh_select2 = extractvalue {ptr, i32} %exn, 1 + store i32 %eh_select2, ptr %eh_selector br label %ppad ppad: ; preds = %lpad br label %bb Unwind: ; preds = %bb - %eh_ptr3 = load i8*, i8** %eh_exception - call void @_Unwind_SjLj_Resume(i8* %eh_ptr3) + %eh_ptr3 = load ptr, ptr %eh_exception + call void @_Unwind_SjLj_Resume(ptr %eh_ptr3) unreachable } -define linkonce_odr void @_ZN1AC1Ev(%struct.A* %this) { +define linkonce_odr void @_ZN1AC1Ev(ptr %this) { entry: - %this_addr = alloca %struct.A* + %this_addr = alloca ptr %"alloca point" = bitcast i32 0 to i32 - store %struct.A* %this, %struct.A** %this_addr - %0 = call i8* @_Znwm(i32 4) - %1 = bitcast i8* %0 to i32* - %2 = load %struct.A*, %struct.A** %this_addr, align 4 - %3 = getelementptr inbounds %struct.A, %struct.A* %2, i32 0, i32 0 - store i32* %1, i32** %3, align 4 + store ptr %this, ptr %this_addr + %0 = call ptr @_Znwm(i32 4) + %1 = load ptr, ptr %this_addr, align 4 + store ptr %0, ptr %1, align 4 br label %return return: ; preds = %entry ret void } -declare i8* @_Znwm(i32) +declare ptr @_Znwm(i32) -define linkonce_odr void @_ZN1AD1Ev(%struct.A* %this) nounwind { +define linkonce_odr void @_ZN1AD1Ev(ptr %this) nounwind { entry: - %this_addr = alloca %struct.A* + %this_addr = alloca ptr %"alloca point" = bitcast i32 0 to i32 - store %struct.A* %this, %struct.A** %this_addr - %0 = load %struct.A*, %struct.A** %this_addr, align 4 - %1 = getelementptr inbounds %struct.A, %struct.A* %0, i32 0, i32 0 - %2 = load i32*, i32** %1, align 4 - %3 = bitcast i32* %2 to i8* - call void @_ZdlPv(i8* %3) nounwind + store ptr %this, ptr %this_addr + %0 = load ptr, ptr %this_addr, align 4 + %1 = load ptr, ptr %0, align 4 + call void @_ZdlPv(ptr %1) nounwind br label %bb bb: ; preds = %entry @@ -95,12 +91,12 @@ return: ; preds = %bb ret void } -declare void @_ZdlPv(i8*) nounwind +declare void @_ZdlPv(ptr) nounwind declare void @_Z3barv() -declare i32 @llvm.eh.typeid.for(i8*) nounwind +declare i32 @llvm.eh.typeid.for(ptr) nounwind declare i32 @__gxx_personality_sj0(...) -declare void @_Unwind_SjLj_Resume(i8*) +declare void @_Unwind_SjLj_Resume(ptr) diff --git a/llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll b/llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll index a6d128d9e0ce60..45e0108f253c9c 100644 --- a/llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll +++ b/llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll @@ -1,10 +1,10 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; pr4843 -define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind { +define <4 x i16> @v2regbug(ptr %B) nounwind { ;CHECK-LABEL: v2regbug: ;CHECK: vzip.16 - %tmp1 = load <4 x i16>, <4 x i16>* %B + %tmp1 = load <4 x i16>, ptr %B %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> ret <4 x i16> %tmp2 } diff --git a/llvm/test/CodeGen/ARM/2009-09-09-AllOnes.ll b/llvm/test/CodeGen/ARM/2009-09-09-AllOnes.ll index 8522a779a42c4d..318f9549bae7fe 100644 --- a/llvm/test/CodeGen/ARM/2009-09-09-AllOnes.ll +++ b/llvm/test/CodeGen/ARM/2009-09-09-AllOnes.ll @@ -5,6 +5,6 @@ target triple = "thumbv7-elf" define void @foo() { entry: %0 = insertelement <4 x i32> undef, i32 -1, i32 3 - store <4 x i32> %0, <4 x i32>* undef, align 16 + store <4 x i32> %0, ptr undef, align 16 unreachable } diff --git a/llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll b/llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll index 3117b809e30a41..d6405a25b75c36 100644 --- a/llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll +++ b/llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll @@ -1,16 +1,16 @@ ; RUN: llc -O1 -mattr=+vfp2 -mtriple=arm-linux-gnueabi < %s | FileCheck %s ; pr4939 -define void @test(double* %x, double* %y) nounwind { - %1 = load double, double* %x - %2 = load double, double* %y +define void @test(ptr %x, ptr %y) nounwind { + %1 = load double, ptr %x + %2 = load double, ptr %y %3 = fsub double -0.000000e+00, %1 %4 = fcmp ugt double %2, %3 br i1 %4, label %bb1, label %bb2 bb1: ;CHECK: vstrhi - store double %1, double* %y + store double %1, ptr %y br label %bb2 bb2: diff --git a/llvm/test/CodeGen/ARM/2009-09-10-postdec.ll b/llvm/test/CodeGen/ARM/2009-09-10-postdec.ll index 66ffe6a1a0fbf6..8a27eca41f1ff6 100644 --- a/llvm/test/CodeGen/ARM/2009-09-10-postdec.ll +++ b/llvm/test/CodeGen/ARM/2009-09-10-postdec.ll @@ -1,11 +1,11 @@ ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s ; Radar 7213850 -define i32 @test(i8* %d, i32 %x, i32 %y) nounwind { - %1 = ptrtoint i8* %d to i32 +define i32 @test(ptr %d, i32 %x, i32 %y) nounwind { + %1 = ptrtoint ptr %d to i32 ;CHECK: sub %2 = sub i32 %x, %1 %3 = add nsw i32 %2, %y - store i8 0, i8* %d, align 1 + store i8 0, ptr %d, align 1 ret i32 %3 } diff --git a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll index de927a8f8b6627..b701c00ca50b10 100644 --- a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll +++ b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll @@ -11,12 +11,12 @@ target triple = "armv7-eabi" declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone -define arm_aapcs_vfpcc i8 @foo(%struct.fr* nocapture %this, %struct.obb* %box) nounwind { +define arm_aapcs_vfpcc i8 @foo(ptr nocapture %this, ptr %box) nounwind { entry: - %val.i.i = load <4 x float>, <4 x float>* undef ; <<4 x float>> [#uses=1] - %val2.i.i = load <4 x float>, <4 x float>* null ; <<4 x float>> [#uses=1] - %elt3.i.i = getelementptr inbounds %struct.obb, %struct.obb* %box, i32 0, i32 0, i32 2, i32 0 ; <<4 x float>*> [#uses=1] - %val4.i.i = load <4 x float>, <4 x float>* %elt3.i.i ; <<4 x float>> [#uses=1] + %val.i.i = load <4 x float>, ptr undef ; <<4 x float>> [#uses=1] + %val2.i.i = load <4 x float>, ptr null ; <<4 x float>> [#uses=1] + %elt3.i.i = getelementptr inbounds %struct.obb, ptr %box, i32 0, i32 0, i32 2, i32 0 ; [#uses=1] + %val4.i.i = load <4 x float>, ptr %elt3.i.i ; <<4 x float>> [#uses=1] %0 = shufflevector <2 x float> undef, <2 x float> zeroinitializer, <4 x i32> ; <<4 x float>> [#uses=1] %1 = fadd <4 x float> undef, zeroinitializer ; <<4 x float>> [#uses=1] br label %bb33 diff --git a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll index b8a1479fd34c9e..c57965fc6eb671 100644 --- a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll +++ b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll @@ -1,28 +1,28 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a9 %s -o /dev/null -define arm_aapcs_vfpcc <4 x float> @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind { - %1 = ptrtoint i8* %pBuffer to i32 +define arm_aapcs_vfpcc <4 x float> @foo(ptr nocapture %pBuffer, i32 %numItems) nounwind { + %1 = ptrtoint ptr %pBuffer to i32 - %lsr.iv2641 = inttoptr i32 %1 to float* + %lsr.iv2641 = inttoptr i32 %1 to ptr %tmp29 = add i32 %1, 4 - %tmp2930 = inttoptr i32 %tmp29 to float* + %tmp2930 = inttoptr i32 %tmp29 to ptr %tmp31 = add i32 %1, 8 - %tmp3132 = inttoptr i32 %tmp31 to float* + %tmp3132 = inttoptr i32 %tmp31 to ptr %tmp33 = add i32 %1, 12 - %tmp3334 = inttoptr i32 %tmp33 to float* + %tmp3334 = inttoptr i32 %tmp33 to ptr %tmp35 = add i32 %1, 16 - %tmp3536 = inttoptr i32 %tmp35 to float* + %tmp3536 = inttoptr i32 %tmp35 to ptr %tmp37 = add i32 %1, 20 - %tmp3738 = inttoptr i32 %tmp37 to float* + %tmp3738 = inttoptr i32 %tmp37 to ptr %tmp39 = add i32 %1, 24 - %tmp3940 = inttoptr i32 %tmp39 to float* - %2 = load float, float* %lsr.iv2641, align 4 - %3 = load float, float* %tmp2930, align 4 - %4 = load float, float* %tmp3132, align 4 - %5 = load float, float* %tmp3334, align 4 - %6 = load float, float* %tmp3536, align 4 - %7 = load float, float* %tmp3738, align 4 - %8 = load float, float* %tmp3940, align 4 + %tmp3940 = inttoptr i32 %tmp39 to ptr + %2 = load float, ptr %lsr.iv2641, align 4 + %3 = load float, ptr %tmp2930, align 4 + %4 = load float, ptr %tmp3132, align 4 + %5 = load float, ptr %tmp3334, align 4 + %6 = load float, ptr %tmp3536, align 4 + %7 = load float, ptr %tmp3738, align 4 + %8 = load float, ptr %tmp3940, align 4 %9 = insertelement <4 x float> undef, float %6, i32 0 %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> zeroinitializer %11 = insertelement <4 x float> %10, float %7, i32 1 diff --git a/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll b/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll index 980f8ce6fa1b23..a024627ef8435a 100644 --- a/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll +++ b/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll @@ -2,7 +2,7 @@ ; PR4986 -define arm_aapcs_vfpcc void @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind { +define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems) nounwind { entry: br i1 undef, label %return, label %bb.preheader @@ -16,14 +16,14 @@ bb: ; preds = %bb, %bb.preheader %3 = insertelement <4 x float> %2, float undef, i32 3 ; <<4 x float>> [#uses=1] %4 = fmul <4 x float> undef, %3 ; <<4 x float>> [#uses=1] %5 = extractelement <4 x float> %4, i32 3 ; [#uses=1] - store float %5, float* undef, align 4 + store float %5, ptr undef, align 4 br i1 undef, label %return, label %bb return: ; preds = %bb, %entry ret void } -define arm_aapcs_vfpcc <4 x float> @bar(i8* nocapture %pBuffer, i32 %numItems) nounwind { +define arm_aapcs_vfpcc <4 x float> @bar(ptr nocapture %pBuffer, i32 %numItems) nounwind { %1 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %2 = insertelement <4 x float> %1, float undef, i32 1 ; <<4 x float>> [#uses=1] %3 = insertelement <4 x float> %2, float undef, i32 2 ; <<4 x float>> [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll b/llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll index eec0afcb894018..5728a6109b0f7a 100644 --- a/llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll +++ b/llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll @@ -5,10 +5,10 @@ %bar = type { <4 x float> } %foo = type { %bar, %bar, %bar, %bar } -declare arm_aapcs_vfpcc <4 x float> @bbb(%bar*) nounwind +declare arm_aapcs_vfpcc <4 x float> @bbb(ptr) nounwind -define arm_aapcs_vfpcc void @aaa(%foo* noalias sret(%foo) %agg.result, %foo* %tfrm) nounwind { +define arm_aapcs_vfpcc void @aaa(ptr noalias sret(%foo) %agg.result, ptr %tfrm) nounwind { entry: - %0 = call arm_aapcs_vfpcc <4 x float> @bbb(%bar* undef) nounwind ; <<4 x float>> [#uses=0] + %0 = call arm_aapcs_vfpcc <4 x float> @bbb(ptr undef) nounwind ; <<4 x float>> [#uses=0] ret void } diff --git a/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll b/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll index 30931a2ffb66db..0ef744bba56e2b 100644 --- a/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll +++ b/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll @@ -5,17 +5,17 @@ %bar = type { %foo, %foo } %foo = type { <4 x float> } -declare arm_aapcs_vfpcc float @aaa(%foo* nocapture) nounwind readonly +declare arm_aapcs_vfpcc float @aaa(ptr nocapture) nounwind readonly -declare arm_aapcs_vfpcc %bar* @bbb(%bar*, <4 x float>, <4 x float>) nounwind +declare arm_aapcs_vfpcc ptr @bbb(ptr, <4 x float>, <4 x float>) nounwind -define arm_aapcs_vfpcc void @ccc(i8* nocapture %pBuffer, i32 %numItems) nounwind { +define arm_aapcs_vfpcc void @ccc(ptr nocapture %pBuffer, i32 %numItems) nounwind { entry: br i1 undef, label %return, label %bb.nph bb.nph: ; preds = %entry - %0 = call arm_aapcs_vfpcc %bar* @bbb(%bar* undef, <4 x float> undef, <4 x float> undef) nounwind ; <%bar*> [#uses=0] - %1 = call arm_aapcs_vfpcc float @aaa(%foo* undef) nounwind ; [#uses=0] + %0 = call arm_aapcs_vfpcc ptr @bbb(ptr undef, <4 x float> undef, <4 x float> undef) nounwind ; [#uses=0] + %1 = call arm_aapcs_vfpcc float @aaa(ptr undef) nounwind ; [#uses=0] unreachable return: ; preds = %entry diff --git a/llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll b/llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll index 4bbd047056438d..de5e8bd7e7b4de 100644 --- a/llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll +++ b/llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll @@ -5,17 +5,17 @@ %struct.1 = type { %struct.4, %struct.4 } %struct.4 = type { <4 x float> } -define arm_aapcs_vfpcc %struct.1* @hhh3(%struct.1* %this, <4 x float> %lenation.0, <4 x float> %legalation.0) nounwind { +define arm_aapcs_vfpcc ptr @hhh3(ptr %this, <4 x float> %lenation.0, <4 x float> %legalation.0) nounwind { entry: - %0 = call arm_aapcs_vfpcc %struct.4* @sss1(%struct.4* undef, float 0.000000e+00) nounwind ; <%struct.4*> [#uses=0] - %1 = call arm_aapcs_vfpcc %struct.4* @qqq1(%struct.4* null, float 5.000000e-01) nounwind ; <%struct.4*> [#uses=0] - %val92 = load <4 x float>, <4 x float>* null ; <<4 x float>> [#uses=1] - %2 = call arm_aapcs_vfpcc %struct.4* @zzz2(%struct.4* undef, <4 x float> %val92) nounwind ; <%struct.4*> [#uses=0] - ret %struct.1* %this + %0 = call arm_aapcs_vfpcc ptr @sss1(ptr undef, float 0.000000e+00) nounwind ; [#uses=0] + %1 = call arm_aapcs_vfpcc ptr @qqq1(ptr null, float 5.000000e-01) nounwind ; [#uses=0] + %val92 = load <4 x float>, ptr null ; <<4 x float>> [#uses=1] + %2 = call arm_aapcs_vfpcc ptr @zzz2(ptr undef, <4 x float> %val92) nounwind ; [#uses=0] + ret ptr %this } -declare arm_aapcs_vfpcc %struct.4* @qqq1(%struct.4*, float) nounwind +declare arm_aapcs_vfpcc ptr @qqq1(ptr, float) nounwind -declare arm_aapcs_vfpcc %struct.4* @sss1(%struct.4*, float) nounwind +declare arm_aapcs_vfpcc ptr @sss1(ptr, float) nounwind -declare arm_aapcs_vfpcc %struct.4* @zzz2(%struct.4*, <4 x float>) nounwind +declare arm_aapcs_vfpcc ptr @zzz2(ptr, <4 x float>) nounwind diff --git a/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll b/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll index 4502542809f75a..5767cbbc20fb2c 100644 --- a/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll +++ b/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll @@ -3,13 +3,13 @@ define void @test_vget_lanep16() nounwind { entry: - %arg0_poly16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1] - %out_poly16_t = alloca i16 ; [#uses=1] + %arg0_poly16x4_t = alloca <4 x i16> ; [#uses=1] + %out_poly16_t = alloca i16 ; [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] ; CHECK: vldr - %0 = load <4 x i16>, <4 x i16>* %arg0_poly16x4_t, align 8 ; <<4 x i16>> [#uses=1] + %0 = load <4 x i16>, ptr %arg0_poly16x4_t, align 8 ; <<4 x i16>> [#uses=1] %1 = extractelement <4 x i16> %0, i32 1 ; [#uses=1] - store i16 %1, i16* %out_poly16_t, align 2 + store i16 %1, ptr %out_poly16_t, align 2 br label %return return: ; preds = %entry diff --git a/llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll b/llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll index 8bf73e924b7ca3..a813f3afd8bab6 100644 --- a/llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll +++ b/llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll @@ -3,7 +3,7 @@ %0 = type { double, double } -define void @foo(%0* noalias nocapture sret(%0) %agg.result, double %x.0, double %y.0) nounwind { +define void @foo(ptr noalias nocapture sret(%0) %agg.result, double %x.0, double %y.0) nounwind { ; CHECK-LABEL: foo: ; CHECK: bl __aeabi_dadd ; CHECK-NOT: strd @@ -11,9 +11,9 @@ define void @foo(%0* noalias nocapture sret(%0) %agg.result, double %x.0, double %x76 = fmul double %y.0, 0.000000e+00 ; [#uses=1] %x77 = fadd double %y.0, 0.000000e+00 ; [#uses=1] %tmpr = fadd double %x.0, %x76 ; [#uses=1] - %agg.result.0 = getelementptr %0, %0* %agg.result, i32 0, i32 0 ; [#uses=1] - store double %tmpr, double* %agg.result.0, align 8 - %agg.result.1 = getelementptr %0, %0* %agg.result, i32 0, i32 1 ; [#uses=1] - store double %x77, double* %agg.result.1, align 8 + %agg.result.0 = getelementptr %0, ptr %agg.result, i32 0, i32 0 ; [#uses=1] + store double %tmpr, ptr %agg.result.0, align 8 + %agg.result.1 = getelementptr %0, ptr %agg.result, i32 0, i32 1 ; [#uses=1] + store double %x77, ptr %agg.result.1, align 8 ret void } diff --git a/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll b/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll index 641036f684b95c..484ad93bebeaba 100644 --- a/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll +++ b/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll @@ -1,13 +1,13 @@ ; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 -enable-unsafe-fp-math < %s ; PR5367 -define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(i8* nocapture %pBuffer, i32 %numItems) nounwind { +define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(ptr nocapture %pBuffer, i32 %numItems) nounwind { entry: br i1 undef, label %return, label %bb bb: ; preds = %bb, %entry - %0 = load float, float* undef, align 4 ; [#uses=1] - %1 = load float, float* null, align 4 ; [#uses=1] + %0 = load float, ptr undef, align 4 ; [#uses=1] + %1 = load float, ptr null, align 4 ; [#uses=1] %2 = insertelement <4 x float> undef, float undef, i32 1 ; <<4 x float>> [#uses=1] %3 = insertelement <4 x float> %2, float %1, i32 2 ; <<4 x float>> [#uses=2] %4 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1] @@ -50,10 +50,10 @@ bb: ; preds = %bb, %entry %41 = fadd <4 x float> %40, zeroinitializer ; <<4 x float>> [#uses=1] %42 = shufflevector <4 x float> undef, <4 x float> %41, <4 x i32> ; <<4 x float>> [#uses=1] %43 = fmul <4 x float> %42, %31 ; <<4 x float>> [#uses=1] - store float undef, float* undef, align 4 - store float 0.000000e+00, float* null, align 4 + store float undef, ptr undef, align 4 + store float 0.000000e+00, ptr null, align 4 %44 = extractelement <4 x float> %43, i32 1 ; [#uses=1] - store float %44, float* undef, align 4 + store float %44, ptr undef, align 4 br i1 undef, label %return, label %bb return: ; preds = %bb, %entry diff --git a/llvm/test/CodeGen/ARM/2009-10-16-Scope.ll b/llvm/test/CodeGen/ARM/2009-10-16-Scope.ll index 3e687322de4fe4..c01f3bf352b180 100644 --- a/llvm/test/CodeGen/ARM/2009-10-16-Scope.ll +++ b/llvm/test/CodeGen/ARM/2009-10-16-Scope.ll @@ -5,12 +5,12 @@ define void @bar() nounwind ssp { entry: - %count_ = alloca i32, align 4 ; [#uses=2] + %count_ = alloca i32, align 4 ; [#uses=2] br label %do.body, !dbg !0 do.body: ; preds = %entry - call void @llvm.dbg.declare(metadata i32* %count_, metadata !4, metadata !DIExpression()), !dbg !DILocation(scope: !5) - %conv = ptrtoint i32* %count_ to i32, !dbg !0 ; [#uses=1] + call void @llvm.dbg.declare(metadata ptr %count_, metadata !4, metadata !DIExpression()), !dbg !DILocation(scope: !5) + %conv = ptrtoint ptr %count_ to i32, !dbg !0 ; [#uses=1] %call = call i32 @foo(i32 %conv) ssp, !dbg !0 ; [#uses=0] br label %do.end, !dbg !0 diff --git a/llvm/test/CodeGen/ARM/2009-10-27-double-align.ll b/llvm/test/CodeGen/ARM/2009-10-27-double-align.ll index 98a89a07af6f31..8bdd97bdc36a7f 100644 --- a/llvm/test/CodeGen/ARM/2009-10-27-double-align.ll +++ b/llvm/test/CodeGen/ARM/2009-10-27-double-align.ll @@ -10,8 +10,8 @@ entry: ;NOREGALLOC: [sp] ;REGALLOC: [sp] ;REGALLOC: [sp, #12] - tail call void (i8*, ...) @f(i8* getelementptr ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) + tail call void (ptr, ...) @f(ptr @.str, i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) ret void } -declare void @f(i8*, ...) +declare void @f(ptr, ...) diff --git a/llvm/test/CodeGen/ARM/2009-10-30.ll b/llvm/test/CodeGen/ARM/2009-10-30.ll index e46ab1eb2ab938..39aeb2690f050a 100644 --- a/llvm/test/CodeGen/ARM/2009-10-30.ll +++ b/llvm/test/CodeGen/ARM/2009-10-30.ll @@ -8,10 +8,9 @@ entry: ;CHECK: add r{{[0-9]+}}, sp, #8 ;CHECK: str r{{[0-9]+}}, [sp], #4 ;CHECK: bx lr - %ap = alloca i8*, align 4 - %ap1 = bitcast i8** %ap to i8* - call void @llvm.va_start(i8* %ap1) + %ap = alloca ptr, align 4 + call void @llvm.va_start(ptr %ap) ret void } -declare void @llvm.va_start(i8*) nounwind +declare void @llvm.va_start(ptr) nounwind diff --git a/llvm/test/CodeGen/ARM/2009-11-01-NeonMoves.ll b/llvm/test/CodeGen/ARM/2009-11-01-NeonMoves.ll index abc815bb8a8b80..7c11d9a884835e 100644 --- a/llvm/test/CodeGen/ARM/2009-11-01-NeonMoves.ll +++ b/llvm/test/CodeGen/ARM/2009-11-01-NeonMoves.ll @@ -5,12 +5,12 @@ target triple = "armv7-eabi" %foo = type { <4 x float> } -define arm_aapcs_vfpcc void @bar(%foo* noalias sret(%foo) %agg.result, <4 x float> %quat.0) nounwind { +define arm_aapcs_vfpcc void @bar(ptr noalias sret(%foo) %agg.result, <4 x float> %quat.0) nounwind { entry: - %quat_addr = alloca %foo, align 16 ; <%foo*> [#uses=2] - %0 = getelementptr inbounds %foo, %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1] - store <4 x float> %quat.0, <4 x float>* %0 - %1 = call arm_aapcs_vfpcc <4 x float> @quux(%foo* %quat_addr) nounwind ; <<4 x float>> [#uses=3] + %quat_addr = alloca %foo, align 16 ; [#uses=2] + %0 = getelementptr inbounds %foo, ptr %quat_addr, i32 0, i32 0 ; [#uses=1] + store <4 x float> %quat.0, ptr %0 + %1 = call arm_aapcs_vfpcc <4 x float> @quux(ptr %quat_addr) nounwind ; <<4 x float>> [#uses=3] %2 = fmul <4 x float> %1, %1 ; <<4 x float>> [#uses=2] %3 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> ; <<2 x float>> [#uses=1] %4 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> ; <<2 x float>> [#uses=1] @@ -25,13 +25,13 @@ entry: %10 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %9, <4 x float> %7) nounwind ; <<4 x float>> [#uses=1] %11 = fmul <4 x float> %10, %8 ; <<4 x float>> [#uses=1] %12 = fmul <4 x float> %11, %1 ; <<4 x float>> [#uses=1] - %13 = call arm_aapcs_vfpcc %foo* @baz(%foo* %agg.result, <4 x float> %12) nounwind ; <%foo*> [#uses=0] + %13 = call arm_aapcs_vfpcc ptr @baz(ptr %agg.result, <4 x float> %12) nounwind ; [#uses=0] ret void } -declare arm_aapcs_vfpcc %foo* @baz(%foo*, <4 x float>) nounwind +declare arm_aapcs_vfpcc ptr @baz(ptr, <4 x float>) nounwind -declare arm_aapcs_vfpcc <4 x float> @quux(%foo* nocapture) nounwind readonly +declare arm_aapcs_vfpcc <4 x float> @quux(ptr nocapture) nounwind readonly declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone diff --git a/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll b/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll index 154cd65e4ec1b7..ff182aeb9cbf58 100644 --- a/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll +++ b/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll @@ -2,18 +2,18 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "armv7-eabi" -define arm_aapcs_vfpcc void @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind { +define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems) nounwind { entry: br i1 undef, label %return, label %bb bb: ; preds = %bb, %entry ; CHECK: vld1.16 {d16[], d17[]} - %0 = load i16, i16* undef, align 2 + %0 = load i16, ptr undef, align 2 %1 = insertelement <8 x i16> undef, i16 %0, i32 2 %2 = insertelement <8 x i16> %1, i16 undef, i32 3 %3 = mul <8 x i16> %2, %2 %4 = extractelement <8 x i16> %3, i32 2 - store i16 %4, i16* undef, align 2 + store i16 %4, ptr undef, align 2 br i1 undef, label %return, label %bb return: ; preds = %bb, %entry diff --git a/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll b/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll index c4d03479a2ba5f..4a23448a0aaed2 100644 --- a/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll +++ b/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll @@ -6,7 +6,7 @@ target triple = "armv7-eabi" define arm_aapcs_vfpcc void @foo() { entry: - %0 = load float, float* null, align 4 ; [#uses=2] + %0 = load float, ptr null, align 4 ; [#uses=2] %1 = fmul float %0, %0 ; [#uses=2] %2 = fmul float 0.000000e+00, %1 ; [#uses=2] %3 = fmul float %0, %1 ; [#uses=1] @@ -18,7 +18,7 @@ entry: %7 = fsub float %2, %2 ; [#uses=1] %8 = fsub float 0.000000e+00, %7 ; [#uses=3] %9 = fadd float %2, %2 ; [#uses=3] - %10 = load float, float* undef, align 8 ; [#uses=3] + %10 = load float, ptr undef, align 8 ; [#uses=3] %11 = fmul float %8, %10 ; [#uses=1] %12 = fadd float %11, %11 ; [#uses=2] %13 = fmul float %12, %12 ; [#uses=1] @@ -30,10 +30,10 @@ entry: %19 = fadd float %18, 0.000000e+00 ; [#uses=1] %20 = fmul float %10, %10 ; [#uses=1] %21 = fadd float %19, %20 ; [#uses=1] - %22 = load float, float* undef, align 8 ; [#uses=1] + %22 = load float, ptr undef, align 8 ; [#uses=1] %23 = fmul float %5, %22 ; [#uses=1] %24 = fadd float %23, %23 ; [#uses=1] - %25 = load float, float* undef, align 8 ; [#uses=2] + %25 = load float, ptr undef, align 8 ; [#uses=2] %26 = fmul float %8, %25 ; [#uses=1] %27 = fadd float %24, %26 ; [#uses=1] %28 = fmul float %9, %25 ; [#uses=1] @@ -49,18 +49,18 @@ entry: %38 = fadd float %36, %37 ; [#uses=1] %39 = fmul float %38, %38 ; [#uses=1] %40 = fadd float %38, %39 ; [#uses=1] - store float %12, float* undef, align 8 - store float %17, float* undef, align 4 - store float %21, float* undef, align 8 - store float %27, float* undef, align 8 - store float %29, float* undef, align 4 - store float %31, float* undef, align 8 - store float %40, float* undef, align 8 - store float %12, float* null, align 8 + store float %12, ptr undef, align 8 + store float %17, ptr undef, align 4 + store float %21, ptr undef, align 8 + store float %27, ptr undef, align 8 + store float %29, ptr undef, align 4 + store float %31, ptr undef, align 8 + store float %40, ptr undef, align 8 + store float %12, ptr null, align 8 %41 = fmul float %17, %17 ; [#uses=1] %42 = fadd float %41, %41 ; [#uses=1] %43 = fmul float %35, %35 ; [#uses=1] %44 = fadd float %42, %43 ; [#uses=1] - store float %44, float* null, align 4 + store float %44, ptr null, align 4 unreachable } diff --git a/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll b/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll index efc4be11581cf3..f6ee605c026eae 100644 --- a/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll +++ b/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll @@ -5,16 +5,16 @@ %pln = type { %vec, float } %vec = type { [4 x float] } -define arm_aapcs_vfpcc float @aaa(%vec* nocapture %ustart, %vec* nocapture %udir, %vec* nocapture %vstart, %vec* nocapture %vdir, %vec* %upoint, %vec* %vpoint) { +define arm_aapcs_vfpcc float @aaa(ptr nocapture %ustart, ptr nocapture %udir, ptr nocapture %vstart, ptr nocapture %vdir, ptr %upoint, ptr %vpoint) { entry: br i1 undef, label %bb81, label %bb48 bb48: ; preds = %entry - %0 = call arm_aapcs_vfpcc %0 @bbb(%pln* undef, %vec* %vstart, %vec* undef) nounwind ; <%0> [#uses=0] + %0 = call arm_aapcs_vfpcc %0 @bbb(ptr undef, ptr %vstart, ptr undef) nounwind ; <%0> [#uses=0] ret float 0.000000e+00 bb81: ; preds = %entry ret float 0.000000e+00 } -declare arm_aapcs_vfpcc %0 @bbb(%pln* nocapture, %vec* nocapture, %vec* nocapture) nounwind +declare arm_aapcs_vfpcc %0 @bbb(ptr nocapture, ptr nocapture, ptr nocapture) nounwind diff --git a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll index 07e910b3e07b6b..92efbbd7d469cf 100644 --- a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll @@ -1,23 +1,23 @@ ; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s ; PR5411 -%bar = type { %quad, float, float, [3 x %quux*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 } -%baz = type { %bar*, i32 } +%bar = type { %quad, float, float, [3 x ptr], [3 x ptr], [2 x ptr], [3 x i8], i8 } +%baz = type { ptr, i32 } %foo = type { i8, %quuz, %quad, float, [64 x %quux], [128 x %bar], i32, %baz, %baz } %quad = type { [4 x float] } %quux = type { %quad, %quad } -%quuz = type { [4 x %quux*], [4 x float], i32 } +%quuz = type { [4 x ptr], [4 x float], i32 } -define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quux* %a, %quux* %b, %quux* %c, i8 zeroext %forced) { +define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) { entry: br i1 undef, label %bb85, label %bb bb: ; preds = %entry - %0 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 2 ; [#uses=2] - %1 = load float, float* undef, align 4 ; [#uses=1] + %0 = getelementptr inbounds %bar, ptr null, i32 0, i32 0, i32 0, i32 2 ; [#uses=2] + %1 = load float, ptr undef, align 4 ; [#uses=1] %2 = fsub float 0.000000e+00, undef ; [#uses=2] %3 = fmul float 0.000000e+00, undef ; [#uses=1] - %4 = load float, float* %0, align 4 ; [#uses=3] + %4 = load float, ptr %0, align 4 ; [#uses=3] %5 = fmul float %4, %2 ; [#uses=1] %6 = fsub float %3, %5 ; [#uses=1] %7 = fmul float %4, undef ; [#uses=1] @@ -32,11 +32,11 @@ bb: ; preds = %entry %16 = fadd float %14, %15 ; [#uses=1] %17 = select i1 undef, float undef, float %16 ; [#uses=1] %18 = fdiv float %17, 0.000000e+00 ; [#uses=1] - store float %18, float* undef, align 4 + store float %18, ptr undef, align 4 %19 = fmul float %4, undef ; [#uses=1] - store float %19, float* %0, align 4 - ret %bar* null + store float %19, ptr %0, align 4 + ret ptr null bb85: ; preds = %entry - ret %bar* null + ret ptr null } diff --git a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll index 9eddcf71cb3b45..f5f065b43a8e96 100644 --- a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll +++ b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll @@ -1,14 +1,14 @@ ; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s ; PR5412 -%bar = type { %quad, float, float, [3 x %quuz*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 } -%baz = type { %bar*, i32 } +%bar = type { %quad, float, float, [3 x ptr], [3 x ptr], [2 x ptr], [3 x i8], i8 } +%baz = type { ptr, i32 } %foo = type { i8, %quux, %quad, float, [64 x %quuz], [128 x %bar], i32, %baz, %baz } %quad = type { [4 x float] } -%quux = type { [4 x %quuz*], [4 x float], i32 } +%quux = type { [4 x ptr], [4 x float], i32 } %quuz = type { %quad, %quad } -define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quuz* %a, %quuz* %b, %quuz* %c, i8 zeroext %forced) { +define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) { entry: br i1 undef, label %bb85, label %bb @@ -19,22 +19,22 @@ bb2.i: ; preds = %bb br label %bb3.i bb3.i: ; preds = %bb2.i, %bb - %0 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; [#uses=0] + %0 = getelementptr inbounds %quuz, ptr %a, i32 0, i32 1, i32 0, i32 0 ; [#uses=0] %1 = fsub float 0.000000e+00, undef ; [#uses=1] - %2 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; [#uses=2] - %3 = load float, float* %2, align 4 ; [#uses=1] - %4 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 1 ; [#uses=1] + %2 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 1 ; [#uses=2] + %3 = load float, ptr %2, align 4 ; [#uses=1] + %4 = getelementptr inbounds %quuz, ptr %a, i32 0, i32 1, i32 0, i32 1 ; [#uses=1] %5 = fsub float %3, undef ; [#uses=2] - %6 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; [#uses=2] - %7 = load float, float* %6, align 4 ; [#uses=1] + %6 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 2 ; [#uses=2] + %7 = load float, ptr %6, align 4 ; [#uses=1] %8 = fsub float %7, undef ; [#uses=1] - %9 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; [#uses=2] - %10 = load float, float* %9, align 4 ; [#uses=1] + %9 = getelementptr inbounds %quuz, ptr %c, i32 0, i32 1, i32 0, i32 0 ; [#uses=2] + %10 = load float, ptr %9, align 4 ; [#uses=1] %11 = fsub float %10, undef ; [#uses=2] - %12 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; [#uses=2] - %13 = load float, float* %12, align 4 ; [#uses=1] + %12 = getelementptr inbounds %quuz, ptr %c, i32 0, i32 1, i32 0, i32 1 ; [#uses=2] + %13 = load float, ptr %12, align 4 ; [#uses=1] %14 = fsub float %13, undef ; [#uses=1] - %15 = load float, float* undef, align 4 ; [#uses=1] + %15 = load float, ptr undef, align 4 ; [#uses=1] %16 = fsub float %15, undef ; [#uses=1] %17 = fmul float %5, %16 ; [#uses=1] %18 = fsub float %17, 0.000000e+00 ; [#uses=5] @@ -43,20 +43,20 @@ bb3.i: ; preds = %bb2.i, %bb %21 = fmul float %1, %14 ; [#uses=1] %22 = fmul float %5, %11 ; [#uses=1] %23 = fsub float %21, %22 ; [#uses=2] - store float %18, float* undef - %24 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 1 ; [#uses=2] - store float %20, float* %24 - store float %23, float* undef - %25 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 3 ; [#uses=0] + store float %18, ptr undef + %24 = getelementptr inbounds %bar, ptr null, i32 0, i32 0, i32 0, i32 1 ; [#uses=2] + store float %20, ptr %24 + store float %23, ptr undef + %25 = getelementptr inbounds %bar, ptr null, i32 0, i32 0, i32 0, i32 3 ; [#uses=0] %26 = fmul float %18, %18 ; [#uses=1] %27 = fadd float %26, undef ; [#uses=1] %28 = fadd float %27, undef ; [#uses=1] %29 = call arm_aapcs_vfpcc float @sqrtf(float %28) readnone ; [#uses=1] - %30 = load float, float* null, align 4 ; [#uses=2] - %31 = load float, float* %4, align 4 ; [#uses=2] - %32 = load float, float* %2, align 4 ; [#uses=2] - %33 = load float, float* null, align 4 ; [#uses=3] - %34 = load float, float* %6, align 4 ; [#uses=2] + %30 = load float, ptr null, align 4 ; [#uses=2] + %31 = load float, ptr %4, align 4 ; [#uses=2] + %32 = load float, ptr %2, align 4 ; [#uses=2] + %33 = load float, ptr null, align 4 ; [#uses=3] + %34 = load float, ptr %6, align 4 ; [#uses=2] %35 = fsub float %33, %34 ; [#uses=2] %36 = fmul float %20, %35 ; [#uses=1] %37 = fsub float %36, undef ; [#uses=1] @@ -71,12 +71,12 @@ bb3.i: ; preds = %bb2.i, %bb %46 = fadd float %44, %45 ; [#uses=1] %47 = fmul float %33, %43 ; [#uses=1] %48 = fadd float %46, %47 ; [#uses=2] - %49 = load float, float* %9, align 4 ; [#uses=2] + %49 = load float, ptr %9, align 4 ; [#uses=2] %50 = fsub float %30, %49 ; [#uses=1] - %51 = load float, float* %12, align 4 ; [#uses=3] + %51 = load float, ptr %12, align 4 ; [#uses=3] %52 = fsub float %32, %51 ; [#uses=2] - %53 = load float, float* undef, align 4 ; [#uses=2] - %54 = load float, float* %24, align 4 ; [#uses=2] + %53 = load float, ptr undef, align 4 ; [#uses=2] + %54 = load float, ptr %24, align 4 ; [#uses=2] %55 = fmul float %54, undef ; [#uses=1] %56 = fmul float undef, %52 ; [#uses=1] %57 = fsub float %55, %56 ; [#uses=1] @@ -93,7 +93,7 @@ bb3.i: ; preds = %bb2.i, %bb %68 = fsub float %51, %31 ; [#uses=1] %69 = fsub float %53, %33 ; [#uses=1] %70 = fmul float undef, %67 ; [#uses=1] - %71 = load float, float* undef, align 4 ; [#uses=2] + %71 = load float, ptr undef, align 4 ; [#uses=2] %72 = fmul float %71, %69 ; [#uses=1] %73 = fsub float %70, %72 ; [#uses=1] %74 = fmul float %71, %68 ; [#uses=1] @@ -107,17 +107,17 @@ bb3.i: ; preds = %bb2.i, %bb %iftmp.164.0 = select i1 undef, float %29, float 1.000000e+00 ; [#uses=1] %82 = fdiv float %81, %iftmp.164.0 ; [#uses=1] %iftmp.165.0 = select i1 undef, float %82, float 0.000000e+00 ; [#uses=1] - store float %iftmp.165.0, float* undef, align 4 + store float %iftmp.165.0, ptr undef, align 4 br i1 false, label %bb4.i97, label %ccc.exit98 bb4.i97: ; preds = %bb3.i br label %ccc.exit98 ccc.exit98: ; preds = %bb4.i97, %bb3.i - ret %bar* null + ret ptr null bb85: ; preds = %entry - ret %bar* null + ret ptr null } declare arm_aapcs_vfpcc float @sqrtf(float) readnone diff --git a/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll b/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll index 8a14804dcf85cc..9c773ca8d613cf 100644 --- a/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll +++ b/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll @@ -2,16 +2,16 @@ ; PR5412 ; rdar://7384107 -%bar = type { %quad, float, float, [3 x %quuz*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 } -%baz = type { %bar*, i32 } +%bar = type { %quad, float, float, [3 x ptr], [3 x ptr], [2 x ptr], [3 x i8], i8 } +%baz = type { ptr, i32 } %foo = type { i8, %quux, %quad, float, [64 x %quuz], [128 x %bar], i32, %baz, %baz } %quad = type { [4 x float] } -%quux = type { [4 x %quuz*], [4 x float], i32 } +%quux = type { [4 x ptr], [4 x float], i32 } %quuz = type { %quad, %quad } -define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quuz* %a, %quuz* %b, %quuz* %c, i8 zeroext %forced) { +define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) { entry: - %0 = load %bar*, %bar** undef, align 4 ; <%bar*> [#uses=2] + %0 = load ptr, ptr undef, align 4 ; [#uses=2] br i1 false, label %bb85, label %bb bb: ; preds = %entry @@ -21,13 +21,13 @@ bb2.i: ; preds = %bb br label %bb3.i bb3.i: ; preds = %bb2.i, %bb - %1 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; [#uses=1] + %1 = getelementptr inbounds %quuz, ptr %a, i32 0, i32 1, i32 0, i32 0 ; [#uses=1] %2 = fsub float 0.000000e+00, undef ; [#uses=1] - %3 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; [#uses=1] - %4 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; [#uses=1] + %3 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 1 ; [#uses=1] + %4 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 2 ; [#uses=1] %5 = fsub float 0.000000e+00, undef ; [#uses=1] - %6 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; [#uses=1] - %7 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; [#uses=1] + %6 = getelementptr inbounds %quuz, ptr %c, i32 0, i32 1, i32 0, i32 0 ; [#uses=1] + %7 = getelementptr inbounds %quuz, ptr %c, i32 0, i32 1, i32 0, i32 1 ; [#uses=1] %8 = fsub float undef, undef ; [#uses=1] %9 = fmul float 0.000000e+00, %8 ; [#uses=1] %10 = fmul float %5, 0.000000e+00 ; [#uses=1] @@ -35,18 +35,18 @@ bb3.i: ; preds = %bb2.i, %bb %12 = fmul float %2, 0.000000e+00 ; [#uses=1] %13 = fmul float 0.000000e+00, undef ; [#uses=1] %14 = fsub float %12, %13 ; [#uses=2] - store float %14, float* undef - %15 = getelementptr inbounds %bar, %bar* %0, i32 0, i32 0, i32 0, i32 3 ; [#uses=1] - store float 0.000000e+00, float* %15 + store float %14, ptr undef + %15 = getelementptr inbounds %bar, ptr %0, i32 0, i32 0, i32 0, i32 3 ; [#uses=1] + store float 0.000000e+00, ptr %15 %16 = fmul float %11, %11 ; [#uses=1] %17 = fadd float %16, 0.000000e+00 ; [#uses=1] %18 = fadd float %17, undef ; [#uses=1] %19 = call arm_aapcs_vfpcc float @sqrtf(float %18) readnone ; [#uses=2] %20 = fcmp ogt float %19, 0x3F1A36E2E0000000 ; [#uses=1] - %21 = load float, float* %1, align 4 ; [#uses=2] - %22 = load float, float* %3, align 4 ; [#uses=2] - %23 = load float, float* undef, align 4 ; [#uses=2] - %24 = load float, float* %4, align 4 ; [#uses=2] + %21 = load float, ptr %1, align 4 ; [#uses=2] + %22 = load float, ptr %3, align 4 ; [#uses=2] + %23 = load float, ptr undef, align 4 ; [#uses=2] + %24 = load float, ptr %4, align 4 ; [#uses=2] %25 = fsub float %23, %24 ; [#uses=2] %26 = fmul float 0.000000e+00, %25 ; [#uses=1] %27 = fsub float %26, undef ; [#uses=1] @@ -59,11 +59,11 @@ bb3.i: ; preds = %bb2.i, %bb %34 = fadd float %32, %33 ; [#uses=1] %35 = fmul float %23, %31 ; [#uses=1] %36 = fadd float %34, %35 ; [#uses=1] - %37 = load float, float* %6, align 4 ; [#uses=2] - %38 = load float, float* %7, align 4 ; [#uses=2] + %37 = load float, ptr %6, align 4 ; [#uses=2] + %38 = load float, ptr %7, align 4 ; [#uses=2] %39 = fsub float %22, %38 ; [#uses=2] - %40 = load float, float* undef, align 4 ; [#uses=1] - %41 = load float, float* null, align 4 ; [#uses=2] + %40 = load float, ptr undef, align 4 ; [#uses=1] + %41 = load float, ptr null, align 4 ; [#uses=2] %42 = fmul float %41, undef ; [#uses=1] %43 = fmul float undef, %39 ; [#uses=1] %44 = fsub float %42, %43 ; [#uses=1] @@ -80,7 +80,7 @@ bb3.i: ; preds = %bb2.i, %bb %55 = fmul float undef, undef ; [#uses=1] %56 = fsub float %54, %55 ; [#uses=1] %57 = fmul float undef, %53 ; [#uses=1] - %58 = load float, float* undef, align 4 ; [#uses=2] + %58 = load float, ptr undef, align 4 ; [#uses=2] %59 = fmul float %58, undef ; [#uses=1] %60 = fsub float %57, %59 ; [#uses=1] %61 = fmul float %58, undef ; [#uses=1] @@ -95,19 +95,19 @@ bb3.i: ; preds = %bb2.i, %bb %70 = select i1 undef, float %69, float %68 ; [#uses=1] %iftmp.164.0 = select i1 %20, float %19, float 1.000000e+00 ; [#uses=1] %71 = fdiv float %70, %iftmp.164.0 ; [#uses=1] - store float %71, float* null, align 4 - %72 = icmp eq %bar* null, %0 ; [#uses=1] + store float %71, ptr null, align 4 + %72 = icmp eq ptr null, %0 ; [#uses=1] br i1 %72, label %bb4.i97, label %ccc.exit98 bb4.i97: ; preds = %bb3.i - %73 = load %bar*, %bar** undef, align 4 ; <%bar*> [#uses=0] + %73 = load ptr, ptr undef, align 4 ; [#uses=0] br label %ccc.exit98 ccc.exit98: ; preds = %bb4.i97, %bb3.i - ret %bar* null + ret ptr null bb85: ; preds = %entry - ret %bar* null + ret ptr null } declare arm_aapcs_vfpcc float @sqrtf(float) readnone diff --git a/llvm/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll b/llvm/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll index efe74cfd13875b..a25114b71a96d2 100644 --- a/llvm/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll +++ b/llvm/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll @@ -1,13 +1,13 @@ ; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s ; PR5614 -%"als" = type { i32 (...)** } +%"als" = type { ptr } %"av" = type { %"als" } -%"c" = type { %"lsm", %"Vec3", %"av"*, float, i8, float, %"lsm", i8, %"Vec3", %"Vec3", %"Vec3", float, float, float, %"Vec3", %"Vec3" } +%"c" = type { %"lsm", %"Vec3", ptr, float, i8, float, %"lsm", i8, %"Vec3", %"Vec3", %"Vec3", float, float, float, %"Vec3", %"Vec3" } %"lsm" = type { %"als", %"Vec3", %"Vec3", %"Vec3", %"Vec3" } %"Vec3" = type { float, float, float } -define arm_aapcs_vfpcc void @foo(%"c"* %this, %"Vec3"* nocapture %adjustment) { +define arm_aapcs_vfpcc void @foo(ptr %this, ptr nocapture %adjustment) { entry: switch i32 undef, label %return [ i32 1, label %bb @@ -21,10 +21,10 @@ bb: ; preds = %entry ret void bb31: ; preds = %entry - %0 = call arm_aapcs_vfpcc %"Vec3" undef(%"lsm"* undef) ; <%"Vec3"> [#uses=1] + %0 = call arm_aapcs_vfpcc %"Vec3" undef(ptr undef) ; <%"Vec3"> [#uses=1] %mrv_gr69 = extractvalue %"Vec3" %0, 1 ; [#uses=1] %1 = fsub float %mrv_gr69, undef ; [#uses=1] - store float %1, float* undef, align 4 + store float %1, ptr undef, align 4 ret void bb72: ; preds = %entry diff --git a/llvm/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll b/llvm/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll index be9dcffedcd443..c7418af52fd7e6 100644 --- a/llvm/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll +++ b/llvm/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll @@ -6,28 +6,27 @@ target triple = "armv7-apple-darwin10" %struct.int16x8_t = type { <8 x i16> } %struct.int16x8x2_t = type { [2 x %struct.int16x8_t] } -define void @t(%struct.int16x8x2_t* noalias nocapture sret(%struct.int16x8x2_t) %agg.result, <8 x i16> %tmp.0, %struct.int16x8x2_t* nocapture %dst) nounwind { +define void @t(ptr noalias nocapture sret(%struct.int16x8x2_t) %agg.result, <8 x i16> %tmp.0, ptr nocapture %dst) nounwind { entry: ;CHECK: vtrn.16 %0 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> %1 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> - %agg.result1218.0 = getelementptr %struct.int16x8x2_t, %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 0, i32 0 ; <<8 x i16>*> - store <8 x i16> %0, <8 x i16>* %agg.result1218.0, align 16 - %agg.result12.1.0 = getelementptr %struct.int16x8x2_t, %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 1, i32 0 ; <<8 x i16>*> - store <8 x i16> %1, <8 x i16>* %agg.result12.1.0, align 16 + %agg.result1218.0 = getelementptr %struct.int16x8x2_t, ptr %agg.result, i32 0, i32 0, i32 0, i32 0 ; + store <8 x i16> %0, ptr %agg.result1218.0, align 16 + %agg.result12.1.0 = getelementptr %struct.int16x8x2_t, ptr %agg.result, i32 0, i32 0, i32 1, i32 0 ; + store <8 x i16> %1, ptr %agg.result12.1.0, align 16 ret void } ; Radar 8290937: Ignore undef shuffle indices. ; CHECK: t2 ; CHECK: vtrn.16 -define void @t2(%struct.int16x8x2_t* nocapture %ptr, <4 x i16> %a.0, <4 x i16> %b.0) nounwind { +define void @t2(ptr nocapture %ptr, <4 x i16> %a.0, <4 x i16> %b.0) nounwind { entry: %0 = shufflevector <4 x i16> %a.0, <4 x i16> undef, <8 x i32> %1 = shufflevector <4 x i16> %a.0, <4 x i16> undef, <8 x i32> - %ptr26.0 = getelementptr inbounds %struct.int16x8x2_t, %struct.int16x8x2_t* %ptr, i32 0, i32 0, i32 0, i32 0 - store <8 x i16> %0, <8 x i16>* %ptr26.0, align 16 - %ptr20.1.0 = getelementptr inbounds %struct.int16x8x2_t, %struct.int16x8x2_t* %ptr, i32 0, i32 0, i32 1, i32 0 - store <8 x i16> %1, <8 x i16>* %ptr20.1.0, align 16 + store <8 x i16> %0, ptr %ptr, align 16 + %ptr20.1.0 = getelementptr inbounds %struct.int16x8x2_t, ptr %ptr, i32 0, i32 0, i32 1, i32 0 + store <8 x i16> %1, ptr %ptr20.1.0, align 16 ret void } diff --git a/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll b/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll index d21b488bb3a0e1..c44850bbd554ea 100644 --- a/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll +++ b/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi -define void @"java.lang.String::getChars"([84 x i8]* %method, i32 %base_pc, [788 x i8]* %thread) { - %1 = load i32, i32* undef ; [#uses=1] +define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread) { + %1 = load i32, ptr undef ; [#uses=1] %2 = sub i32 %1, 48 ; [#uses=1] br i1 undef, label %stack_overflow, label %no_overflow @@ -9,14 +9,13 @@ stack_overflow: ; preds = %0 unreachable no_overflow: ; preds = %0 - %frame = inttoptr i32 %2 to [17 x i32]* ; <[17 x i32]*> [#uses=4] - %3 = load i32, i32* undef ; [#uses=1] - %4 = load i32, i32* null ; [#uses=1] - %5 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 13 ; [#uses=1] - %6 = bitcast i32* %5 to [8 x i8]** ; <[8 x i8]**> [#uses=1] - %7 = load [8 x i8]*, [8 x i8]** %6 ; <[8 x i8]*> [#uses=1] - %8 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 12 ; [#uses=1] - %9 = load i32, i32* %8 ; [#uses=1] + %frame = inttoptr i32 %2 to ptr ; [#uses=4] + %3 = load i32, ptr undef ; [#uses=1] + %4 = load i32, ptr null ; [#uses=1] + %5 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 13 ; [#uses=1] + %6 = load ptr, ptr %5 ; [#uses=1] + %7 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 12 ; [#uses=1] + %8 = load i32, ptr %7 ; [#uses=1] br i1 undef, label %bci_13, label %bci_4 bci_13: ; preds = %no_overflow @@ -26,26 +25,23 @@ bci_30: ; preds = %bci_13 br i1 undef, label %bci_46, label %bci_35 bci_46: ; preds = %bci_30 - %10 = sub i32 %4, %3 ; [#uses=1] - %11 = load [8 x i8]*, [8 x i8]** null ; <[8 x i8]*> [#uses=1] - %callee = bitcast [8 x i8]* %11 to [84 x i8]* ; <[84 x i8]*> [#uses=1] - %12 = bitcast i8* undef to i32* ; [#uses=1] - %base_pc7 = load i32, i32* %12 ; [#uses=2] - %13 = add i32 %base_pc7, 0 ; [#uses=1] - %14 = inttoptr i32 %13 to void ([84 x i8]*, i32, [788 x i8]*)** ; [#uses=1] - %entry_point = load void ([84 x i8]*, i32, [788 x i8]*)*, void ([84 x i8]*, i32, [788 x i8]*)** %14 ; [#uses=1] - %15 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 1 ; [#uses=1] - %16 = ptrtoint i32* %15 to i32 ; [#uses=1] - %stack_pointer_addr9 = bitcast i8* undef to i32* ; [#uses=1] - store i32 %16, i32* %stack_pointer_addr9 - %17 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 2 ; [#uses=1] - store i32 %9, i32* %17 - store i32 %10, i32* undef - store [84 x i8]* %method, [84 x i8]** undef - %18 = add i32 %base_pc, 20 ; [#uses=1] - store i32 %18, i32* undef - store [8 x i8]* %7, [8 x i8]** undef - call void %entry_point([84 x i8]* %callee, i32 %base_pc7, [788 x i8]* %thread) + %9 = sub i32 %4, %3 ; [#uses=1] + %10 = load ptr, ptr null ; [#uses=1] + %base_pc7 = load i32, ptr undef ; [#uses=2] + %11 = add i32 %base_pc7, 0 ; [#uses=1] + %12 = inttoptr i32 %11 to ptr ; [#uses=1] + %entry_point = load ptr, ptr %12 ; [#uses=1] + %13 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 1 ; [#uses=1] + %14 = ptrtoint ptr %13 to i32 ; [#uses=1] + store i32 %14, ptr undef + %15 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 2 ; [#uses=1] + store i32 %8, ptr %15 + store i32 %9, ptr undef + store ptr %method, ptr undef + %16 = add i32 %base_pc, 20 ; [#uses=1] + store i32 %16, ptr undef + store ptr %6, ptr undef + call void %entry_point(ptr %10, i32 %base_pc7, ptr %thread) br i1 undef, label %no_exception, label %exception exception: ; preds = %bci_46 diff --git a/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll b/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll index a1923ec2c3e08d..fe4e3478ffd3aa 100644 --- a/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll +++ b/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=arm-eabi %s -o /dev/null -define void @"java.lang.String::getChars"([84 x i8]* %method, i32 %base_pc, [788 x i8]* %thread) { +define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread) { %1 = sub i32 undef, 48 ; [#uses=1] br i1 undef, label %stack_overflow, label %no_overflow @@ -8,11 +8,11 @@ stack_overflow: ; preds = %0 unreachable no_overflow: ; preds = %0 - %frame = inttoptr i32 %1 to [17 x i32]* ; <[17 x i32]*> [#uses=4] - %2 = load i32, i32* null ; [#uses=2] - %3 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 14 ; [#uses=1] - %4 = load i32, i32* %3 ; [#uses=2] - %5 = load [8 x i8]*, [8 x i8]** undef ; <[8 x i8]*> [#uses=2] + %frame = inttoptr i32 %1 to ptr ; [#uses=4] + %2 = load i32, ptr null ; [#uses=2] + %3 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 14 ; [#uses=1] + %4 = load i32, ptr %3 ; [#uses=2] + %5 = load ptr, ptr undef ; [#uses=2] br i1 undef, label %bci_13, label %bci_4 bci_13: ; preds = %no_overflow @@ -23,7 +23,7 @@ bci_30: ; preds = %bci_13 br i1 %6, label %bci_46, label %bci_35 bci_46: ; preds = %bci_30 - store [84 x i8]* %method, [84 x i8]** undef + store ptr %method, ptr undef br i1 false, label %no_exception, label %exception exception: ; preds = %bci_46 @@ -33,22 +33,21 @@ no_exception: ; preds = %bci_46 ret void bci_35: ; preds = %bci_30 - %7 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 15 ; [#uses=1] - store i32 %2, i32* %7 - %8 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 14 ; [#uses=1] - store i32 %4, i32* %8 - %9 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 13 ; [#uses=1] - %10 = bitcast i32* %9 to [8 x i8]** ; <[8 x i8]**> [#uses=1] - store [8 x i8]* %5, [8 x i8]** %10 - call void inttoptr (i32 13839116 to void ([788 x i8]*, i32)*)([788 x i8]* %thread, i32 7) + %7 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 15 ; [#uses=1] + store i32 %2, ptr %7 + %8 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 14 ; [#uses=1] + store i32 %4, ptr %8 + %9 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 13 ; [#uses=1] + store ptr %5, ptr %9 + call void inttoptr (i32 13839116 to ptr)(ptr %thread, i32 7) ret void bci_21: ; preds = %bci_13 ret void bci_4: ; preds = %no_overflow - store [8 x i8]* %5, [8 x i8]** undef - store i32 undef, i32* undef - call void inttoptr (i32 13839116 to void ([788 x i8]*, i32)*)([788 x i8]* %thread, i32 7) + store ptr %5, ptr undef + store i32 undef, ptr undef + call void inttoptr (i32 13839116 to ptr)(ptr %thread, i32 7) ret void } diff --git a/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll b/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll index ceef0830fd2e91..1426d91b4b030d 100644 --- a/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll +++ b/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o /dev/null ; rdar://7770501 : Don't crash on SELECT and SELECT_CC with NEON vector values. -define void @vDSP_FFT16_copv(float* nocapture %O, float* nocapture %I, i32 %Direction) nounwind { +define void @vDSP_FFT16_copv(ptr nocapture %O, ptr nocapture %I, i32 %Direction) nounwind { entry: %.22 = select i1 undef, <4 x float> undef, <4 x float> zeroinitializer ; <<4 x float>> [#uses=1] %0 = fadd <4 x float> undef, %.22 ; <<4 x float>> [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll b/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll index 5f5489a1ca74f9..7ad9cb18e5de18 100644 --- a/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll +++ b/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll @@ -9,8 +9,8 @@ target triple = "arm-pc-linux-gnu" %struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 } -@search = external global %struct.CHESS_POSITION ; <%struct.CHESS_POSITION*> [#uses=1] -@bishop_mobility_rr45 = external global [64 x [256 x i32]] ; <[64 x [256 x i32]]*> [#uses=1] +@search = external global %struct.CHESS_POSITION ; [#uses=1] +@bishop_mobility_rr45 = external global [64 x [256 x i32]] ; [#uses=1] declare fastcc i32 @FirstOne() @@ -82,17 +82,17 @@ cond_true1369.preheader: ; preds = %cond_true1254 ret void bb1567: ; preds = %cond_true1254 - %tmp1591 = load i64, i64* getelementptr inbounds (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 4) ; [#uses=1] + %tmp1591 = load i64, ptr getelementptr inbounds (%struct.CHESS_POSITION, ptr @search, i32 0, i32 4) ; [#uses=1] %tmp1572 = tail call fastcc i32 @FirstOne() ; [#uses=1] - %tmp1594 = load i32, i32* undef ; [#uses=1] + %tmp1594 = load i32, ptr undef ; [#uses=1] %tmp1594.upgrd.5 = trunc i32 %tmp1594 to i8 ; [#uses=1] %shift.upgrd.6 = zext i8 %tmp1594.upgrd.5 to i64 ; [#uses=1] %tmp1595 = lshr i64 %tmp1591, %shift.upgrd.6 ; [#uses=1] %tmp1595.upgrd.7 = trunc i64 %tmp1595 to i32 ; [#uses=1] %tmp1596 = and i32 %tmp1595.upgrd.7, 255 ; [#uses=1] %gep.upgrd.8 = zext i32 %tmp1596 to i64 ; [#uses=1] - %tmp1598 = getelementptr [64 x [256 x i32]], [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; [#uses=1] - %tmp1599 = load i32, i32* %tmp1598 ; [#uses=1] + %tmp1598 = getelementptr [64 x [256 x i32]], ptr @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; [#uses=1] + %tmp1599 = load i32, ptr %tmp1598 ; [#uses=1] %tmp1602 = sub i32 0, %tmp1599 ; [#uses=1] br i1 undef, label %cond_next1637, label %cond_true1607 diff --git a/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll b/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll index deb588403265ec..ea1457374f68a0 100644 --- a/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll +++ b/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll @@ -8,23 +8,23 @@ target triple = "armv6-apple-darwin" %struct.q = type { i32, i32 } -@.str = external constant [1 x i8] ; <[1 x i8]*> [#uses=1] +@.str = external constant [1 x i8] ; [#uses=1] -define void @yy(%struct.q* %qq) nounwind { +define void @yy(ptr %qq) nounwind { entry: - %vla6 = alloca i8, i32 undef, align 1 ; [#uses=1] - %vla10 = alloca i8, i32 undef, align 1 ; [#uses=1] - %vla14 = alloca i8, i32 undef, align 1 ; [#uses=1] - %vla18 = alloca i8, i32 undef, align 1 ; [#uses=1] - %tmp21 = load i32, i32* undef ; [#uses=1] + %vla6 = alloca i8, i32 undef, align 1 ; [#uses=1] + %vla10 = alloca i8, i32 undef, align 1 ; [#uses=1] + %vla14 = alloca i8, i32 undef, align 1 ; [#uses=1] + %vla18 = alloca i8, i32 undef, align 1 ; [#uses=1] + %tmp21 = load i32, ptr undef ; [#uses=1] %0 = mul i32 1, %tmp21 ; [#uses=1] - %vla22 = alloca i8, i32 %0, align 1 ; [#uses=1] - call void (...) @zz(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1) + %vla22 = alloca i8, i32 %0, align 1 ; [#uses=1] + call void (...) @zz(ptr @.str, i32 2, i32 1) br i1 undef, label %if.then, label %if.end36 if.then: ; preds = %entry - %call = call i32 (...) @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; [#uses=0] - %call35 = call i32 (...) @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; [#uses=0] + %call = call i32 (...) @x(ptr undef, ptr undef, ptr %vla6, ptr %vla10, i32 undef) ; [#uses=0] + %call35 = call i32 (...) @x(ptr undef, ptr %vla14, ptr %vla18, ptr %vla22, i32 undef) ; [#uses=0] unreachable if.end36: ; preds = %entry diff --git a/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll index f0b7141b5c7a2b..87ed82e83ecf8a 100644 --- a/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll +++ b/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll @@ -4,7 +4,7 @@ %struct.foo = type { i64, i64 } -define zeroext i8 @t(%struct.foo* %this, i1 %tst) noreturn optsize { +define zeroext i8 @t(ptr %this, i1 %tst) noreturn optsize { entry: ; ARM-LABEL: t: ; ARM-DAG: mov r[[ADDR:[0-9]+]], #8 @@ -16,12 +16,12 @@ entry: ; THUMB-DAG: movs [[VAL:r[0-9]+]], #0 ; THUMB-NOT: str {{[a-z0-9]+}}, [{{[a-z0-9]+}}], {{[a-z0-9]+}} ; THUMB: str [[VAL]], [r[[ADDR]]] - %0 = getelementptr inbounds %struct.foo, %struct.foo* %this, i32 0, i32 1 ; [#uses=1] - store i32 0, i32* inttoptr (i32 8 to i32*), align 8 + %0 = getelementptr inbounds %struct.foo, ptr %this, i32 0, i32 1 ; [#uses=1] + store i32 0, ptr inttoptr (i32 8 to ptr), align 8 br i1 %tst, label %bb.nph96, label %bb3 bb3: ; preds = %entry - %1 = load i64, i64* %0, align 4 ; [#uses=0] + %1 = load i64, ptr %0, align 4 ; [#uses=0] ret i8 42 bb.nph96: ; preds = %entry diff --git a/llvm/test/CodeGen/ARM/2010-05-19-Shuffles.ll b/llvm/test/CodeGen/ARM/2010-05-19-Shuffles.ll index 94d0f4abfb7e6d..77d576322151e2 100644 --- a/llvm/test/CodeGen/ARM/2010-05-19-Shuffles.ll +++ b/llvm/test/CodeGen/ARM/2010-05-19-Shuffles.ll @@ -13,9 +13,9 @@ define <8 x i8> @f2(<8 x i8> %x) nounwind { ret <8 x i8> %y } -define void @f3(<4 x i64>* %xp) nounwind { - %x = load <4 x i64>, <4 x i64>* %xp +define void @f3(ptr %xp) nounwind { + %x = load <4 x i64>, ptr %xp %y = shufflevector <4 x i64> %x, <4 x i64> undef, <4 x i32> - store <4 x i64> %y, <4 x i64>* %xp + store <4 x i64> %y, ptr %xp ret void } diff --git a/llvm/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll b/llvm/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll index 171b6d2bcc5c9b..0746ff22085cba 100644 --- a/llvm/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll +++ b/llvm/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll @@ -1,36 +1,36 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+neon -O0 -optimize-regalloc -regalloc=basic %s -o /dev/null ; This test would crash the rewriter when trying to handle a spill after one of -; the @llvm.arm.neon.vld3.v8i8.p0i8 defined three parts of a register. +; the @llvm.arm.neon.vld3.v8i8.p0 defined three parts of a register. %struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } -declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr, i32) nounwind readonly -declare void @llvm.arm.neon.vst3.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind +declare void @llvm.arm.neon.vst3.p0.v8i8(ptr, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind -define <8 x i8> @t3(i8* %A1, i8* %A2, i8* %A3, i8* %A4, i8* %A5, i8* %A6, i8* %A7, i8* %A8, i8* %B) nounwind { - %tmp1b = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A2, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] +define <8 x i8> @t3(ptr %A1, ptr %A2, ptr %A3, ptr %A4, ptr %A5, ptr %A6, ptr %A7, ptr %A8, ptr %B) nounwind { + %tmp1b = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A2, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] %tmp2b = extractvalue %struct.__neon_int8x8x3_t %tmp1b, 0 ; <<8 x i8>> [#uses=1] %tmp4b = extractvalue %struct.__neon_int8x8x3_t %tmp1b, 1 ; <<8 x i8>> [#uses=1] - %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] + %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] %tmp2d = extractvalue %struct.__neon_int8x8x3_t %tmp1d, 0 ; <<8 x i8>> [#uses=1] %tmp4d = extractvalue %struct.__neon_int8x8x3_t %tmp1d, 1 ; <<8 x i8>> [#uses=1] - %tmp1e = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A5, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1] + %tmp1e = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A5, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1] %tmp2e = extractvalue %struct.__neon_int8x8x3_t %tmp1e, 0 ; <<8 x i8>> [#uses=1] - %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1] + %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1] %tmp2f = extractvalue %struct.__neon_int8x8x3_t %tmp1f, 0 ; <<8 x i8>> [#uses=1] - %tmp1g = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A7, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] + %tmp1g = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A7, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] %tmp2g = extractvalue %struct.__neon_int8x8x3_t %tmp1g, 0 ; <<8 x i8>> [#uses=1] %tmp4g = extractvalue %struct.__neon_int8x8x3_t %tmp1g, 1 ; <<8 x i8>> [#uses=1] - %tmp1h = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A8, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] + %tmp1h = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A8, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] %tmp2h = extractvalue %struct.__neon_int8x8x3_t %tmp1h, 0 ; <<8 x i8>> [#uses=1] %tmp3h = extractvalue %struct.__neon_int8x8x3_t %tmp1h, 2 ; <<8 x i8>> [#uses=1] %tmp2bd = add <8 x i8> %tmp2b, %tmp2d ; <<8 x i8>> [#uses=1] %tmp4bd = add <8 x i8> %tmp4b, %tmp4d ; <<8 x i8>> [#uses=1] %tmp2abcd = mul <8 x i8> undef, %tmp2bd ; <<8 x i8>> [#uses=1] %tmp4abcd = mul <8 x i8> undef, %tmp4bd ; <<8 x i8>> [#uses=2] - call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %A1, <8 x i8> %tmp4abcd, <8 x i8> zeroinitializer, <8 x i8> %tmp2abcd, i32 1) + call void @llvm.arm.neon.vst3.p0.v8i8(ptr %A1, <8 x i8> %tmp4abcd, <8 x i8> zeroinitializer, <8 x i8> %tmp2abcd, i32 1) %tmp2ef = sub <8 x i8> %tmp2e, %tmp2f ; <<8 x i8>> [#uses=1] %tmp2gh = sub <8 x i8> %tmp2g, %tmp2h ; <<8 x i8>> [#uses=1] %tmp3gh = sub <8 x i8> zeroinitializer, %tmp3h ; <<8 x i8>> [#uses=1] @@ -38,8 +38,8 @@ define <8 x i8> @t3(i8* %A1, i8* %A2, i8* %A3, i8* %A4, i8* %A5, i8* %A6, i8* %A %tmp2efgh = mul <8 x i8> %tmp2ef, %tmp2gh ; <<8 x i8>> [#uses=1] %tmp3efgh = mul <8 x i8> undef, %tmp3gh ; <<8 x i8>> [#uses=1] %tmp4efgh = mul <8 x i8> %tmp4ef, undef ; <<8 x i8>> [#uses=2] - call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %A2, <8 x i8> %tmp4efgh, <8 x i8> %tmp3efgh, <8 x i8> %tmp2efgh, i32 1) + call void @llvm.arm.neon.vst3.p0.v8i8(ptr %A2, <8 x i8> %tmp4efgh, <8 x i8> %tmp3efgh, <8 x i8> %tmp2efgh, i32 1) %tmp4 = sub <8 x i8> %tmp4efgh, %tmp4abcd ; <<8 x i8>> [#uses=1] - tail call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %B, <8 x i8> zeroinitializer, <8 x i8> undef, <8 x i8> undef, i32 1) + tail call void @llvm.arm.neon.vst3.p0.v8i8(ptr %B, <8 x i8> zeroinitializer, <8 x i8> undef, <8 x i8> undef, i32 1) ret <8 x i8> %tmp4 } diff --git a/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll b/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll index c6c0e2caee420f..e9cea62f586ba3 100644 --- a/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll +++ b/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll @@ -1,43 +1,42 @@ ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s ; Radar 7872877 -define void @test(float* %fltp, i32 %packedValue, float* %table) nounwind { +define void @test(ptr %fltp, i32 %packedValue, ptr %table) nounwind { entry: - %0 = load float, float* %fltp + %0 = load float, ptr %fltp %1 = insertelement <4 x float> undef, float %0, i32 0 %2 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> zeroinitializer %3 = shl i32 %packedValue, 16 %4 = ashr i32 %3, 30 %.sum = add i32 %4, 4 - %5 = getelementptr inbounds float, float* %table, i32 %.sum + %5 = getelementptr inbounds float, ptr %table, i32 %.sum ;CHECK: vldr s - %6 = load float, float* %5, align 4 + %6 = load float, ptr %5, align 4 %tmp11 = insertelement <4 x float> undef, float %6, i32 0 %7 = shl i32 %packedValue, 18 %8 = ashr i32 %7, 30 %.sum12 = add i32 %8, 4 - %9 = getelementptr inbounds float, float* %table, i32 %.sum12 + %9 = getelementptr inbounds float, ptr %table, i32 %.sum12 ;CHECK: vldr s - %10 = load float, float* %9, align 4 + %10 = load float, ptr %9, align 4 %tmp9 = insertelement <4 x float> %tmp11, float %10, i32 1 %11 = shl i32 %packedValue, 20 %12 = ashr i32 %11, 30 %.sum13 = add i32 %12, 4 - %13 = getelementptr inbounds float, float* %table, i32 %.sum13 + %13 = getelementptr inbounds float, ptr %table, i32 %.sum13 ;CHECK: vldr s - %14 = load float, float* %13, align 4 + %14 = load float, ptr %13, align 4 %tmp7 = insertelement <4 x float> %tmp9, float %14, i32 2 %15 = shl i32 %packedValue, 22 %16 = ashr i32 %15, 30 %.sum14 = add i32 %16, 4 - %17 = getelementptr inbounds float, float* %table, i32 %.sum14 + %17 = getelementptr inbounds float, ptr %table, i32 %.sum14 ;CHECK: vldr s - %18 = load float, float* %17, align 4 + %18 = load float, ptr %17, align 4 %tmp5 = insertelement <4 x float> %tmp7, float %18, i32 3 %19 = fmul <4 x float> %tmp5, %2 - %20 = bitcast float* %fltp to i8* - tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %20, <4 x float> %19, i32 1) + tail call void @llvm.arm.neon.vst1.p0.v4f32(ptr %fltp, <4 x float> %19, i32 1) ret void } -declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0.v4f32(ptr, <4 x float>, i32) nounwind diff --git a/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll b/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll index 1deb98631a4f66..b72c3079559582 100644 --- a/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll +++ b/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll @@ -3,17 +3,16 @@ %struct.__int8x8x2_t = type { [2 x <8 x i8>] } -define void @foo(%struct.__int8x8x2_t* nocapture %a, i8* %b) nounwind { +define void @foo(ptr nocapture %a, ptr %b) nounwind { entry: - %0 = bitcast %struct.__int8x8x2_t* %a to i128* ; [#uses=1] - %srcval = load i128, i128* %0, align 8 ; [#uses=2] + %srcval = load i128, ptr %a, align 8 ; [#uses=2] %tmp6 = trunc i128 %srcval to i64 ; [#uses=1] %tmp8 = lshr i128 %srcval, 64 ; [#uses=1] %tmp9 = trunc i128 %tmp8 to i64 ; [#uses=1] %tmp16.i = bitcast i64 %tmp6 to <8 x i8> ; <<8 x i8>> [#uses=1] %tmp20.i = bitcast i64 %tmp9 to <8 x i8> ; <<8 x i8>> [#uses=1] - tail call void @llvm.arm.neon.vst2.p0i8.v8i8(i8* %b, <8 x i8> %tmp16.i, <8 x i8> %tmp20.i, i32 1) nounwind + tail call void @llvm.arm.neon.vst2.p0.v8i8(ptr %b, <8 x i8> %tmp16.i, <8 x i8> %tmp20.i, i32 1) nounwind ret void } -declare void @llvm.arm.neon.vst2.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind +declare void @llvm.arm.neon.vst2.p0.v8i8(ptr, <8 x i8>, <8 x i8>, i32) nounwind diff --git a/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll b/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll index 6f55ac05805436..7bf577b5b7c8df 100644 --- a/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll +++ b/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll @@ -2,26 +2,26 @@ ; PR7421 %struct.CONTENTBOX = type { i32, i32, i32, i32, i32 } -%struct.FILE = type { i8* } -%struct.tilebox = type { %struct.tilebox*, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } +%struct.FILE = type { ptr } +%struct.tilebox = type { ptr, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.UNCOMBOX = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } -%struct.cellbox = type { i8*, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, double, double, double, double, double, i32, i32, %struct.CONTENTBOX*, %struct.UNCOMBOX*, [8 x %struct.tilebox*] } -%struct.termbox = type { %struct.termbox*, i32, i32, i32, i32, i32 } +%struct.cellbox = type { ptr, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, double, double, double, double, double, i32, i32, ptr, ptr, [8 x ptr] } +%struct.termbox = type { ptr, i32, i32, i32, i32, i32 } -@.str2708 = external constant [14 x i8], align 4 ; <[14 x i8]*> [#uses=1] +@.str2708 = external constant [14 x i8], align 4 ; [#uses=1] -define void @TW_oldinput(%struct.FILE* nocapture %fp) nounwind { +define void @TW_oldinput(ptr nocapture %fp) nounwind { entry: - %xcenter = alloca i32, align 4 ; [#uses=2] - %0 = call i32 (%struct.FILE*, i8*, ...) @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; [#uses=1] + %xcenter = alloca i32, align 4 ; [#uses=2] + %0 = call i32 (ptr, ptr, ...) @fscanf(ptr %fp, ptr @.str2708, ptr undef, ptr undef, ptr %xcenter, ptr null) nounwind ; [#uses=1] %1 = icmp eq i32 %0, 4 ; [#uses=1] br i1 %1, label %bb, label %return bb: ; preds = %bb445, %entry - %2 = load %struct.cellbox*, %struct.cellbox** undef, align 4 ; <%struct.cellbox*> [#uses=2] - %3 = getelementptr inbounds %struct.cellbox, %struct.cellbox* %2, i32 0, i32 3 ; [#uses=1] - store i32 undef, i32* %3, align 4 - %4 = load i32, i32* undef, align 4 ; [#uses=3] + %2 = load ptr, ptr undef, align 4 ; [#uses=2] + %3 = getelementptr inbounds %struct.cellbox, ptr %2, i32 0, i32 3 ; [#uses=1] + store i32 undef, ptr %3, align 4 + %4 = load i32, ptr undef, align 4 ; [#uses=3] %5 = icmp eq i32 undef, 1 ; [#uses=1] br i1 %5, label %bb10, label %bb445 @@ -29,12 +29,12 @@ bb10: ; preds = %bb br i1 undef, label %bb11, label %bb445 bb11: ; preds = %bb10 - %6 = load %struct.tilebox*, %struct.tilebox** undef, align 4 ; <%struct.tilebox*> [#uses=3] - %7 = load %struct.termbox*, %struct.termbox** null, align 4 ; <%struct.termbox*> [#uses=1] - %8 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %6, i32 0, i32 13 ; [#uses=1] - %9 = load i32, i32* %8, align 4 ; [#uses=3] - %10 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %6, i32 0, i32 15 ; [#uses=1] - %11 = load i32, i32* %10, align 4 ; [#uses=1] + %6 = load ptr, ptr undef, align 4 ; [#uses=3] + %7 = load ptr, ptr null, align 4 ; [#uses=1] + %8 = getelementptr inbounds %struct.tilebox, ptr %6, i32 0, i32 13 ; [#uses=1] + %9 = load i32, ptr %8, align 4 ; [#uses=3] + %10 = getelementptr inbounds %struct.tilebox, ptr %6, i32 0, i32 15 ; [#uses=1] + %11 = load i32, ptr %10, align 4 ; [#uses=1] br i1 false, label %bb12, label %bb13 bb12: ; preds = %bb11 @@ -57,7 +57,7 @@ bb21: ; preds = %bb13 %18 = zext i1 %not.460 to i32 ; [#uses=1] %iftmp.42.0 = add i32 %16, %iftmp.41.0.neg ; [#uses=1] %19 = add i32 %iftmp.42.0, %18 ; [#uses=1] - store i32 %19, i32* undef, align 4 + store i32 %19, ptr undef, align 4 %20 = sub nsw i32 0, %9 ; [#uses=1] %21 = sitofp i32 %20 to double ; [#uses=1] %22 = fdiv double %21, 0.000000e+00 ; [#uses=2] @@ -67,34 +67,34 @@ bb21: ; preds = %bb13 %25 = zext i1 %not.461 to i32 ; [#uses=1] %iftmp.43.0 = add i32 %23, %iftmp.41.0.neg ; [#uses=1] %26 = add i32 %iftmp.43.0, %25 ; [#uses=1] - %27 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %6, i32 0, i32 10 ; [#uses=1] - store i32 %26, i32* %27, align 4 + %27 = getelementptr inbounds %struct.tilebox, ptr %6, i32 0, i32 10 ; [#uses=1] + store i32 %26, ptr %27, align 4 %28 = fptosi double undef to i32 ; [#uses=1] %iftmp.45.0 = add i32 %28, %iftmp.40.0.neg ; [#uses=1] %29 = add i32 %iftmp.45.0, 0 ; [#uses=1] - store i32 %29, i32* undef, align 4 + store i32 %29, ptr undef, align 4 br label %bb43.loopexit bb36: ; preds = %bb43.loopexit, %bb36 - %termptr.0478 = phi %struct.termbox* [ %42, %bb36 ], [ %7, %bb43.loopexit ] ; <%struct.termbox*> [#uses=1] - %30 = load i32, i32* undef, align 4 ; [#uses=1] + %termptr.0478 = phi ptr [ %42, %bb36 ], [ %7, %bb43.loopexit ] ; [#uses=1] + %30 = load i32, ptr undef, align 4 ; [#uses=1] %31 = sub nsw i32 %30, %9 ; [#uses=1] %32 = sitofp i32 %31 to double ; [#uses=1] %33 = fdiv double %32, 0.000000e+00 ; [#uses=1] %34 = fptosi double %33 to i32 ; [#uses=1] %iftmp.46.0 = add i32 %34, %iftmp.41.0.neg ; [#uses=1] %35 = add i32 %iftmp.46.0, 0 ; [#uses=1] - store i32 %35, i32* undef, align 4 + store i32 %35, ptr undef, align 4 %36 = sub nsw i32 0, %11 ; [#uses=1] %37 = sitofp i32 %36 to double ; [#uses=1] %38 = fmul double %37, 0.000000e+00 ; [#uses=1] %39 = fptosi double %38 to i32 ; [#uses=1] %iftmp.47.0 = add i32 %39, %iftmp.40.0.neg ; [#uses=1] %40 = add i32 %iftmp.47.0, 0 ; [#uses=1] - store i32 %40, i32* undef, align 4 - %41 = getelementptr inbounds %struct.termbox, %struct.termbox* %termptr.0478, i32 0, i32 0 ; <%struct.termbox**> [#uses=1] - %42 = load %struct.termbox*, %struct.termbox** %41, align 4 ; <%struct.termbox*> [#uses=2] - %43 = icmp eq %struct.termbox* %42, null ; [#uses=1] + store i32 %40, ptr undef, align 4 + %41 = getelementptr inbounds %struct.termbox, ptr %termptr.0478, i32 0, i32 0 ; [#uses=1] + %42 = load ptr, ptr %41, align 4 ; [#uses=2] + %43 = icmp eq ptr %42, null ; [#uses=1] br i1 %43, label %bb52.loopexit, label %bb36 bb43.loopexit: ; preds = %bb21, %bb13 @@ -127,17 +127,17 @@ bb248: ; preds = %bb322, %bb.nph485 br i1 %45, label %bb322, label %bb249 bb249: ; preds = %bb248 - %46 = getelementptr inbounds %struct.cellbox, %struct.cellbox* %2, i32 0, i32 21, i32 undef ; <%struct.tilebox**> [#uses=1] - %47 = load %struct.tilebox*, %struct.tilebox** %46, align 4 ; <%struct.tilebox*> [#uses=1] - %48 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %47, i32 0, i32 11 ; [#uses=1] - store i32 undef, i32* %48, align 4 + %46 = getelementptr inbounds %struct.cellbox, ptr %2, i32 0, i32 21, i32 undef ; [#uses=1] + %47 = load ptr, ptr %46, align 4 ; [#uses=1] + %48 = getelementptr inbounds %struct.tilebox, ptr %47, i32 0, i32 11 ; [#uses=1] + store i32 undef, ptr %48, align 4 unreachable bb322: ; preds = %bb248 br i1 undef, label %bb248, label %bb445 bb445: ; preds = %bb322, %bb10, %bb - %49 = call i32 (%struct.FILE*, i8*, ...) @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; [#uses=1] + %49 = call i32 (ptr, ptr, ...) @fscanf(ptr %fp, ptr @.str2708, ptr undef, ptr undef, ptr %xcenter, ptr null) nounwind ; [#uses=1] %50 = icmp eq i32 %49, 4 ; [#uses=1] br i1 %50, label %bb, label %return @@ -145,4 +145,4 @@ return: ; preds = %bb445, %entry ret void } -declare i32 @fscanf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind +declare i32 @fscanf(ptr nocapture, ptr nocapture, ...) nounwind diff --git a/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll b/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll index a1dcdd6283debb..938787af962448 100644 --- a/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll +++ b/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll @@ -2,116 +2,110 @@ ; PR 7433 ; XFAIL: * -%0 = type { i8*, i8* } -%1 = type { i8*, i8*, i8* } +%0 = type { ptr, ptr } +%1 = type { ptr, ptr, ptr } %"class.llvm::Record" = type { i32, %"class.std::basic_string", %"class.llvm::SMLoc", %"class.std::vector", %"class.std::vector", %"class.std::vector" } -%"class.llvm::RecordVal" = type { %"class.std::basic_string", %"struct.llvm::Init"*, i32, %"struct.llvm::Init"* } -%"class.llvm::SMLoc" = type { i8* } +%"class.llvm::RecordVal" = type { %"class.std::basic_string", ptr, i32, ptr } +%"class.llvm::SMLoc" = type { ptr } %"class.llvm::StringInit" = type { [8 x i8], %"class.std::basic_string" } %"class.std::basic_string" = type { %"class.llvm::SMLoc" } %"class.std::vector" = type { [12 x i8] } -%"struct.llvm::Init" = type { i32 (...)** } +%"struct.llvm::Init" = type { ptr } -@_ZTIN4llvm5RecTyE = external constant %0 ; <%0*> [#uses=1] -@_ZTIN4llvm4InitE = external constant %0 ; <%0*> [#uses=1] -@_ZTIN4llvm11RecordRecTyE = external constant %1 ; <%1*> [#uses=1] -@.str8 = external constant [47 x i8] ; <[47 x i8]*> [#uses=1] -@_ZTIN4llvm9UnsetInitE = external constant %1 ; <%1*> [#uses=1] -@.str51 = external constant [45 x i8] ; <[45 x i8]*> [#uses=1] -@__PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs = external constant [116 x i8] ; <[116 x i8]*> [#uses=1] +@_ZTIN4llvm5RecTyE = external constant %0 ; [#uses=1] +@_ZTIN4llvm4InitE = external constant %0 ; [#uses=1] +@_ZTIN4llvm11RecordRecTyE = external constant %1 ; [#uses=1] +@.str8 = external constant [47 x i8] ; [#uses=1] +@_ZTIN4llvm9UnsetInitE = external constant %1 ; [#uses=1] +@.str51 = external constant [45 x i8] ; [#uses=1] +@__PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs = external constant [116 x i8] ; [#uses=1] -@_ZN4llvm9RecordValC1ERKSsPNS_5RecTyEj = alias void (%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32), void (%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32)* @_ZN4llvm9RecordValC2ERKSsPNS_5RecTyEj ; [#uses=0] +@_ZN4llvm9RecordValC1ERKSsPNS_5RecTyEj = alias void (ptr, ptr, ptr, i32), ptr @_ZN4llvm9RecordValC2ERKSsPNS_5RecTyEj ; [#uses=0] -declare i8* @__dynamic_cast(i8*, i8*, i8*, i32) +declare ptr @__dynamic_cast(ptr, ptr, ptr, i32) -declare void @__assert_fail(i8*, i8*, i32, i8*) noreturn +declare void @__assert_fail(ptr, ptr, i32, ptr) noreturn -declare void @_ZN4llvm9RecordValC2ERKSsPNS_5RecTyEj(%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32) align 2 +declare void @_ZN4llvm9RecordValC2ERKSsPNS_5RecTyEj(ptr, ptr, ptr, i32) align 2 -define %"struct.llvm::Init"* @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs(%"class.llvm::StringInit"* %this, %"class.llvm::Record"* %R, %"class.llvm::RecordVal"* %RV, %"class.std::basic_string"* %FieldName) align 2 { +define ptr @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs(ptr %this, ptr %R, ptr %RV, ptr %FieldName) align 2 { ;CHECK: ldmia sp!, {r4, r5, r6, r7, r8, lr} ;CHECK: bx r12 @ TAILCALL entry: - %.loc = alloca i32 ; [#uses=2] - %tmp.i = getelementptr inbounds %"class.llvm::StringInit", %"class.llvm::StringInit"* %this, i32 0, i32 0, i32 4 ; [#uses=1] - %0 = bitcast i8* %tmp.i to %"struct.llvm::Init"** ; <%"struct.llvm::Init"**> [#uses=1] - %tmp2.i = load %"struct.llvm::Init"*, %"struct.llvm::Init"** %0 ; <%"struct.llvm::Init"*> [#uses=2] - %1 = icmp eq %"struct.llvm::Init"* %tmp2.i, null ; [#uses=1] - br i1 %1, label %entry.return_crit_edge, label %tmpbb + %.loc = alloca i32 ; [#uses=2] + %tmp.i = getelementptr inbounds %"class.llvm::StringInit", ptr %this, i32 0, i32 0, i32 4 ; [#uses=1] + %tmp2.i = load ptr, ptr %tmp.i ; [#uses=2] + %0 = icmp eq ptr %tmp2.i, null ; [#uses=1] + br i1 %0, label %entry.return_crit_edge, label %tmpbb entry.return_crit_edge: ; preds = %entry br label %return tmpbb: ; preds = %entry - %2 = bitcast %"struct.llvm::Init"* %tmp2.i to i8* ; [#uses=1] - %3 = tail call i8* @__dynamic_cast(i8* %2, i8* bitcast (%0* @_ZTIN4llvm5RecTyE to i8*), i8* bitcast (%1* @_ZTIN4llvm11RecordRecTyE to i8*), i32 -1) ; [#uses=1] - %phitmp = icmp eq i8* %3, null ; [#uses=1] + %1 = tail call ptr @__dynamic_cast(ptr %tmp2.i, ptr @_ZTIN4llvm5RecTyE, ptr @_ZTIN4llvm11RecordRecTyE, i32 -1) ; [#uses=1] + %phitmp = icmp eq ptr %1, null ; [#uses=1] br i1 %phitmp, label %.return_crit_edge, label %if.then .return_crit_edge: ; preds = %tmpbb br label %return if.then: ; preds = %tmpbb - %tmp2.i.i.i.i = getelementptr inbounds %"class.llvm::StringInit", %"class.llvm::StringInit"* %this, i32 0, i32 1, i32 0, i32 0 ; [#uses=1] - %tmp3.i.i.i.i = load i8*, i8** %tmp2.i.i.i.i ; [#uses=2] - %arrayidx.i.i.i.i = getelementptr inbounds i8, i8* %tmp3.i.i.i.i, i32 -12 ; [#uses=1] - %tmp.i.i.i = bitcast i8* %arrayidx.i.i.i.i to i32* ; [#uses=1] - %tmp2.i.i.i = load i32, i32* %tmp.i.i.i ; [#uses=1] - %tmp.i5 = getelementptr inbounds %"class.llvm::Record", %"class.llvm::Record"* %R, i32 0, i32 4 ; <%"class.std::vector"*> [#uses=1] - %tmp2.i.i = getelementptr inbounds %"class.llvm::Record", %"class.llvm::Record"* %R, i32 0, i32 4, i32 0, i32 4 ; [#uses=1] - %4 = bitcast i8* %tmp2.i.i to %"class.llvm::RecordVal"** ; <%"class.llvm::RecordVal"**> [#uses=1] - %tmp3.i.i6 = load %"class.llvm::RecordVal"*, %"class.llvm::RecordVal"** %4 ; <%"class.llvm::RecordVal"*> [#uses=1] - %tmp5.i.i = bitcast %"class.std::vector"* %tmp.i5 to %"class.llvm::RecordVal"** ; <%"class.llvm::RecordVal"**> [#uses=1] - %tmp6.i.i = load %"class.llvm::RecordVal"*, %"class.llvm::RecordVal"** %tmp5.i.i ; <%"class.llvm::RecordVal"*> [#uses=5] - %sub.ptr.lhs.cast.i.i = ptrtoint %"class.llvm::RecordVal"* %tmp3.i.i6 to i32 ; [#uses=1] - %sub.ptr.rhs.cast.i.i = ptrtoint %"class.llvm::RecordVal"* %tmp6.i.i to i32 ; [#uses=1] + %tmp2.i.i.i.i = getelementptr inbounds %"class.llvm::StringInit", ptr %this, i32 0, i32 1, i32 0, i32 0 ; [#uses=1] + %tmp3.i.i.i.i = load ptr, ptr %tmp2.i.i.i.i ; [#uses=2] + %arrayidx.i.i.i.i = getelementptr inbounds i8, ptr %tmp3.i.i.i.i, i32 -12 ; [#uses=1] + %tmp2.i.i.i = load i32, ptr %arrayidx.i.i.i.i ; [#uses=1] + %tmp.i5 = getelementptr inbounds %"class.llvm::Record", ptr %R, i32 0, i32 4 ; [#uses=1] + %tmp2.i.i = getelementptr inbounds %"class.llvm::Record", ptr %R, i32 0, i32 4, i32 0, i32 4 ; [#uses=1] + %tmp3.i.i6 = load ptr, ptr %tmp2.i.i ; [#uses=1] + %tmp6.i.i = load ptr, ptr %tmp.i5 ; [#uses=5] + %sub.ptr.lhs.cast.i.i = ptrtoint ptr %tmp3.i.i6 to i32 ; [#uses=1] + %sub.ptr.rhs.cast.i.i = ptrtoint ptr %tmp6.i.i to i32 ; [#uses=1] %sub.ptr.sub.i.i = sub i32 %sub.ptr.lhs.cast.i.i, %sub.ptr.rhs.cast.i.i ; [#uses=1] %sub.ptr.div.i.i = ashr i32 %sub.ptr.sub.i.i, 4 ; [#uses=1] br label %codeRepl codeRepl: ; preds = %if.then - %targetBlock = call i1 @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs_for.cond.i(i32 %sub.ptr.div.i.i, %"class.llvm::RecordVal"* %tmp6.i.i, i32 %tmp2.i.i.i, i8* %tmp3.i.i.i.i, i32* %.loc) ; [#uses=1] - %.reload = load i32, i32* %.loc ; [#uses=3] + %targetBlock = call i1 @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs_for.cond.i(i32 %sub.ptr.div.i.i, ptr %tmp6.i.i, i32 %tmp2.i.i.i, ptr %tmp3.i.i.i.i, ptr %.loc) ; [#uses=1] + %.reload = load i32, ptr %.loc ; [#uses=3] br i1 %targetBlock, label %for.cond.i.return_crit_edge, label %_ZN4llvm6Record8getValueENS_9StringRefE.exit for.cond.i.return_crit_edge: ; preds = %codeRepl br label %return _ZN4llvm6Record8getValueENS_9StringRefE.exit: ; preds = %codeRepl - %add.ptr.i.i = getelementptr inbounds %"class.llvm::RecordVal", %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload ; <%"class.llvm::RecordVal"*> [#uses=2] - %tobool5 = icmp eq %"class.llvm::RecordVal"* %add.ptr.i.i, null ; [#uses=1] + %add.ptr.i.i = getelementptr inbounds %"class.llvm::RecordVal", ptr %tmp6.i.i, i32 %.reload ; [#uses=2] + %tobool5 = icmp eq ptr %add.ptr.i.i, null ; [#uses=1] br i1 %tobool5, label %_ZN4llvm6Record8getValueENS_9StringRefE.exit.return_crit_edge, label %if.then6 _ZN4llvm6Record8getValueENS_9StringRefE.exit.return_crit_edge: ; preds = %_ZN4llvm6Record8getValueENS_9StringRefE.exit br label %return if.then6: ; preds = %_ZN4llvm6Record8getValueENS_9StringRefE.exit - %cmp = icmp eq %"class.llvm::RecordVal"* %add.ptr.i.i, %RV ; [#uses=1] + %cmp = icmp eq ptr %add.ptr.i.i, %RV ; [#uses=1] br i1 %cmp, label %if.then6.if.end_crit_edge, label %land.lhs.true if.then6.if.end_crit_edge: ; preds = %if.then6 br label %if.end land.lhs.true: ; preds = %if.then6 - %tobool10 = icmp eq %"class.llvm::RecordVal"* %RV, null ; [#uses=1] + %tobool10 = icmp eq ptr %RV, null ; [#uses=1] br i1 %tobool10, label %lor.lhs.false, label %land.lhs.true.return_crit_edge land.lhs.true.return_crit_edge: ; preds = %land.lhs.true br label %return lor.lhs.false: ; preds = %land.lhs.true - %tmp.i3 = getelementptr inbounds %"class.llvm::RecordVal", %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1] - %tmp2.i4 = load %"struct.llvm::Init"*, %"struct.llvm::Init"** %tmp.i3 ; <%"struct.llvm::Init"*> [#uses=2] - %5 = icmp eq %"struct.llvm::Init"* %tmp2.i4, null ; [#uses=1] - br i1 %5, label %lor.lhs.false.if.end_crit_edge, label %tmpbb1 + %tmp.i3 = getelementptr inbounds %"class.llvm::RecordVal", ptr %tmp6.i.i, i32 %.reload, i32 3 ; [#uses=1] + %tmp2.i4 = load ptr, ptr %tmp.i3 ; [#uses=2] + %2 = icmp eq ptr %tmp2.i4, null ; [#uses=1] + br i1 %2, label %lor.lhs.false.if.end_crit_edge, label %tmpbb1 lor.lhs.false.if.end_crit_edge: ; preds = %lor.lhs.false br label %if.end tmpbb1: ; preds = %lor.lhs.false - %6 = bitcast %"struct.llvm::Init"* %tmp2.i4 to i8* ; [#uses=1] - %7 = tail call i8* @__dynamic_cast(i8* %6, i8* bitcast (%0* @_ZTIN4llvm4InitE to i8*), i8* bitcast (%1* @_ZTIN4llvm9UnsetInitE to i8*), i32 -1) ; [#uses=1] - %phitmp32 = icmp eq i8* %7, null ; [#uses=1] + %3 = tail call ptr @__dynamic_cast(ptr %tmp2.i4, ptr @_ZTIN4llvm4InitE, ptr @_ZTIN4llvm9UnsetInitE, i32 -1) ; [#uses=1] + %phitmp32 = icmp eq ptr %3, null ; [#uses=1] br i1 %phitmp32, label %.if.end_crit_edge, label %.return_crit_edge1 .return_crit_edge1: ; preds = %tmpbb1 @@ -121,26 +115,24 @@ tmpbb1: ; preds = %lor.lhs.false br label %if.end if.end: ; preds = %.if.end_crit_edge, %lor.lhs.false.if.end_crit_edge, %if.then6.if.end_crit_edge - %tmp.i1 = getelementptr inbounds %"class.llvm::RecordVal", %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1] - %tmp2.i2 = load %"struct.llvm::Init"*, %"struct.llvm::Init"** %tmp.i1 ; <%"struct.llvm::Init"*> [#uses=3] - %8 = bitcast %"class.llvm::StringInit"* %this to %"struct.llvm::Init"* ; <%"struct.llvm::Init"*> [#uses=1] - %cmp19 = icmp eq %"struct.llvm::Init"* %tmp2.i2, %8 ; [#uses=1] + %tmp.i1 = getelementptr inbounds %"class.llvm::RecordVal", ptr %tmp6.i.i, i32 %.reload, i32 3 ; [#uses=1] + %tmp2.i2 = load ptr, ptr %tmp.i1 ; [#uses=3] + %cmp19 = icmp eq ptr %tmp2.i2, %this ; [#uses=1] br i1 %cmp19, label %cond.false, label %cond.end cond.false: ; preds = %if.end - tail call void @__assert_fail(i8* getelementptr inbounds ([45 x i8], [45 x i8]* @.str51, i32 0, i32 0), i8* getelementptr inbounds ([47 x i8], [47 x i8]* @.str8, i32 0, i32 0), i32 1141, i8* getelementptr inbounds ([116 x i8], [116 x i8]* @__PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs, i32 0, i32 0)) noreturn + tail call void @__assert_fail(ptr @.str51, ptr @.str8, i32 1141, ptr @__PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs) noreturn unreachable cond.end: ; preds = %if.end - %9 = bitcast %"struct.llvm::Init"* %tmp2.i2 to %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)***> [#uses=1] - %10 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**, %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** %9 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1] - %vfn = getelementptr inbounds %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*, %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %10, i32 8 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1] - %11 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*, %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %vfn ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*> [#uses=1] - %call25 = tail call %"struct.llvm::Init"* %11(%"struct.llvm::Init"* %tmp2.i2, %"class.llvm::Record"* %R, %"class.llvm::RecordVal"* %RV, %"class.std::basic_string"* %FieldName) ; <%"struct.llvm::Init"*> [#uses=1] - ret %"struct.llvm::Init"* %call25 + %4 = load ptr, ptr %tmp2.i2 ; [#uses=1] + %vfn = getelementptr inbounds ptr, ptr %4, i32 8 ; [#uses=1] + %5 = load ptr, ptr %vfn ; [#uses=1] + %call25 = tail call ptr %5(ptr %tmp2.i2, ptr %R, ptr %RV, ptr %FieldName) ; [#uses=1] + ret ptr %call25 return: ; preds = %.return_crit_edge1, %land.lhs.true.return_crit_edge, %_ZN4llvm6Record8getValueENS_9StringRefE.exit.return_crit_edge, %for.cond.i.return_crit_edge, %.return_crit_edge, %entry.return_crit_edge - ret %"struct.llvm::Init"* null + ret ptr null } -declare i1 @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs_for.cond.i(i32, %"class.llvm::RecordVal"*, i32, i8*, i32*) +declare i1 @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs_for.cond.i(i32, ptr, i32, ptr, ptr) diff --git a/llvm/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll b/llvm/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll index 9ffb68cdeac846..0973d17d3c47b6 100644 --- a/llvm/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll +++ b/llvm/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll @@ -7,11 +7,11 @@ target triple = "thumbv7-apple-darwin3.0.0-iphoneos" @length = common global i32 0, align 4, !dbg !0 ; Function Attrs: nounwind optsize -define void @x0(i8* nocapture %buf, i32 %nbytes) #0 { +define void @x0(ptr nocapture %buf, i32 %nbytes) #0 { entry: - tail call void @llvm.dbg.value(metadata i8* %buf, metadata !8, metadata !14), !dbg !15 + tail call void @llvm.dbg.value(metadata ptr %buf, metadata !8, metadata !14), !dbg !15 tail call void @llvm.dbg.value(metadata i32 %nbytes, metadata !16, metadata !14), !dbg !18 - %tmp = load i32, i32* @length, !dbg !19 + %tmp = load i32, ptr @length, !dbg !19 %cmp = icmp eq i32 %tmp, -1, !dbg !19 %cmp.not = xor i1 %cmp, true %cmp3 = icmp ult i32 %tmp, %nbytes, !dbg !19 @@ -24,7 +24,7 @@ entry: while.cond: ; preds = %while.body, %entry %0 = phi i32 [ 0, %entry ], [ %inc, %while.body ] - %buf.addr.0 = getelementptr i8, i8* %buf, i32 %0 + %buf.addr.0 = getelementptr i8, ptr %buf, i32 %0 %cmp7 = icmp ult i32 %0, %nbytes.addr.0, !dbg !23 br i1 %cmp7, label %land.rhs, label %while.end, !dbg !23 @@ -35,7 +35,7 @@ land.rhs: ; preds = %while.cond while.body: ; preds = %land.rhs %conv = trunc i32 %call to i8, !dbg !24 - store i8 %conv, i8* %buf.addr.0, !dbg !24 + store i8 %conv, ptr %buf.addr.0, !dbg !24 %inc = add i32 %0, 1, !dbg !26 br label %while.cond, !dbg !27 diff --git a/llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll b/llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll index c0b94134bec9d9..ede148b73c412a 100644 --- a/llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll +++ b/llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll @@ -14,12 +14,12 @@ target triple = "thumbv7-apple-darwin10" ; CHECK-NOT: vld1.64 {d16, d17} ; CHECK: vmov.f64 -define i32 @test(i8* %arg) nounwind { +define i32 @test(ptr %arg) nounwind { entry: - %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8* %arg, i32 1) + %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0(ptr %arg, i32 1) %1 = shufflevector <2 x i64> undef, <2 x i64> %0, <2 x i32> - store <2 x i64> %1, <2 x i64>* undef, align 16 + store <2 x i64> %1, ptr undef, align 16 ret i32 undef } -declare <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8*, i32) nounwind readonly +declare <2 x i64> @llvm.arm.neon.vld1.v2i64.p0(ptr, i32) nounwind readonly diff --git a/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll b/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll index 03362a8e51f916..47f5eb253d7573 100644 --- a/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll +++ b/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll @@ -1,15 +1,15 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o /dev/null -@.str271 = external constant [21 x i8], align 4 ; <[21 x i8]*> [#uses=1] -@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32, i8**)* @main to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] +@.str271 = external constant [21 x i8], align 4 ; [#uses=1] +@llvm.used = appending global [1 x ptr] [ptr @main], section "llvm.metadata" ; [#uses=0] -define i32 @main(i32 %argc, i8** %argv) nounwind { +define i32 @main(i32 %argc, ptr %argv) nounwind { entry: %0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> ; <<2 x i64>> [#uses=1] - store <2 x i64> %0, <2 x i64>* undef, align 16 - %val4723 = load <8 x i16>, <8 x i16>* undef ; <<8 x i16>> [#uses=1] - call void @PrintShortX(i8* getelementptr inbounds ([21 x i8], [21 x i8]* @.str271, i32 0, i32 0), <8 x i16> %val4723, i32 0) nounwind + store <2 x i64> %0, ptr undef, align 16 + %val4723 = load <8 x i16>, ptr undef ; <<8 x i16>> [#uses=1] + call void @PrintShortX(ptr @.str271, <8 x i16> %val4723, i32 0) nounwind ret i32 undef } -declare void @PrintShortX(i8*, <8 x i16>, i32) nounwind +declare void @PrintShortX(ptr, <8 x i16>, i32) nounwind diff --git a/llvm/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll b/llvm/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll index a876d998e75029..31b255eb581188 100644 --- a/llvm/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll +++ b/llvm/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll @@ -3,92 +3,91 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" target triple = "thumbv7-apple-darwin10.0.0" -%0 = type { i8*, i8* } +%0 = type { ptr, ptr } %struct.A = type { i32 } -@d = internal global i32 0, align 4 ; [#uses=6] -@_ZTVN10__cxxabiv117__class_type_infoE = external global i8* ; [#uses=1] -@_ZTS1A = internal constant [3 x i8] c"1A\00" ; <[3 x i8]*> [#uses=1] -@_ZTI1A = internal constant %0 { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i32 2) to i8*), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @_ZTS1A, i32 0, i32 0) } ; <%0*> [#uses=1] -@.str2 = private constant [18 x i8] c"c == %d, d == %d\0A\00" ; <[18 x i8]*> [#uses=1] -@.str3 = private constant [16 x i8] c"A(const A&) %d\0A\00" ; <[16 x i8]*> [#uses=1] -@.str4 = private constant [9 x i8] c"~A() %d\0A\00" ; <[9 x i8]*> [#uses=1] -@.str5 = private constant [8 x i8] c"A() %d\0A\00" ; <[8 x i8]*> [#uses=1] -@str = internal constant [14 x i8] c"Throwing 1...\00" ; <[14 x i8]*> [#uses=1] -@str1 = internal constant [8 x i8] c"Caught.\00" ; <[8 x i8]*> [#uses=1] +@d = internal global i32 0, align 4 ; [#uses=6] +@_ZTVN10__cxxabiv117__class_type_infoE = external global ptr ; [#uses=1] +@_ZTS1A = internal constant [3 x i8] c"1A\00" ; [#uses=1] +@_ZTI1A = internal constant %0 { ptr getelementptr inbounds (ptr, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i32 2), ptr @_ZTS1A } ; [#uses=1] +@.str2 = private constant [18 x i8] c"c == %d, d == %d\0A\00" ; [#uses=1] +@.str3 = private constant [16 x i8] c"A(const A&) %d\0A\00" ; [#uses=1] +@.str4 = private constant [9 x i8] c"~A() %d\0A\00" ; [#uses=1] +@.str5 = private constant [8 x i8] c"A() %d\0A\00" ; [#uses=1] +@str = internal constant [14 x i8] c"Throwing 1...\00" ; [#uses=1] +@str1 = internal constant [8 x i8] c"Caught.\00" ; [#uses=1] -declare i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(ptr nocapture, ...) nounwind -declare i8* @__cxa_allocate_exception(i32) +declare ptr @__cxa_allocate_exception(i32) declare i32 @__gxx_personality_sj0(...) -declare i32 @llvm.eh.typeid.for(i8*) nounwind +declare i32 @llvm.eh.typeid.for(ptr) nounwind -declare void @_Unwind_SjLj_Resume(i8*) +declare void @_Unwind_SjLj_Resume(ptr) -define internal void @_ZN1AD1Ev(%struct.A* nocapture %this) nounwind ssp align 2 { +define internal void @_ZN1AD1Ev(ptr nocapture %this) nounwind ssp align 2 { entry: - %tmp.i = getelementptr inbounds %struct.A, %struct.A* %this, i32 0, i32 0 ; [#uses=1] - %tmp2.i = load i32, i32* %tmp.i ; [#uses=1] - %call.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str4, i32 0, i32 0), i32 %tmp2.i) nounwind ; [#uses=0] - %tmp3.i = load i32, i32* @d ; [#uses=1] + %tmp.i = getelementptr inbounds %struct.A, ptr %this, i32 0, i32 0 ; [#uses=1] + %tmp2.i = load i32, ptr %tmp.i ; [#uses=1] + %call.i = tail call i32 (ptr, ...) @printf(ptr @.str4, i32 %tmp2.i) nounwind ; [#uses=0] + %tmp3.i = load i32, ptr @d ; [#uses=1] %inc.i = add nsw i32 %tmp3.i, 1 ; [#uses=1] - store i32 %inc.i, i32* @d + store i32 %inc.i, ptr @d ret void } -declare void @__cxa_throw(i8*, i8*, i8*) +declare void @__cxa_throw(ptr, ptr, ptr) -define i32 @main() ssp personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) { +define i32 @main() ssp personality ptr @__gxx_personality_sj0 { entry: - %puts.i = tail call i32 @puts(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @str, i32 0, i32 0)) ; [#uses=0] - %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind ; [#uses=2] - %tmp2.i.i.i = bitcast i8* %exception.i to i32* ; [#uses=1] - store i32 1, i32* %tmp2.i.i.i - %call.i.i.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str5, i32 0, i32 0), i32 1) nounwind ; [#uses=0] - invoke void @__cxa_throw(i8* %exception.i, i8* bitcast (%0* @_ZTI1A to i8*), i8* bitcast (void (%struct.A*)* @_ZN1AD1Ev to i8*)) noreturn + %puts.i = tail call i32 @puts(ptr @str) ; [#uses=0] + %exception.i = tail call ptr @__cxa_allocate_exception(i32 4) nounwind ; [#uses=2] + store i32 1, ptr %exception.i + %call.i.i.i = tail call i32 (ptr, ...) @printf(ptr @.str5, i32 1) nounwind ; [#uses=0] + invoke void @__cxa_throw(ptr %exception.i, ptr @_ZTI1A, ptr @_ZN1AD1Ev) noreturn to label %.noexc unwind label %lpad .noexc: ; preds = %entry unreachable try.cont: ; preds = %lpad - %0 = tail call i8* @__cxa_get_exception_ptr(i8* %exn) nounwind ; [#uses=0] - %call.i.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str3, i32 0, i32 0), i32 2) nounwind ; [#uses=0] - %1 = tail call i8* @__cxa_begin_catch(i8* %exn) nounwind ; [#uses=0] - %puts = tail call i32 @puts(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @str1, i32 0, i32 0)) ; [#uses=0] - %call.i.i3 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str4, i32 0, i32 0), i32 2) nounwind ; [#uses=0] - %tmp3.i.i = load i32, i32* @d ; [#uses=1] + %0 = tail call ptr @__cxa_get_exception_ptr(ptr %exn) nounwind ; [#uses=0] + %call.i.i = tail call i32 (ptr, ...) @printf(ptr @.str3, i32 2) nounwind ; [#uses=0] + %1 = tail call ptr @__cxa_begin_catch(ptr %exn) nounwind ; [#uses=0] + %puts = tail call i32 @puts(ptr @str1) ; [#uses=0] + %call.i.i3 = tail call i32 (ptr, ...) @printf(ptr @.str4, i32 2) nounwind ; [#uses=0] + %tmp3.i.i = load i32, ptr @d ; [#uses=1] %inc.i.i4 = add nsw i32 %tmp3.i.i, 1 ; [#uses=1] - store i32 %inc.i.i4, i32* @d + store i32 %inc.i.i4, ptr @d tail call void @__cxa_end_catch() - %tmp13 = load i32, i32* @d ; [#uses=1] - %call14 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str2, i32 0, i32 0), i32 2, i32 %tmp13) ; [#uses=0] - %tmp16 = load i32, i32* @d ; [#uses=1] + %tmp13 = load i32, ptr @d ; [#uses=1] + %call14 = tail call i32 (ptr, ...) @printf(ptr @.str2, i32 2, i32 %tmp13) ; [#uses=0] + %tmp16 = load i32, ptr @d ; [#uses=1] %cmp = icmp ne i32 %tmp16, 2 ; [#uses=1] %conv = zext i1 %cmp to i32 ; [#uses=1] ret i32 %conv lpad: ; preds = %entry - %exn.ptr = landingpad { i8*, i32 } - catch i8* bitcast (%0* @_ZTI1A to i8*) - catch i8* null - %exn = extractvalue { i8*, i32 } %exn.ptr, 0 - %eh.selector = extractvalue { i8*, i32 } %exn.ptr, 1 - %2 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (%0* @_ZTI1A to i8*)) nounwind ; [#uses=1] + %exn.ptr = landingpad { ptr, i32 } + catch ptr @_ZTI1A + catch ptr null + %exn = extractvalue { ptr, i32 } %exn.ptr, 0 + %eh.selector = extractvalue { ptr, i32 } %exn.ptr, 1 + %2 = tail call i32 @llvm.eh.typeid.for(ptr @_ZTI1A) nounwind ; [#uses=1] %3 = icmp eq i32 %eh.selector, %2 ; [#uses=1] br i1 %3, label %try.cont, label %eh.resume eh.resume: ; preds = %lpad - tail call void @_Unwind_SjLj_Resume(i8* %exn) noreturn + tail call void @_Unwind_SjLj_Resume(ptr %exn) noreturn unreachable } -declare i8* @__cxa_get_exception_ptr(i8*) +declare ptr @__cxa_get_exception_ptr(ptr) -declare i8* @__cxa_begin_catch(i8*) +declare ptr @__cxa_begin_catch(ptr) declare void @__cxa_end_catch() -declare i32 @puts(i8* nocapture) nounwind +declare i32 @puts(ptr nocapture) nounwind diff --git a/llvm/test/CodeGen/ARM/2010-08-04-EHCrash.ll b/llvm/test/CodeGen/ARM/2010-08-04-EHCrash.ll index 69482cc8b35bc4..3f5f581229d6f2 100644 --- a/llvm/test/CodeGen/ARM/2010-08-04-EHCrash.ll +++ b/llvm/test/CodeGen/ARM/2010-08-04-EHCrash.ll @@ -1,29 +1,29 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 ; -define linkonce_odr arm_apcscc void @func1() personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) { +define linkonce_odr arm_apcscc void @func1() personality ptr @__gxx_personality_sj0 { entry: - %save_filt.936 = alloca i32 ; [#uses=2] - %save_eptr.935 = alloca i8* ; [#uses=2] - %eh_exception = alloca i8* ; [#uses=5] - %eh_selector = alloca i32 ; [#uses=3] + %save_filt.936 = alloca i32 ; [#uses=2] + %save_eptr.935 = alloca ptr ; [#uses=2] + %eh_exception = alloca ptr ; [#uses=5] + %eh_selector = alloca i32 ; [#uses=3] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] call arm_apcscc void @func2() br label %return bb: ; No predecessors! - %eh_select = load i32, i32* %eh_selector ; [#uses=1] - store i32 %eh_select, i32* %save_filt.936, align 4 - %eh_value = load i8*, i8** %eh_exception ; [#uses=1] - store i8* %eh_value, i8** %save_eptr.935, align 4 + %eh_select = load i32, ptr %eh_selector ; [#uses=1] + store i32 %eh_select, ptr %save_filt.936, align 4 + %eh_value = load ptr, ptr %eh_exception ; [#uses=1] + store ptr %eh_value, ptr %save_eptr.935, align 4 invoke arm_apcscc void @func3() to label %invcont unwind label %lpad invcont: ; preds = %bb - %tmp6 = load i8*, i8** %save_eptr.935, align 4 ; [#uses=1] - store i8* %tmp6, i8** %eh_exception, align 4 - %tmp7 = load i32, i32* %save_filt.936, align 4 ; [#uses=1] - store i32 %tmp7, i32* %eh_selector, align 4 + %tmp6 = load ptr, ptr %save_eptr.935, align 4 ; [#uses=1] + store ptr %tmp6, ptr %eh_exception, align 4 + %tmp7 = load i32, ptr %save_filt.936, align 4 ; [#uses=1] + store i32 %tmp7, ptr %eh_selector, align 4 br label %Unwind bb12: ; preds = %ppad @@ -34,21 +34,21 @@ return: ; preds = %entry ret void lpad: ; preds = %bb - %eh_ptr = landingpad { i8*, i32 } + %eh_ptr = landingpad { ptr, i32 } cleanup - %exn = extractvalue { i8*, i32 } %eh_ptr, 0 - store i8* %exn, i8** %eh_exception - %eh_ptr13 = load i8*, i8** %eh_exception ; [#uses=1] - %eh_select14 = extractvalue { i8*, i32 } %eh_ptr, 1 - store i32 %eh_select14, i32* %eh_selector + %exn = extractvalue { ptr, i32 } %eh_ptr, 0 + store ptr %exn, ptr %eh_exception + %eh_ptr13 = load ptr, ptr %eh_exception ; [#uses=1] + %eh_select14 = extractvalue { ptr, i32 } %eh_ptr, 1 + store i32 %eh_select14, ptr %eh_selector br label %ppad ppad: br label %bb12 Unwind: - %eh_ptr15 = load i8*, i8** %eh_exception - call arm_apcscc void @_Unwind_SjLj_Resume(i8* %eh_ptr15) + %eh_ptr15 = load ptr, ptr %eh_exception + call arm_apcscc void @_Unwind_SjLj_Resume(ptr %eh_ptr15) unreachable } @@ -56,7 +56,7 @@ declare arm_apcscc void @func2() declare arm_apcscc void @_ZSt9terminatev() noreturn nounwind -declare arm_apcscc void @_Unwind_SjLj_Resume(i8*) +declare arm_apcscc void @_Unwind_SjLj_Resume(ptr) declare arm_apcscc void @func3() diff --git a/llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll index 662a78c4dfa650..fafe022c5f2987 100644 --- a/llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll +++ b/llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll @@ -3,28 +3,28 @@ ; CHECK: @ DW_OP_breg -%struct.SVal = type { i8*, i32 } +%struct.SVal = type { ptr, i32 } -define i32 @_Z3fooi4SVal(i32 %i, %struct.SVal* noalias %location) #0 !dbg !4 { +define i32 @_Z3fooi4SVal(i32 %i, ptr noalias %location) #0 !dbg !4 { entry: %"alloca point" = bitcast i32 0 to i32 br label %realentry realentry: call void @llvm.dbg.value(metadata i32 %i, metadata !21, metadata !DIExpression()), !dbg !22 - call void @llvm.dbg.value(metadata %struct.SVal* %location, metadata !23, metadata !DIExpression()), !dbg !22 + call void @llvm.dbg.value(metadata ptr %location, metadata !23, metadata !DIExpression()), !dbg !22 %tmp = icmp ne i32 %i, 0, !dbg !25 br i1 %tmp, label %bb, label %bb1, !dbg !25 bb: ; preds = %entry - %tmp1 = getelementptr inbounds %struct.SVal, %struct.SVal* %location, i32 0, i32 1, !dbg !27 - %tmp2 = load i32, i32* %tmp1, align 8, !dbg !27 + %tmp1 = getelementptr inbounds %struct.SVal, ptr %location, i32 0, i32 1, !dbg !27 + %tmp2 = load i32, ptr %tmp1, align 8, !dbg !27 %tmp3 = add i32 %tmp2, %i, !dbg !27 br label %bb2, !dbg !27 bb1: ; preds = %entry - %tmp4 = getelementptr inbounds %struct.SVal, %struct.SVal* %location, i32 0, i32 1, !dbg !28 - %tmp5 = load i32, i32* %tmp4, align 8, !dbg !28 + %tmp4 = getelementptr inbounds %struct.SVal, ptr %location, i32 0, i32 1, !dbg !28 + %tmp5 = load i32, ptr %tmp4, align 8, !dbg !28 %tmp6 = sub i32 %tmp5, 1, !dbg !28 br label %bb2, !dbg !28 diff --git a/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll b/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll index d2820918626ad0..9354ff39ec2c94 100644 --- a/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll +++ b/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -declare noalias i8* @malloc(i32) nounwind +declare noalias ptr @malloc(i32) nounwind -define internal void @gl_DrawPixels(i32 %width, i32 %height, i32 %format, i32 %type, i8* %pixels) nounwind { +define internal void @gl_DrawPixels(i32 %width, i32 %height, i32 %format, i32 %type, ptr %pixels) nounwind { entry: br i1 undef, label %bb3.i, label %bb3 @@ -49,7 +49,7 @@ bb4.i18: ; preds = %bb3.i17 %not..i = icmp ne i32 %1, 0 %2 = zext i1 %not..i to i32 %storemerge2.i = add i32 0, %2 - %3 = call noalias i8* @malloc(i32 %storemerge2.i) nounwind + %3 = call noalias ptr @malloc(i32 %storemerge2.i) nounwind br i1 undef, label %bb3.i9, label %bb9.i bb9.i: ; preds = %bb4.i18 diff --git a/llvm/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll b/llvm/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll index e7e0580179c47d..f5762cb1566afd 100644 --- a/llvm/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll +++ b/llvm/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll @@ -10,7 +10,7 @@ define i32 @test(i32 %x) { entry: - %0 = tail call signext i16 undef(i32* undef) + %0 = tail call signext i16 undef(ptr undef) switch i32 %x, label %bb3 [ i32 0, label %bb4 i32 1, label %bb1 diff --git a/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll b/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll index 09428ce9c33963..209bcec1843bb9 100644 --- a/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll +++ b/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll @@ -13,7 +13,7 @@ target triple = "armv7-eabi" %0 = type { i32, i32 } -define void @foo(i32* %in) nounwind { +define void @foo(ptr %in) nounwind { entry: br label %bb.i @@ -34,34 +34,34 @@ bb28.i: ; preds = %bb28.i, %bb27.i presymmetry.exit: ; preds = %bb28.i %tmp175387 = or i32 undef, 12 - %scevgep101.i = getelementptr i32, i32* %in, i32 undef + %scevgep101.i = getelementptr i32, ptr %in, i32 undef %tmp189401 = or i32 undef, 7 - %scevgep97.i = getelementptr i32, i32* %in, i32 undef + %scevgep97.i = getelementptr i32, ptr %in, i32 undef %tmp198410 = or i32 undef, 1 - %scevgep.i48 = getelementptr i32, i32* %in, i32 undef - %0 = load i32, i32* %scevgep.i48, align 4 + %scevgep.i48 = getelementptr i32, ptr %in, i32 undef + %0 = load i32, ptr %scevgep.i48, align 4 %1 = add nsw i32 %0, 0 - store i32 %1, i32* undef, align 4 + store i32 %1, ptr undef, align 4 %asmtmp.i.i33.i.i.i = tail call %0 asm "smull\09$0, $1, $2, $3", "=&r,=&r,%r,r,~{cc}"(i32 undef, i32 1518500250) nounwind %asmresult1.i.i34.i.i.i = extractvalue %0 %asmtmp.i.i33.i.i.i, 1 %2 = shl i32 %asmresult1.i.i34.i.i.i, 1 - %3 = load i32, i32* null, align 4 - %4 = load i32, i32* undef, align 4 + %3 = load i32, ptr null, align 4 + %4 = load i32, ptr undef, align 4 %5 = sub nsw i32 %3, %4 - %6 = load i32, i32* undef, align 4 - %7 = load i32, i32* null, align 4 + %6 = load i32, ptr undef, align 4 + %7 = load i32, ptr null, align 4 %8 = sub nsw i32 %6, %7 - %9 = load i32, i32* %scevgep97.i, align 4 - %10 = load i32, i32* undef, align 4 + %9 = load i32, ptr %scevgep97.i, align 4 + %10 = load i32, ptr undef, align 4 %11 = sub nsw i32 %9, %10 - %12 = load i32, i32* null, align 4 - %13 = load i32, i32* %scevgep101.i, align 4 + %12 = load i32, ptr null, align 4 + %13 = load i32, ptr %scevgep101.i, align 4 %14 = sub nsw i32 %12, %13 - %15 = load i32, i32* %scevgep.i48, align 4 - %16 = load i32, i32* null, align 4 + %15 = load i32, ptr %scevgep.i48, align 4 + %16 = load i32, ptr null, align 4 %17 = add nsw i32 %16, %15 %18 = sub nsw i32 %15, %16 - %19 = load i32, i32* undef, align 4 + %19 = load i32, ptr undef, align 4 %20 = add nsw i32 %19, %2 %21 = sub nsw i32 %19, %2 %22 = add nsw i32 %14, %5 @@ -69,16 +69,16 @@ presymmetry.exit: ; preds = %bb28.i %24 = add nsw i32 %11, %8 %25 = sub nsw i32 %8, %11 %26 = add nsw i32 %21, %23 - store i32 %26, i32* %scevgep.i48, align 4 + store i32 %26, ptr %scevgep.i48, align 4 %27 = sub nsw i32 %25, %18 - store i32 %27, i32* null, align 4 + store i32 %27, ptr null, align 4 %28 = sub nsw i32 %23, %21 - store i32 %28, i32* undef, align 4 + store i32 %28, ptr undef, align 4 %29 = add nsw i32 %18, %25 - store i32 %29, i32* undef, align 4 + store i32 %29, ptr undef, align 4 %30 = add nsw i32 %17, %22 - store i32 %30, i32* %scevgep101.i, align 4 + store i32 %30, ptr %scevgep101.i, align 4 %31 = add nsw i32 %20, %24 - store i32 %31, i32* null, align 4 + store i32 %31, ptr null, align 4 unreachable } diff --git a/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll b/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll index 4b89ea32536d59..ff1e769600d385 100644 --- a/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll +++ b/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s ; rdar://8690640 -define i32* @t(i32* %x) nounwind "frame-pointer"="all" { +define ptr @t(ptr %x) nounwind "frame-pointer"="all" { entry: ; CHECK-LABEL: t: ; CHECK: push @@ -12,10 +12,10 @@ entry: ; CHECK: bl _foo ; CHECK: pop {r7, pc} - %0 = tail call i32* @foo(i32* %x) nounwind - %1 = tail call i32* @foo(i32* %0) nounwind - %2 = tail call i32* @foo(i32* %1) nounwind - ret i32* %2 + %0 = tail call ptr @foo(ptr %x) nounwind + %1 = tail call ptr @foo(ptr %0) nounwind + %2 = tail call ptr @foo(ptr %1) nounwind + ret ptr %2 } -declare i32* @foo(i32*) +declare ptr @foo(ptr) diff --git a/llvm/test/CodeGen/ARM/2010-12-08-tpsoft.ll b/llvm/test/CodeGen/ARM/2010-12-08-tpsoft.ll index 2df9fb76b97476..652b53b7380635 100644 --- a/llvm/test/CodeGen/ARM/2010-12-08-tpsoft.ll +++ b/llvm/test/CodeGen/ARM/2010-12-08-tpsoft.ll @@ -12,14 +12,14 @@ define arm_aapcs_vfpcc i32 @main() nounwind { entry: - %0 = load i32, i32* @i, align 4 + %0 = load i32, ptr @i, align 4 switch i32 %0, label %bb2 [ i32 12, label %bb i32 13, label %bb1 ] bb: ; preds = %entry - %1 = tail call arm_aapcs_vfpcc i32 @foo(i8* @a) nounwind + %1 = tail call arm_aapcs_vfpcc i32 @foo(ptr @a) nounwind ret i32 %1 ; ELFASM: bl __aeabi_read_tp @@ -34,13 +34,13 @@ bb: ; preds = %entry bb1: ; preds = %entry - %2 = tail call arm_aapcs_vfpcc i32 @bar(i32* bitcast ([10 x i8]* @b to i32*)) nounwind + %2 = tail call arm_aapcs_vfpcc i32 @bar(ptr @b) nounwind ret i32 %2 bb2: ; preds = %entry ret i32 -1 } -declare arm_aapcs_vfpcc i32 @foo(i8*) +declare arm_aapcs_vfpcc i32 @foo(ptr) -declare arm_aapcs_vfpcc i32 @bar(i32*) +declare arm_aapcs_vfpcc i32 @bar(ptr) diff --git a/llvm/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll b/llvm/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll index ccebe2a003cdf2..34122e62cc0709 100644 --- a/llvm/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll +++ b/llvm/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll @@ -26,9 +26,9 @@ ; OBJ-NEXT: Section: .bss define i32 @main(i32 %argc) nounwind { - %1 = load i32, i32* @sum, align 4 - %2 = getelementptr [80 x i8], [80 x i8]* @array00, i32 0, i32 %argc - %3 = load i8, i8* %2 + %1 = load i32, ptr @sum, align 4 + %2 = getelementptr [80 x i8], ptr @array00, i32 0, i32 %argc + %3 = load i8, ptr %2 %4 = zext i8 %3 to i32 %5 = add i32 %1, %4 ret i32 %5 diff --git a/llvm/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll b/llvm/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll index 783c82eb88b7db..ca2a7aa54ca84d 100644 --- a/llvm/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll +++ b/llvm/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll @@ -9,7 +9,6 @@ entry: br label %bb bb: - %p.2 = getelementptr [8096 x i8], [8096 x i8]* %buf, i32 0, i32 0 - store i8 undef, i8* %p.2, align 1 + store i8 undef, ptr %buf, align 1 ret void } diff --git a/llvm/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/llvm/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll index c65c64dfc67913..57c5316796be17 100644 --- a/llvm/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll +++ b/llvm/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll @@ -22,9 +22,9 @@ target triple = "thumbv7-apple-darwin10" define zeroext i8 @get1(i8 zeroext %a) #0 !dbg !16 { entry: tail call void @llvm.dbg.value(metadata i8 %a, metadata !20, metadata !23), !dbg !24 - %0 = load i8, i8* @x1, align 4, !dbg !24 + %0 = load i8, ptr @x1, align 4, !dbg !24 tail call void @llvm.dbg.value(metadata i8 %0, metadata !21, metadata !23), !dbg !24 - store i8 %a, i8* @x1, align 4, !dbg !24 + store i8 %a, ptr @x1, align 4, !dbg !24 ret i8 %0, !dbg !25 } @@ -35,9 +35,9 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) #1 define zeroext i8 @get2(i8 zeroext %a) #0 !dbg !26 { entry: tail call void @llvm.dbg.value(metadata i8 %a, metadata !28, metadata !23), !dbg !31 - %0 = load i8, i8* @x2, align 4, !dbg !31 + %0 = load i8, ptr @x2, align 4, !dbg !31 tail call void @llvm.dbg.value(metadata i8 %0, metadata !29, metadata !23), !dbg !31 - store i8 %a, i8* @x2, align 4, !dbg !31 + store i8 %a, ptr @x2, align 4, !dbg !31 ret i8 %0, !dbg !32 } @@ -46,9 +46,9 @@ entry: define zeroext i8 @get3(i8 zeroext %a) #0 !dbg !33 { entry: tail call void @llvm.dbg.value(metadata i8 %a, metadata !35, metadata !23), !dbg !38 - %0 = load i8, i8* @x3, align 4, !dbg !38 + %0 = load i8, ptr @x3, align 4, !dbg !38 tail call void @llvm.dbg.value(metadata i8 %0, metadata !36, metadata !23), !dbg !38 - store i8 %a, i8* @x3, align 4, !dbg !38 + store i8 %a, ptr @x3, align 4, !dbg !38 ret i8 %0, !dbg !39 } @@ -57,9 +57,9 @@ entry: define zeroext i8 @get4(i8 zeroext %a) #0 !dbg !40 { entry: tail call void @llvm.dbg.value(metadata i8 %a, metadata !42, metadata !23), !dbg !45 - %0 = load i8, i8* @x4, align 4, !dbg !45 + %0 = load i8, ptr @x4, align 4, !dbg !45 tail call void @llvm.dbg.value(metadata i8 %0, metadata !43, metadata !23), !dbg !45 - store i8 %a, i8* @x4, align 4, !dbg !45 + store i8 %a, ptr @x4, align 4, !dbg !45 ret i8 %0, !dbg !46 } @@ -68,9 +68,9 @@ entry: define zeroext i8 @get5(i8 zeroext %a) #0 !dbg !47 { entry: tail call void @llvm.dbg.value(metadata i8 %a, metadata !49, metadata !23), !dbg !52 - %0 = load i8, i8* @x5, align 4, !dbg !52 + %0 = load i8, ptr @x5, align 4, !dbg !52 tail call void @llvm.dbg.value(metadata i8 %0, metadata !50, metadata !23), !dbg !52 - store i8 %a, i8* @x5, align 4, !dbg !52 + store i8 %a, ptr @x5, align 4, !dbg !52 ret i8 %0, !dbg !53 } diff --git a/llvm/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll b/llvm/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll index 730f3050d11590..793a60f36e229a 100644 --- a/llvm/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll +++ b/llvm/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll @@ -7,7 +7,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32" target triple = "armv6-apple-darwin10" -define void @ptoa(i1 %tst, i8* %p8, i8 %val8) nounwind { +define void @ptoa(i1 %tst, ptr %p8, i8 %val8) nounwind { entry: br i1 false, label %bb3, label %bb @@ -15,108 +15,107 @@ bb: ; preds = %entry br label %bb3 bb3: ; preds = %bb, %entry - %0 = call noalias i8* @malloc() nounwind + %0 = call noalias ptr @malloc() nounwind br i1 %tst, label %bb46, label %bb8 bb8: ; preds = %bb3 - %1 = getelementptr inbounds i8, i8* %0, i32 0 - store volatile i8 0, i8* %1, align 1 - %2 = call i32 @ptou() nounwind + store volatile i8 0, ptr %0, align 1 + %1 = call i32 @ptou() nounwind ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} - %3 = udiv i32 %2, 10 - %4 = urem i32 %3, 10 - %5 = icmp ult i32 %4, 10 - %6 = trunc i32 %4 to i8 - %7 = or i8 %6, 48 - %8 = add i8 %6, 87 - %iftmp.5.0.1 = select i1 %5, i8 %7, i8 %8 - store volatile i8 %iftmp.5.0.1, i8* %p8, align 1 + %2 = udiv i32 %1, 10 + %3 = urem i32 %2, 10 + %4 = icmp ult i32 %3, 10 + %5 = trunc i32 %3 to i8 + %6 = or i8 %5, 48 + %7 = add i8 %5, 87 + %iftmp.5.0.1 = select i1 %4, i8 %6, i8 %7 + store volatile i8 %iftmp.5.0.1, ptr %p8, align 1 ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} - %9 = udiv i32 %2, 100 - %10 = urem i32 %9, 10 - %11 = icmp ult i32 %10, 10 - %12 = trunc i32 %10 to i8 - %13 = or i8 %12, 48 - %14 = add i8 %12, 87 - %iftmp.5.0.2 = select i1 %11, i8 %13, i8 %14 - store volatile i8 %iftmp.5.0.2, i8* %p8, align 1 + %8 = udiv i32 %1, 100 + %9 = urem i32 %8, 10 + %10 = icmp ult i32 %9, 10 + %11 = trunc i32 %9 to i8 + %12 = or i8 %11, 48 + %13 = add i8 %11, 87 + %iftmp.5.0.2 = select i1 %10, i8 %12, i8 %13 + store volatile i8 %iftmp.5.0.2, ptr %p8, align 1 ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} - %15 = udiv i32 %2, 10000 - %16 = urem i32 %15, 10 - %17 = icmp ult i32 %16, 10 - %18 = trunc i32 %16 to i8 - %19 = or i8 %18, 48 - %20 = add i8 %18, 87 - %iftmp.5.0.4 = select i1 %17, i8 %19, i8 %20 - store volatile i8 %iftmp.5.0.4, i8* null, align 1 + %14 = udiv i32 %1, 10000 + %15 = urem i32 %14, 10 + %16 = icmp ult i32 %15, 10 + %17 = trunc i32 %15 to i8 + %18 = or i8 %17, 48 + %19 = add i8 %17, 87 + %iftmp.5.0.4 = select i1 %16, i8 %18, i8 %19 + store volatile i8 %iftmp.5.0.4, ptr null, align 1 ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} - %21 = udiv i32 %2, 100000 - %22 = urem i32 %21, 10 - %23 = icmp ult i32 %22, 10 - %iftmp.5.0.5 = select i1 %23, i8 0, i8 %val8 - store volatile i8 %iftmp.5.0.5, i8* %p8, align 1 + %20 = udiv i32 %1, 100000 + %21 = urem i32 %20, 10 + %22 = icmp ult i32 %21, 10 + %iftmp.5.0.5 = select i1 %22, i8 0, i8 %val8 + store volatile i8 %iftmp.5.0.5, ptr %p8, align 1 ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} - %24 = udiv i32 %2, 1000000 - %25 = urem i32 %24, 10 - %26 = icmp ult i32 %25, 10 - %27 = trunc i32 %25 to i8 - %28 = or i8 %27, 48 - %29 = add i8 %27, 87 - %iftmp.5.0.6 = select i1 %26, i8 %28, i8 %29 - store volatile i8 %iftmp.5.0.6, i8* %p8, align 1 + %23 = udiv i32 %1, 1000000 + %24 = urem i32 %23, 10 + %25 = icmp ult i32 %24, 10 + %26 = trunc i32 %24 to i8 + %27 = or i8 %26, 48 + %28 = add i8 %26, 87 + %iftmp.5.0.6 = select i1 %25, i8 %27, i8 %28 + store volatile i8 %iftmp.5.0.6, ptr %p8, align 1 ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} - %30 = udiv i32 %2, 10000000 - %31 = urem i32 %30, 10 - %32 = icmp ult i32 %31, 10 - %33 = trunc i32 %31 to i8 - %34 = or i8 %33, 48 - %35 = add i8 %33, 87 - %iftmp.5.0.7 = select i1 %32, i8 %34, i8 %35 - store volatile i8 %iftmp.5.0.7, i8* %p8, align 1 - %36 = udiv i32 %2, 100000000 - %37 = urem i32 %36, 10 - %38 = icmp ult i32 %37, 10 - %39 = trunc i32 %37 to i8 - %40 = or i8 %39, 48 - %41 = add i8 %39, 87 - %iftmp.5.0.8 = select i1 %38, i8 %40, i8 %41 - store volatile i8 %iftmp.5.0.8, i8* null, align 1 + %29 = udiv i32 %1, 10000000 + %30 = urem i32 %29, 10 + %31 = icmp ult i32 %30, 10 + %32 = trunc i32 %30 to i8 + %33 = or i8 %32, 48 + %34 = add i8 %32, 87 + %iftmp.5.0.7 = select i1 %31, i8 %33, i8 %34 + store volatile i8 %iftmp.5.0.7, ptr %p8, align 1 + %35 = udiv i32 %1, 100000000 + %36 = urem i32 %35, 10 + %37 = icmp ult i32 %36, 10 + %38 = trunc i32 %36 to i8 + %39 = or i8 %38, 48 + %40 = add i8 %38, 87 + %iftmp.5.0.8 = select i1 %37, i8 %39, i8 %40 + store volatile i8 %iftmp.5.0.8, ptr null, align 1 br label %bb46 bb46: ; preds = %bb3 ret void } -declare noalias i8* @malloc() nounwind +declare noalias ptr @malloc() nounwind declare i32 @ptou() diff --git a/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll b/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll index e96641bf6671f1..1515b06b620bd8 100644 --- a/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll +++ b/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll @@ -8,7 +8,7 @@ target triple = "armv5e-none-linux-gnueabi" define hidden fastcc void @storeAtts() nounwind { entry: - %.SV116 = alloca i8** + %.SV116 = alloca ptr br i1 undef, label %meshBB520, label %meshBB464 bb15: ; preds = %meshBB424 @@ -39,22 +39,22 @@ bb134: ; preds = %bb131 unreachable bb135: ; preds = %meshBB396 - %uriHash.1.phi.load = load i32, i32* undef - %.load120 = load i8**, i8*** %.SV116 - %.phi24 = load i8, i8* null - %.phi26 = load i8*, i8** null - store i8 %.phi24, i8* %.phi26, align 1 - %0 = getelementptr inbounds i8, i8* %.phi26, i32 1 - store i8* %0, i8** %.load120, align 4 + %uriHash.1.phi.load = load i32, ptr undef + %.load120 = load ptr, ptr %.SV116 + %.phi24 = load i8, ptr null + %.phi26 = load ptr, ptr null + store i8 %.phi24, ptr %.phi26, align 1 + %0 = getelementptr inbounds i8, ptr %.phi26, i32 1 + store ptr %0, ptr %.load120, align 4 ; CHECK: mul [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{(lr|r[0-9]+)$}} %1 = mul i32 %uriHash.1.phi.load, 1000003 %2 = xor i32 0, %1 - store i32 %2, i32* null - %3 = load i8, i8* null, align 1 + store i32 %2, ptr null + %3 = load i8, ptr null, align 1 %4 = icmp eq i8 %3, 0 - store i8* %0, i8** undef + store ptr %0, ptr undef br i1 %4, label %meshBB472, label %bb131 bb212: ; preds = %meshBB540 diff --git a/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll b/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll index b33b333b299d09..2ff19c7975f124 100644 --- a/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll +++ b/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll @@ -2,12 +2,12 @@ ; rdar://9117613 -%struct.mo = type { i32, %struct.mo_pops* } -%struct.mo_pops = type { void (%struct.mo*)*, void (%struct.mo*)*, i32 (%struct.mo*, i32*, i32)*, i32 (%struct.mo*)*, i32 (%struct.mo*, i64, i32, i32, i32*, i64, i32)*, i32 (%struct.mo*, i64, i32, i64*, i32*, i32, i32, i32)*, i32 (%struct.mo*, i64, i32)*, i32 (%struct.mo*, i64, i64, i32)*, i32 (%struct.mo*, i64, i64, i32)*, i32 (%struct.mo*, i32)*, i32 (%struct.mo*)*, i32 (%struct.mo*, i32)*, i8* } -%struct.ui = type { %struct.mo*, i32*, i32, i32*, i32*, i64, i32*, i32*, i32* } +%struct.mo = type { i32, ptr } +%struct.mo_pops = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr } +%struct.ui = type { ptr, ptr, i32, ptr, ptr, i64, ptr, ptr, ptr } -define internal fastcc i32 @t(i32* %vp, i32 %withfsize, i64 %filesize) nounwind { +define internal fastcc i32 @t(ptr %vp, i32 %withfsize, i64 %filesize) nounwind { entry: br i1 undef, label %bb1, label %bb @@ -15,13 +15,12 @@ bb: ; preds = %entry unreachable bb1: ; preds = %entry - %0 = call %struct.ui* @vn_pp_to_ui(i32* undef) nounwind - call void @llvm.memset.p0i8.i32(i8* align 4 undef, i8 0, i32 40, i1 false) - %1 = getelementptr inbounds %struct.ui, %struct.ui* %0, i32 0, i32 0 - store %struct.mo* undef, %struct.mo** %1, align 4 - %2 = getelementptr inbounds %struct.ui, %struct.ui* %0, i32 0, i32 5 - %3 = load i64, i64* %2, align 4 - %4 = call i32 @mo_create_nnm(%struct.mo* undef, i64 %3, i32** undef) nounwind + %0 = call ptr @vn_pp_to_ui(ptr undef) nounwind + call void @llvm.memset.p0.i32(ptr align 4 undef, i8 0, i32 40, i1 false) + store ptr undef, ptr %0, align 4 + %1 = getelementptr inbounds %struct.ui, ptr %0, i32 0, i32 5 + %2 = load i64, ptr %1, align 4 + %3 = call i32 @mo_create_nnm(ptr undef, i64 %2, ptr undef) nounwind br i1 undef, label %bb3, label %bb2 bb2: ; preds = %bb1 @@ -31,17 +30,17 @@ bb3: ; preds = %bb1 br i1 undef, label %bb4, label %bb6 bb4: ; preds = %bb3 - %5 = call i32 @vn_size(i32* %vp, i64* %2, i32* undef) nounwind + %4 = call i32 @vn_size(ptr %vp, ptr %1, ptr undef) nounwind unreachable bb6: ; preds = %bb3 ret i32 0 } -declare %struct.ui* @vn_pp_to_ui(i32*) +declare ptr @vn_pp_to_ui(ptr) -declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) nounwind +declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) nounwind -declare i32 @mo_create_nnm(%struct.mo*, i64, i32**) +declare i32 @mo_create_nnm(ptr, i64, ptr) -declare i32 @vn_size(i32*, i64*, i32*) +declare i32 @vn_size(ptr, ptr, ptr) diff --git a/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll b/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll index b526b8c3075d53..44ae16339499a5 100644 --- a/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll +++ b/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll @@ -18,11 +18,11 @@ for.body.lr.ph: for.body: ; preds = %_Z14printIsNotZeroi.exit17.for.body_crit_edge, %for.body.lr.ph %tmp3 = phi i1 [ false, %for.body.lr.ph ], [ %phitmp27, %_Z14printIsNotZeroi.exit17.for.body_crit_edge ] %i.022 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %_Z14printIsNotZeroi.exit17.for.body_crit_edge ] - %x = getelementptr %struct.Outer, %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 0 - %y = getelementptr %struct.Outer, %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 1 + %x = getelementptr %struct.Outer, ptr @oStruct, i32 0, i32 1, i32 %i.022, i32 0 + %y = getelementptr %struct.Outer, ptr @oStruct, i32 0, i32 1, i32 %i.022, i32 1 %inc = add i32 %i.022, 1 - %tmp8 = load i32, i32* %x, align 4 - %tmp11 = load i32, i32* %y, align 4 + %tmp8 = load i32, ptr %x, align 4 + %tmp11 = load i32, ptr %y, align 4 %mul = mul nsw i32 %tmp11, %tmp8 %tobool.i14 = icmp eq i32 %mul, 0 br i1 %tobool.i14, label %_Z14printIsNotZeroi.exit17, label %if.then.i16 @@ -34,8 +34,8 @@ _Z14printIsNotZeroi.exit17: ; preds = %_Z14printIsNotZeroi br label %_Z14printIsNotZeroi.exit17.for.body_crit_edge _Z14printIsNotZeroi.exit17.for.body_crit_edge: ; preds = %_Z14printIsNotZeroi.exit17 - %b.phi.trans.insert = getelementptr %struct.Outer, %struct.Outer* @oStruct, i32 0, i32 1, i32 %inc, i32 3 - %tmp3.pre = load i8, i8* %b.phi.trans.insert, align 1 + %b.phi.trans.insert = getelementptr %struct.Outer, ptr @oStruct, i32 0, i32 1, i32 %inc, i32 3 + %tmp3.pre = load i8, ptr %b.phi.trans.insert, align 1 %phitmp27 = icmp eq i8 %val8, 0 br label %for.body diff --git a/llvm/test/CodeGen/ARM/2011-04-07-schediv.ll b/llvm/test/CodeGen/ARM/2011-04-07-schediv.ll index 7f603157c5d3f6..2dde043207f5c0 100644 --- a/llvm/test/CodeGen/ARM/2011-04-07-schediv.ll +++ b/llvm/test/CodeGen/ARM/2011-04-07-schediv.ll @@ -4,9 +4,8 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" target triple = "thumbv7-apple-darwin10" -define void @t(i32 %src_width, float* nocapture %src_copy_start, float* nocapture %dst_copy_start, i32 %src_copy_start_index) nounwind optsize { +define void @t(i32 %src_width, ptr nocapture %src_copy_start, ptr nocapture %dst_copy_start, i32 %src_copy_start_index) nounwind optsize { entry: - %src_copy_start6 = bitcast float* %src_copy_start to i8* %0 = icmp eq i32 %src_width, 0 br i1 %0, label %return, label %bb @@ -18,11 +17,10 @@ entry: bb: ; preds = %entry, %bb %j.05 = phi i32 [ %2, %bb ], [ 0, %entry ] %tmp = mul i32 %j.05, %src_copy_start_index - %uglygep = getelementptr i8, i8* %src_copy_start6, i32 %tmp - %src_copy_start_addr.04 = bitcast i8* %uglygep to float* - %dst_copy_start_addr.03 = getelementptr float, float* %dst_copy_start, i32 %j.05 - %1 = load float, float* %src_copy_start_addr.04, align 4 - store float %1, float* %dst_copy_start_addr.03, align 4 + %uglygep = getelementptr i8, ptr %src_copy_start, i32 %tmp + %dst_copy_start_addr.03 = getelementptr float, ptr %dst_copy_start, i32 %j.05 + %1 = load float, ptr %uglygep, align 4 + store float %1, ptr %dst_copy_start_addr.03, align 4 %2 = add i32 %j.05, 1 %exitcond = icmp eq i32 %2, %src_width br i1 %exitcond, label %return, label %bb diff --git a/llvm/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll b/llvm/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll index 54fc9b049b8e9b..ad743fde20a12f 100644 --- a/llvm/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll +++ b/llvm/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll @@ -3,7 +3,7 @@ ; Overly aggressive LICM simply adds copies of constants ; rdar://9266679 -define zeroext i1 @t(i32* nocapture %A, i32 %size, i32 %value) nounwind readonly ssp { +define zeroext i1 @t(ptr nocapture %A, i32 %size, i32 %value) nounwind readonly ssp { ; CHECK-LABEL: t: entry: br label %for.cond @@ -18,8 +18,8 @@ for.body: ; CHECK: mov{{.*}} r{{[0-9]+}}, #{{[01]}} ; CHECK: mov{{.*}} r{{[0-9]+}}, #{{[01]}} ; CHECK-NOT: mov r{{[0-9]+}}, #{{[01]}} - %arrayidx = getelementptr i32, i32* %A, i32 %0 - %tmp4 = load i32, i32* %arrayidx, align 4 + %arrayidx = getelementptr i32, ptr %A, i32 %0 + %tmp4 = load i32, ptr %arrayidx, align 4 %cmp6 = icmp eq i32 %tmp4, %value br i1 %cmp6, label %return, label %for.inc diff --git a/llvm/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll b/llvm/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll index 8ad654fc8f9d00..0fbe7da66fe7f1 100644 --- a/llvm/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll +++ b/llvm/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll @@ -7,7 +7,7 @@ target triple = "thumbv7-apple-darwin10.0.0" define void @_Z8TestCasev() nounwind ssp { entry: %a = alloca float, align 4 - %tmp = load float, float* %a, align 4 + %tmp = load float, ptr %a, align 4 call void asm sideeffect "", "w,~{s0},~{s16}"(float %tmp) nounwind, !srcloc !0 ret void } diff --git a/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll b/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll index 3c5579acf6aec2..f5134d8d1b5ce0 100644 --- a/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll +++ b/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll @@ -4,10 +4,10 @@ ; more callee-saved registers and introduce copies. ; rdar://9329627 -%struct.FF = type { i32 (i32*)*, i32 (i32*, i32*, i32, i32, i32, i32)*, i32 (i32, i32, i8*)*, void ()*, i32 (i32, i8*, i32*)*, i32 ()* } -%struct.BD = type { %struct.BD*, i32, i32, i32, i32, i64, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i64, i32)*, [16 x i8], i64, i64 } +%struct.FF = type { ptr, ptr, ptr, ptr, ptr, ptr } +%struct.BD = type { ptr, i32, i32, i32, i32, i64, ptr, ptr, ptr, ptr, ptr, [16 x i8], i64, i64 } -@FuncPtr = external hidden unnamed_addr global %struct.FF* +@FuncPtr = external hidden unnamed_addr global ptr @.str1 = external hidden unnamed_addr constant [6 x i8], align 4 @G = external unnamed_addr global i32 @.str2 = external hidden unnamed_addr constant [58 x i8], align 4 @@ -21,8 +21,8 @@ entry: %block_size = alloca i32, align 4 %block_count = alloca i32, align 4 %index_cache = alloca i32, align 4 - store i32 0, i32* %index_cache, align 4 - %tmp = load i32, i32* @G, align 4 + store i32 0, ptr %index_cache, align 4 + %tmp = load i32, ptr @G, align 4 %tmp1 = call i32 @bar(i32 0, i32 0, i32 %tmp) nounwind switch i32 %tmp1, label %bb8 [ i32 0, label %bb @@ -31,7 +31,7 @@ entry: ] bb: - %tmp2 = load i32, i32* @G, align 4 + %tmp2 = load i32, ptr @G, align 4 %tmp4 = icmp eq i32 %tmp2, 0 br i1 %tmp4, label %bb1, label %bb8 @@ -41,14 +41,14 @@ bb1: ; CHECK: bl _Get ; CHECK: umull ; CHECK: bl _foo - %tmp5 = load i32, i32* %block_size, align 4 - %tmp6 = load i32, i32* %block_count, align 4 - %tmp7 = call %struct.FF* @Get() nounwind - store %struct.FF* %tmp7, %struct.FF** @FuncPtr, align 4 + %tmp5 = load i32, ptr %block_size, align 4 + %tmp6 = load i32, ptr %block_count, align 4 + %tmp7 = call ptr @Get() nounwind + store ptr %tmp7, ptr @FuncPtr, align 4 %tmp10 = zext i32 %tmp6 to i64 %tmp11 = zext i32 %tmp5 to i64 %tmp12 = mul nsw i64 %tmp10, %tmp11 - %tmp13 = call i32 @foo(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), i64 %tmp12, i32 %tmp5) nounwind + %tmp13 = call i32 @foo(ptr @.str1, i64 %tmp12, i32 %tmp5) nounwind br label %bb8 bb4: @@ -61,10 +61,10 @@ bb8: ret i32 -1 } -declare i32 @printf(i8*, ...) +declare i32 @printf(ptr, ...) -declare %struct.FF* @Get() +declare ptr @Get() -declare i32 @foo(i8*, i64, i32) +declare i32 @foo(ptr, i64, i32) declare i32 @bar(i32, i32, i32) diff --git a/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll b/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll index 0741049cffdd35..5996db7db79a42 100644 --- a/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll +++ b/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll @@ -41,11 +41,11 @@ if.then115: br i1 undef, label %if.else163, label %if.else145 if.else145: - %call150 = call fastcc %struct.hc* @foo(%struct.hc* undef, i32 34865152) optsize + %call150 = call fastcc ptr @foo(ptr undef, i32 34865152) optsize br label %while.body172 if.else163: - %call168 = call fastcc %struct.hc* @foo(%struct.hc* undef, i32 34078720) optsize + %call168 = call fastcc ptr @foo(ptr undef, i32 34078720) optsize br label %while.body172 while.body172: @@ -55,5 +55,5 @@ if.else173: ret i32 -1 } -declare hidden fastcc %struct.hc* @foo(%struct.hc* nocapture, i32) nounwind optsize +declare hidden fastcc ptr @foo(ptr nocapture, i32) nounwind optsize diff --git a/llvm/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll b/llvm/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll index 26b2a6efeebecf..397fc27aec4c0b 100644 --- a/llvm/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll +++ b/llvm/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" target triple = "thumbv7-apple-darwin" -define void @func() unnamed_addr align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) { +define void @func() unnamed_addr align 2 personality ptr @__gxx_personality_sj0 { entry: br label %for.cond @@ -36,14 +36,14 @@ for.cond.backedge: br label %for.cond lpad: - %exn = landingpad { i8*, i32 } - catch i8* null + %exn = landingpad { ptr, i32 } + catch ptr null invoke void @foo() to label %eh.resume unwind label %terminate.lpad lpad26: - %exn27 = landingpad { i8*, i32 } - catch i8* null + %exn27 = landingpad { ptr, i32 } + catch ptr null invoke void @foo() to label %eh.resume unwind label %terminate.lpad @@ -58,18 +58,18 @@ call8.i.i.i.noexc: ret void lpad44: - %exn45 = landingpad { i8*, i32 } - catch i8* null + %exn45 = landingpad { ptr, i32 } + catch ptr null invoke void @foo() to label %eh.resume unwind label %terminate.lpad eh.resume: - %exn.slot.0 = phi { i8*, i32 } [ %exn27, %lpad26 ], [ %exn, %lpad ], [ %exn45, %lpad44 ] - resume { i8*, i32 } %exn.slot.0 + %exn.slot.0 = phi { ptr, i32 } [ %exn27, %lpad26 ], [ %exn, %lpad ], [ %exn45, %lpad44 ] + resume { ptr, i32 } %exn.slot.0 terminate.lpad: - %exn51 = landingpad { i8*, i32 } - catch i8* null + %exn51 = landingpad { ptr, i32 } + catch ptr null tail call void @_ZSt9terminatev() noreturn nounwind unreachable } @@ -78,7 +78,7 @@ declare void @foo() declare i32 @__gxx_personality_sj0(...) -declare void @_Unwind_SjLj_Resume_or_Rethrow(i8*) +declare void @_Unwind_SjLj_Resume_or_Rethrow(ptr) declare void @_ZSt9terminatev() diff --git a/llvm/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll b/llvm/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll index b2557b7165db87..40f626f51db89d 100644 --- a/llvm/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll +++ b/llvm/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll @@ -4,26 +4,26 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- target triple = "thumbv7-apple-darwin10" %struct._RuneCharClass = type { [14 x i8], i32 } -%struct._RuneEntry = type { i32, i32, i32, i32* } -%struct._RuneLocale = type { [8 x i8], [32 x i8], i32 (i8*, i32, i8**)*, i32 (i32, i8*, i32, i8**)*, i32, [256 x i32], [256 x i32], [256 x i32], %struct._RuneRange, %struct._RuneRange, %struct._RuneRange, i8*, i32, i32, %struct._RuneCharClass* } -%struct._RuneRange = type { i32, %struct._RuneEntry* } +%struct._RuneEntry = type { i32, i32, i32, ptr } +%struct._RuneLocale = type { [8 x i8], [32 x i8], ptr, ptr, i32, [256 x i32], [256 x i32], [256 x i32], %struct._RuneRange, %struct._RuneRange, %struct._RuneRange, ptr, i32, i32, ptr } +%struct._RuneRange = type { i32, ptr } %struct.__collate_st_chain_pri = type { [10 x i32], [2 x i32] } %struct.__collate_st_char_pri = type { [2 x i32] } %struct.__collate_st_info = type { [2 x i8], i8, i8, [2 x i32], [2 x i32], i32, i32 } %struct.__collate_st_large_char_pri = type { i32, %struct.__collate_st_char_pri } %struct.__collate_st_subst = type { i32, [10 x i32] } -%struct.__xlocale_st_collate = type { i32, void (i8*)*, [32 x i8], %struct.__collate_st_info, [2 x %struct.__collate_st_subst*], %struct.__collate_st_chain_pri*, %struct.__collate_st_large_char_pri*, [256 x %struct.__collate_st_char_pri] } -%struct.__xlocale_st_messages = type { i32, void (i8*)*, i8*, %struct.lc_messages_T } -%struct.__xlocale_st_monetary = type { i32, void (i8*)*, i8*, %struct.lc_monetary_T } -%struct.__xlocale_st_numeric = type { i32, void (i8*)*, i8*, %struct.lc_numeric_T } -%struct.__xlocale_st_runelocale = type { i32, void (i8*)*, [32 x i8], i32, i32, i32 (i32*, i8*, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32 (%union.__mbstate_t*, %struct._xlocale*)*, i32 (i32*, i8**, i32, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32 (i8*, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32 (i8*, i32**, i32, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32, %struct._RuneLocale } -%struct.__xlocale_st_time = type { i32, void (i8*)*, i8*, %struct.lc_time_T } -%struct._xlocale = type { i32, void (i8*)*, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, i32, i64, i8, i8, i8, i8, i8, i8, i8, i8, i8, %struct.__xlocale_st_collate*, %struct.__xlocale_st_runelocale*, %struct.__xlocale_st_messages*, %struct.__xlocale_st_monetary*, %struct.__xlocale_st_numeric*, %struct._xlocale*, %struct.__xlocale_st_time*, %struct.lconv } -%struct.lc_messages_T = type { i8*, i8*, i8*, i8* } -%struct.lc_monetary_T = type { i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8* } -%struct.lc_numeric_T = type { i8*, i8*, i8* } -%struct.lc_time_T = type { [12 x i8*], [12 x i8*], [7 x i8*], [7 x i8*], i8*, i8*, i8*, i8*, i8*, i8*, [12 x i8*], i8*, i8* } -%struct.lconv = type { i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } +%struct.__xlocale_st_collate = type { i32, ptr, [32 x i8], %struct.__collate_st_info, [2 x ptr], ptr, ptr, [256 x %struct.__collate_st_char_pri] } +%struct.__xlocale_st_messages = type { i32, ptr, ptr, %struct.lc_messages_T } +%struct.__xlocale_st_monetary = type { i32, ptr, ptr, %struct.lc_monetary_T } +%struct.__xlocale_st_numeric = type { i32, ptr, ptr, %struct.lc_numeric_T } +%struct.__xlocale_st_runelocale = type { i32, ptr, [32 x i8], i32, i32, ptr, ptr, ptr, ptr, ptr, i32, %struct._RuneLocale } +%struct.__xlocale_st_time = type { i32, ptr, ptr, %struct.lc_time_T } +%struct._xlocale = type { i32, ptr, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, i32, i64, i8, i8, i8, i8, i8, i8, i8, i8, i8, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %struct.lconv } +%struct.lc_messages_T = type { ptr, ptr, ptr, ptr } +%struct.lc_monetary_T = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr } +%struct.lc_numeric_T = type { ptr, ptr, ptr } +%struct.lc_time_T = type { [12 x ptr], [12 x ptr], [7 x ptr], [7 x ptr], ptr, ptr, ptr, ptr, ptr, ptr, [12 x ptr], ptr, ptr } +%struct.lconv = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } %union.__mbstate_t = type { i64, [120 x i8] } @"\01_fnmatch.initial" = external constant %union.__mbstate_t, align 4 @@ -31,10 +31,10 @@ target triple = "thumbv7-apple-darwin10" ; CHECK: _fnmatch ; CHECK: bl _fnmatch1 -define i32 @"\01_fnmatch"(i8* %pattern, i8* %string, i32 %flags) nounwind optsize { +define i32 @"\01_fnmatch"(ptr %pattern, ptr %string, i32 %flags) nounwind optsize { entry: - %call4 = tail call i32 @fnmatch1(i8* %pattern, i8* %string, i8* %string, i32 %flags, %union.__mbstate_t* byval(%union.__mbstate_t) @"\01_fnmatch.initial", %union.__mbstate_t* byval(%union.__mbstate_t) @"\01_fnmatch.initial", %struct._xlocale* undef, i32 64) optsize + %call4 = tail call i32 @fnmatch1(ptr %pattern, ptr %string, ptr %string, i32 %flags, ptr byval(%union.__mbstate_t) @"\01_fnmatch.initial", ptr byval(%union.__mbstate_t) @"\01_fnmatch.initial", ptr undef, i32 64) optsize ret i32 %call4 } -declare i32 @fnmatch1(i8*, i8*, i8*, i32, %union.__mbstate_t* byval(%union.__mbstate_t), %union.__mbstate_t* byval(%union.__mbstate_t), %struct._xlocale*, i32) nounwind optsize +declare i32 @fnmatch1(ptr, ptr, ptr, i32, ptr byval(%union.__mbstate_t), ptr byval(%union.__mbstate_t), ptr, i32) nounwind optsize diff --git a/llvm/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll b/llvm/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll index aa83b7e2fa8202..089df7c2c02292 100644 --- a/llvm/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll +++ b/llvm/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll @@ -16,10 +16,10 @@ target triple = "thumbv7-apple-ios5.0" ; CHECK: add sp, #12 ; CHECK: b.w _puts -define void @f(i8* %s, %struct.A* nocapture byval(%struct.A) %a) nounwind optsize { +define void @f(ptr %s, ptr nocapture byval(%struct.A) %a) nounwind optsize { entry: - %puts = tail call i32 @puts(i8* %s) + %puts = tail call i32 @puts(ptr %s) ret void } -declare i32 @puts(i8* nocapture) nounwind +declare i32 @puts(ptr nocapture) nounwind diff --git a/llvm/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll b/llvm/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll index aac8f7b3a026b9..bf9e6f47ed947e 100644 --- a/llvm/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll +++ b/llvm/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll @@ -3,7 +3,7 @@ @prev = external global [0 x i16] @max_lazy_match = internal unnamed_addr global i32 0, align 4 -@read_buf = external global i32 (i8*, i32)* +@read_buf = external global ptr @window = external global [0 x i8] @lookahead = internal unnamed_addr global i32 0, align 4 @eofile.b = internal unnamed_addr global i32 0 diff --git a/llvm/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/llvm/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll index f7cdc83d0d9491..ceec112ffe823f 100644 --- a/llvm/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll +++ b/llvm/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll @@ -21,9 +21,9 @@ target triple = "thumbv7-apple-macosx10.7.0" ; Function Attrs: nounwind optsize ssp define i32 @get1(i32 %a) #0 !dbg !10 { tail call void @llvm.dbg.value(metadata i32 %a, metadata !14, metadata !17), !dbg !18 - %1 = load i32, i32* @x1, align 4, !dbg !19 + %1 = load i32, ptr @x1, align 4, !dbg !19 tail call void @llvm.dbg.value(metadata i32 %1, metadata !15, metadata !17), !dbg !19 - store i32 %a, i32* @x1, align 4, !dbg !19 + store i32 %a, ptr @x1, align 4, !dbg !19 ret i32 %1, !dbg !19 } @@ -31,9 +31,9 @@ define i32 @get1(i32 %a) #0 !dbg !10 { define i32 @get2(i32 %a) #0 !dbg !20 { tail call void @llvm.dbg.value(metadata i32 %a, metadata !22, metadata !17), !dbg !25 - %1 = load i32, i32* @x2, align 4, !dbg !26 + %1 = load i32, ptr @x2, align 4, !dbg !26 tail call void @llvm.dbg.value(metadata i32 %1, metadata !23, metadata !17), !dbg !26 - store i32 %a, i32* @x2, align 4, !dbg !26 + store i32 %a, ptr @x2, align 4, !dbg !26 ret i32 %1, !dbg !26 } @@ -41,9 +41,9 @@ define i32 @get2(i32 %a) #0 !dbg !20 { define i32 @get3(i32 %a) #0 !dbg !27 { tail call void @llvm.dbg.value(metadata i32 %a, metadata !29, metadata !17), !dbg !32 - %1 = load i32, i32* @x3, align 4, !dbg !33 + %1 = load i32, ptr @x3, align 4, !dbg !33 tail call void @llvm.dbg.value(metadata i32 %1, metadata !30, metadata !17), !dbg !33 - store i32 %a, i32* @x3, align 4, !dbg !33 + store i32 %a, ptr @x3, align 4, !dbg !33 ret i32 %1, !dbg !33 } @@ -51,9 +51,9 @@ define i32 @get3(i32 %a) #0 !dbg !27 { define i32 @get4(i32 %a) #0 !dbg !34 { tail call void @llvm.dbg.value(metadata i32 %a, metadata !36, metadata !17), !dbg !39 - %1 = load i32, i32* @x4, align 4, !dbg !40 + %1 = load i32, ptr @x4, align 4, !dbg !40 tail call void @llvm.dbg.value(metadata i32 %1, metadata !37, metadata !17), !dbg !40 - store i32 %a, i32* @x4, align 4, !dbg !40 + store i32 %a, ptr @x4, align 4, !dbg !40 ret i32 %1, !dbg !40 } @@ -61,9 +61,9 @@ define i32 @get4(i32 %a) #0 !dbg !34 { define i32 @get5(i32 %a) #0 !dbg !41 { tail call void @llvm.dbg.value(metadata i32 %a, metadata !43, metadata !17), !dbg !46 - %1 = load i32, i32* @x5, align 4, !dbg !47 + %1 = load i32, ptr @x5, align 4, !dbg !47 tail call void @llvm.dbg.value(metadata i32 %1, metadata !44, metadata !17), !dbg !47 - store i32 %a, i32* @x5, align 4, !dbg !47 + store i32 %a, ptr @x5, align 4, !dbg !47 ret i32 %1, !dbg !47 } diff --git a/llvm/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll b/llvm/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll index d702af7c0c708e..cebf96e56eedbe 100644 --- a/llvm/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll +++ b/llvm/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll @@ -4,9 +4,9 @@ define void @test_vmovqqqq_pseudo() nounwind ssp { entry: - %vld3_lane = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16.p0i8(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> zeroinitializer, i32 7, i32 2) - store { <8 x i16>, <8 x i16>, <8 x i16> } %vld3_lane, { <8 x i16>, <8 x i16>, <8 x i16> }* undef + %vld3_lane = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16.p0(ptr undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> zeroinitializer, i32 7, i32 2) + store { <8 x i16>, <8 x i16>, <8 x i16> } %vld3_lane, ptr undef ret void } -declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16.p0i8(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly +declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16.p0(ptr, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly diff --git a/llvm/test/CodeGen/ARM/2011-08-29-SchedCycle.ll b/llvm/test/CodeGen/ARM/2011-08-29-SchedCycle.ll index fb8454479508ed..52324436baad2c 100644 --- a/llvm/test/CodeGen/ARM/2011-08-29-SchedCycle.ll +++ b/llvm/test/CodeGen/ARM/2011-08-29-SchedCycle.ll @@ -32,14 +32,14 @@ define void @t() nounwind { entry: - %tmp = load i64, i64* undef, align 4 + %tmp = load i64, ptr undef, align 4 %tmp5 = udiv i64 %tmp, 30 %tmp13 = and i64 %tmp5, 64739244643450880 %tmp16 = sub i64 0, %tmp13 %tmp19 = and i64 %tmp16, 63 %tmp20 = urem i64 %tmp19, 3 %tmp22 = and i64 %tmp16, -272346829004752 - store i64 %tmp22, i64* undef, align 4 - store i64 %tmp20, i64* undef, align 4 + store i64 %tmp22, ptr undef, align 4 + store i64 %tmp20, ptr undef, align 4 ret void } diff --git a/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll b/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll index d9b38b5e5735cd..c31e8462f49de8 100644 --- a/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll +++ b/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll @@ -17,14 +17,14 @@ bb25.lr.ph: ; preds = %entry bb.i: ; preds = %bb5.i %1 = shl nsw i32 %k_addr.0.i, 1 %.sum8.i = add i32 %1, -1 - %2 = getelementptr inbounds [256 x i32], [256 x i32]* %heap, i32 0, i32 %.sum8.i - %3 = load i32, i32* %2, align 4 + %2 = getelementptr inbounds [256 x i32], ptr %heap, i32 0, i32 %.sum8.i + %3 = load i32, ptr %2, align 4 br i1 false, label %bb5.i, label %bb4.i bb4.i: ; preds = %bb.i %.sum10.i = add i32 %k_addr.0.i, -1 - %4 = getelementptr inbounds [256 x i32], [256 x i32]* %heap, i32 0, i32 %.sum10.i - store i32 %3, i32* %4, align 4 + %4 = getelementptr inbounds [256 x i32], ptr %heap, i32 0, i32 %.sum10.i + store i32 %3, ptr %4, align 4 br label %bb5.i bb5.i: ; preds = %bb5.i, %bb4.i, %bb.i, %bb25.lr.ph diff --git a/llvm/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll b/llvm/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll index 2561af707d755d..c22ab937a0792e 100644 --- a/llvm/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll +++ b/llvm/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll @@ -11,13 +11,13 @@ target triple = "armv7-none-linux-gnueabi" @z2 = common global <4 x i16> zeroinitializer define void @f() { - %1 = load <3 x i16>, <3 x i16>* @x1 - %2 = load <3 x i16>, <3 x i16>* @y1 + %1 = load <3 x i16>, ptr @x1 + %2 = load <3 x i16>, ptr @y1 %3 = sdiv <3 x i16> %1, %2 - store <3 x i16> %3, <3 x i16>* @z1 - %4 = load <4 x i16>, <4 x i16>* @x2 - %5 = load <4 x i16>, <4 x i16>* @y2 + store <3 x i16> %3, ptr @z1 + %4 = load <4 x i16>, ptr @x2 + %5 = load <4 x i16>, ptr @y2 %6 = sdiv <4 x i16> %4, %5 - store <4 x i16> %6, <4 x i16>* @z2 + store <4 x i16> %6, ptr @z2 ret void } diff --git a/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll b/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll index a0205fcdd348de..4309d9408aaa74 100644 --- a/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll +++ b/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll @@ -8,9 +8,9 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" target triple = "thumbv7-apple-ios4.0.0" -declare i8* @__memset_chk(i8*, i32, i32, i32) nounwind +declare ptr @__memset_chk(ptr, i32, i32, i32) nounwind -define hidden fastcc i32 @sqlite3VdbeExec(i32* %p) nounwind { +define hidden fastcc i32 @sqlite3VdbeExec(ptr %p) nounwind { entry: br label %sqlite3VarintLen.exit7424 @@ -40,7 +40,7 @@ for.body2377: ; preds = %for.body2355 %conv2385 = trunc i64 %sub2384 to i32 %len.0.i = select i1 undef, i32 %conv2385, i32 undef %sub.i7384 = sub nsw i32 %len.0.i, 0 - %call.i.i7385 = call i8* @__memset_chk(i8* undef, i32 0, i32 %sub.i7384, i32 undef) nounwind + %call.i.i7385 = call ptr @__memset_chk(ptr undef, i32 0, i32 %sub.i7384, i32 undef) nounwind unreachable too_big: ; preds = %sqlite3VarintLen.exit diff --git a/llvm/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll b/llvm/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll index 53e3bed5383139..f2edd262a6323d 100644 --- a/llvm/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll +++ b/llvm/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll @@ -4,7 +4,7 @@ ; ARM target specific dag combine created a cycle in DAG. define void @t() nounwind ssp { - %1 = load i64, i64* undef, align 4 + %1 = load i64, ptr undef, align 4 %2 = shl i32 5, 0 %3 = zext i32 %2 to i64 %4 = and i64 %1, %3 diff --git a/llvm/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll b/llvm/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll index 6f6624d1bbc7cc..4463e63085b82c 100644 --- a/llvm/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll +++ b/llvm/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll @@ -2,20 +2,16 @@ target triple = "armv6-none-linux-gnueabi" -define void @sample_test(i8* %.T0348, i16* nocapture %sourceA, i16* nocapture %destValues) { +define void @sample_test(ptr %.T0348, ptr nocapture %sourceA, ptr nocapture %destValues) { L.entry: - %0 = call i32 (...) @get_index(i8* %.T0348, i32 0) - %1 = bitcast i16* %destValues to i8* - %2 = mul i32 %0, 6 - %3 = getelementptr i8, i8* %1, i32 %2 - %4 = bitcast i8* %3 to <3 x i16>* - %5 = load <3 x i16>, <3 x i16>* %4, align 1 - %6 = bitcast i16* %sourceA to i8* - %7 = getelementptr i8, i8* %6, i32 %2 - %8 = bitcast i8* %7 to <3 x i16>* - %9 = load <3 x i16>, <3 x i16>* %8, align 1 - %10 = or <3 x i16> %9, %5 - store <3 x i16> %10, <3 x i16>* %4, align 1 + %0 = call i32 (...) @get_index(ptr %.T0348, i32 0) + %1 = mul i32 %0, 6 + %2 = getelementptr i8, ptr %destValues, i32 %1 + %3 = load <3 x i16>, ptr %2, align 1 + %4 = getelementptr i8, ptr %sourceA, i32 %1 + %5 = load <3 x i16>, ptr %4, align 1 + %6 = or <3 x i16> %5, %3 + store <3 x i16> %6, ptr %2, align 1 ret void } diff --git a/llvm/test/CodeGen/ARM/2011-10-26-memset-inline.ll b/llvm/test/CodeGen/ARM/2011-10-26-memset-inline.ll index 8d6ce34c26d993..b4f368e1c00e42 100644 --- a/llvm/test/CodeGen/ARM/2011-10-26-memset-inline.ll +++ b/llvm/test/CodeGen/ARM/2011-10-26-memset-inline.ll @@ -12,10 +12,10 @@ target triple = "thumbv7-apple-ios5.0.0" ; CHECK-GENERIC-NEXT: strb ; CHECK-UNALIGNED: strb ; CHECK-UNALIGNED: str -define void @foo(i8* nocapture %c) nounwind optsize { +define void @foo(ptr nocapture %c) nounwind optsize { entry: - call void @llvm.memset.p0i8.i64(i8* %c, i8 -1, i64 5, i1 false) + call void @llvm.memset.p0.i64(ptr %c, i8 -1, i64 5, i1 false) ret void } -declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind +declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind diff --git a/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll b/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll index 7024a653b6c9f9..b394f8194aac2e 100644 --- a/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll +++ b/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll @@ -3,10 +3,10 @@ ; Trigger multiple NEON stores. ; CHECK: vst1.64 ; CHECK: vst1.64 -define void @f_0_40(i8* nocapture %c) nounwind optsize { +define void @f_0_40(ptr nocapture %c) nounwind optsize { entry: - call void @llvm.memset.p0i8.i64(i8* align 16 %c, i8 0, i64 40, i1 false) + call void @llvm.memset.p0.i64(ptr align 16 %c, i8 0, i64 40, i1 false) ret void } -declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind +declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind diff --git a/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll b/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll index e7059716c49be1..473a4924f79606 100644 --- a/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll +++ b/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll @@ -7,18 +7,18 @@ define void @test_neon_vector_add_2xi8() nounwind { ; CHECK-LABEL: test_neon_vector_add_2xi8: - %1 = load <2 x i8>, <2 x i8>* @i8_src1 - %2 = load <2 x i8>, <2 x i8>* @i8_src2 + %1 = load <2 x i8>, ptr @i8_src1 + %2 = load <2 x i8>, ptr @i8_src2 %3 = add <2 x i8> %1, %2 - store <2 x i8> %3, <2 x i8>* @i8_res + store <2 x i8> %3, ptr @i8_res ret void } define void @test_neon_ld_st_volatile_with_ashr_2xi8() { ; CHECK-LABEL: test_neon_ld_st_volatile_with_ashr_2xi8: - %1 = load volatile <2 x i8>, <2 x i8>* @i8_src1 - %2 = load volatile <2 x i8>, <2 x i8>* @i8_src2 + %1 = load volatile <2 x i8>, ptr @i8_src1 + %2 = load volatile <2 x i8>, ptr @i8_src2 %3 = ashr <2 x i8> %1, %2 - store volatile <2 x i8> %3, <2 x i8>* @i8_res + store volatile <2 x i8> %3, ptr @i8_res ret void } diff --git a/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll b/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll index 6dc9d4b7025d9e..1fc43c3257e91b 100644 --- a/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll +++ b/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll @@ -8,8 +8,8 @@ declare <2 x i16> @foo_v2i16(<2 x i16>) nounwind define void @test_neon_call_return_v2i16() { ; CHECK-LABEL: test_neon_call_return_v2i16: - %1 = load <2 x i16>, <2 x i16>* @src1_v2i16 + %1 = load <2 x i16>, ptr @src1_v2i16 %2 = call <2 x i16> @foo_v2i16(<2 x i16> %1) nounwind - store <2 x i16> %2, <2 x i16>* @res_v2i16 + store <2 x i16> %2, ptr @res_v2i16 ret void } diff --git a/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll b/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll index 1da93bdd7c947f..4289838528794b 100644 --- a/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll +++ b/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll @@ -1,37 +1,37 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -define <2 x i32> @test1(<2 x double>* %A) { +define <2 x i32> @test1(ptr %A) { ; CHECK: test1 ; CHECK: vcvt.s32.f64 ; CHECK: vcvt.s32.f64 - %tmp1 = load <2 x double>, <2 x double>* %A + %tmp1 = load <2 x double>, ptr %A %tmp2 = fptosi <2 x double> %tmp1 to <2 x i32> ret <2 x i32> %tmp2 } -define <2 x i32> @test2(<2 x double>* %A) { +define <2 x i32> @test2(ptr %A) { ; CHECK: test2 ; CHECK: vcvt.u32.f64 ; CHECK: vcvt.u32.f64 - %tmp1 = load <2 x double>, <2 x double>* %A + %tmp1 = load <2 x double>, ptr %A %tmp2 = fptoui <2 x double> %tmp1 to <2 x i32> ret <2 x i32> %tmp2 } -define <2 x double> @test3(<2 x i32>* %A) { +define <2 x double> @test3(ptr %A) { ; CHECK: test3 ; CHECK: vcvt.f64.s32 ; CHECK: vcvt.f64.s32 - %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp1 = load <2 x i32>, ptr %A %tmp2 = sitofp <2 x i32> %tmp1 to <2 x double> ret <2 x double> %tmp2 } -define <2 x double> @test4(<2 x i32>* %A) { +define <2 x double> @test4(ptr %A) { ; CHECK: test4 ; CHECK: vcvt.f64.u32 ; CHECK: vcvt.f64.u32 - %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp1 = load <2 x i32>, ptr %A %tmp2 = uitofp <2 x i32> %tmp1 to <2 x double> ret <2 x double> %tmp2 } diff --git a/llvm/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll b/llvm/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll index 38fc3bcd8873e3..89c1cebd404cb1 100644 --- a/llvm/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll +++ b/llvm/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll @@ -15,45 +15,45 @@ target triple = "thumbv7-apple-ios" %struct.Transform_Struct.0.11.12.17.43.46.56.58.60 = type { [4 x [4 x double]] } -define void @Compute_Axis_Rotation_Transform(%struct.Transform_Struct.0.11.12.17.43.46.56.58.60* nocapture %transform, double* nocapture %V1, double %angle) nounwind { +define void @Compute_Axis_Rotation_Transform(ptr nocapture %transform, ptr nocapture %V1, double %angle) nounwind { entry: - store double 1.000000e+00, double* null, align 4 - %arrayidx5.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 1 - store double 0.000000e+00, double* %arrayidx5.1.i, align 4 - %arrayidx5.2.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 2 - store double 0.000000e+00, double* %arrayidx5.2.i, align 4 - %arrayidx5.114.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 0 - store double 0.000000e+00, double* %arrayidx5.114.i, align 4 - %arrayidx5.1.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 1 - store double 1.000000e+00, double* %arrayidx5.1.1.i, align 4 - store double 0.000000e+00, double* null, align 4 - store double 1.000000e+00, double* null, align 4 - store double 0.000000e+00, double* null, align 4 + store double 1.000000e+00, ptr null, align 4 + %arrayidx5.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, ptr %transform, i32 0, i32 0, i32 0, i32 1 + store double 0.000000e+00, ptr %arrayidx5.1.i, align 4 + %arrayidx5.2.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, ptr %transform, i32 0, i32 0, i32 0, i32 2 + store double 0.000000e+00, ptr %arrayidx5.2.i, align 4 + %arrayidx5.114.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, ptr %transform, i32 0, i32 0, i32 1, i32 0 + store double 0.000000e+00, ptr %arrayidx5.114.i, align 4 + %arrayidx5.1.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, ptr %transform, i32 0, i32 0, i32 1, i32 1 + store double 1.000000e+00, ptr %arrayidx5.1.1.i, align 4 + store double 0.000000e+00, ptr null, align 4 + store double 1.000000e+00, ptr null, align 4 + store double 0.000000e+00, ptr null, align 4 %call = tail call double @cos(double %angle) nounwind readnone %call1 = tail call double @sin(double %angle) nounwind readnone - %0 = load double, double* %V1, align 4 - %arrayidx2 = getelementptr inbounds double, double* %V1, i32 1 - %1 = load double, double* %arrayidx2, align 4 + %0 = load double, ptr %V1, align 4 + %arrayidx2 = getelementptr inbounds double, ptr %V1, i32 1 + %1 = load double, ptr %arrayidx2, align 4 %mul = fmul double %0, %1 %sub = fsub double 1.000000e+00, %call %mul3 = fmul double %mul, %sub - %2 = load double, double* undef, align 4 + %2 = load double, ptr undef, align 4 %mul5 = fmul double %2, %call1 %add = fadd double %mul3, %mul5 - store double %add, double* %arrayidx5.1.i, align 4 - %3 = load double, double* %V1, align 4 + store double %add, ptr %arrayidx5.1.i, align 4 + %3 = load double, ptr %V1, align 4 %mul11 = fmul double %3, undef %mul13 = fmul double %mul11, %sub - %4 = load double, double* %arrayidx2, align 4 + %4 = load double, ptr %arrayidx2, align 4 %mul15 = fmul double %4, %call1 %sub16 = fsub double %mul13, %mul15 - store double %sub16, double* %arrayidx5.2.i, align 4 - %5 = load double, double* %V1, align 4 - %6 = load double, double* %arrayidx2, align 4 + store double %sub16, ptr %arrayidx5.2.i, align 4 + %5 = load double, ptr %V1, align 4 + %6 = load double, ptr %arrayidx2, align 4 %mul22 = fmul double %5, %6 %mul24 = fmul double %mul22, %sub %sub27 = fsub double %mul24, undef - store double %sub27, double* %arrayidx5.114.i, align 4 + store double %sub27, ptr %arrayidx5.114.i, align 4 ret void } diff --git a/llvm/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll b/llvm/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll index d820d688fde93f..01648486489cd5 100644 --- a/llvm/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll +++ b/llvm/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll @@ -15,14 +15,14 @@ define hidden void @foo() { ; CHECK: ldr.w ; CHECK-NOT: ldm entry: - %tmp13 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 0), align 1 - %tmp15 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 1), align 1 - %tmp17 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 2), align 1 - %tmp19 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 3), align 1 - %tmp = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 0), align 1 - %tmp3 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 1), align 1 - %tmp4 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 2), align 1 - %tmp5 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 3), align 1 + %tmp13 = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 1, i32 0, i32 0), align 1 + %tmp15 = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 1, i32 0, i32 1), align 1 + %tmp17 = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 1, i32 0, i32 2), align 1 + %tmp19 = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 1, i32 0, i32 3), align 1 + %tmp = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 2, i32 0, i32 0), align 1 + %tmp3 = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 2, i32 0, i32 1), align 1 + %tmp4 = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 2, i32 0, i32 2), align 1 + %tmp5 = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 2, i32 0, i32 3), align 1 %insert21 = insertvalue [4 x i32] undef, i32 %tmp13, 0 %insert23 = insertvalue [4 x i32] %insert21, i32 %tmp15, 1 %insert25 = insertvalue [4 x i32] %insert23, i32 %tmp17, 2 diff --git a/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll b/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll index 274f7bd4fb314e..e14e598086249e 100644 --- a/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll +++ b/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll @@ -2,7 +2,7 @@ @A = global <4 x float> -define void @test_sqrt(<4 x float>* %X) nounwind { +define void @test_sqrt(ptr %X) nounwind { ; CHECK-LABEL: test_sqrt: @@ -16,16 +16,16 @@ define void @test_sqrt(<4 x float>* %X) nounwind { ; CHECK: vst1.64 {{.*}} L.entry: - %0 = load <4 x float>, <4 x float>* @A, align 16 + %0 = load <4 x float>, ptr @A, align 16 %1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0) - store <4 x float> %1, <4 x float>* %X, align 16 + store <4 x float> %1, ptr %X, align 16 ret void } declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly -define void @test_cos(<4 x float>* %X) nounwind { +define void @test_cos(ptr %X) nounwind { ; CHECK-LABEL: test_cos: @@ -48,15 +48,15 @@ define void @test_cos(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>, <4 x float>* @A, align 16 + %0 = load <4 x float>, ptr @A, align 16 %1 = call <4 x float> @llvm.cos.v4f32(<4 x float> %0) - store <4 x float> %1, <4 x float>* %X, align 16 + store <4 x float> %1, ptr %X, align 16 ret void } declare <4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly -define void @test_exp(<4 x float>* %X) nounwind { +define void @test_exp(ptr %X) nounwind { ; CHECK-LABEL: test_exp: @@ -79,15 +79,15 @@ define void @test_exp(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>, <4 x float>* @A, align 16 + %0 = load <4 x float>, ptr @A, align 16 %1 = call <4 x float> @llvm.exp.v4f32(<4 x float> %0) - store <4 x float> %1, <4 x float>* %X, align 16 + store <4 x float> %1, ptr %X, align 16 ret void } declare <4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly -define void @test_exp2(<4 x float>* %X) nounwind { +define void @test_exp2(ptr %X) nounwind { ; CHECK-LABEL: test_exp2: @@ -110,15 +110,15 @@ define void @test_exp2(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>, <4 x float>* @A, align 16 + %0 = load <4 x float>, ptr @A, align 16 %1 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %0) - store <4 x float> %1, <4 x float>* %X, align 16 + store <4 x float> %1, ptr %X, align 16 ret void } declare <4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly -define void @test_log10(<4 x float>* %X) nounwind { +define void @test_log10(ptr %X) nounwind { ; CHECK-LABEL: test_log10: @@ -141,15 +141,15 @@ define void @test_log10(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>, <4 x float>* @A, align 16 + %0 = load <4 x float>, ptr @A, align 16 %1 = call <4 x float> @llvm.log10.v4f32(<4 x float> %0) - store <4 x float> %1, <4 x float>* %X, align 16 + store <4 x float> %1, ptr %X, align 16 ret void } declare <4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonly -define void @test_log(<4 x float>* %X) nounwind { +define void @test_log(ptr %X) nounwind { ; CHECK-LABEL: test_log: @@ -172,15 +172,15 @@ define void @test_log(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>, <4 x float>* @A, align 16 + %0 = load <4 x float>, ptr @A, align 16 %1 = call <4 x float> @llvm.log.v4f32(<4 x float> %0) - store <4 x float> %1, <4 x float>* %X, align 16 + store <4 x float> %1, ptr %X, align 16 ret void } declare <4 x float> @llvm.log.v4f32(<4 x float>) nounwind readonly -define void @test_log2(<4 x float>* %X) nounwind { +define void @test_log2(ptr %X) nounwind { ; CHECK-LABEL: test_log2: @@ -203,16 +203,16 @@ define void @test_log2(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>, <4 x float>* @A, align 16 + %0 = load <4 x float>, ptr @A, align 16 %1 = call <4 x float> @llvm.log2.v4f32(<4 x float> %0) - store <4 x float> %1, <4 x float>* %X, align 16 + store <4 x float> %1, ptr %X, align 16 ret void } declare <4 x float> @llvm.log2.v4f32(<4 x float>) nounwind readonly -define void @test_pow(<4 x float>* %X) nounwind { +define void @test_pow(ptr %X) nounwind { ; CHECK-LABEL: test_pow: @@ -236,17 +236,17 @@ define void @test_pow(<4 x float>* %X) nounwind { L.entry: - %0 = load <4 x float>, <4 x float>* @A, align 16 + %0 = load <4 x float>, ptr @A, align 16 %1 = call <4 x float> @llvm.pow.v4f32(<4 x float> %0, <4 x float> ) - store <4 x float> %1, <4 x float>* %X, align 16 + store <4 x float> %1, ptr %X, align 16 ret void } declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) nounwind readonly -define void @test_powi(<4 x float>* %X) nounwind { +define void @test_powi(ptr %X) nounwind { ; CHECK-LABEL: test_powi: @@ -259,17 +259,17 @@ define void @test_powi(<4 x float>* %X) nounwind { L.entry: - %0 = load <4 x float>, <4 x float>* @A, align 16 + %0 = load <4 x float>, ptr @A, align 16 %1 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> %0, i32 2) - store <4 x float> %1, <4 x float>* %X, align 16 + store <4 x float> %1, ptr %X, align 16 ret void } declare <4 x float> @llvm.powi.v4f32.i32(<4 x float>, i32) nounwind readonly -define void @test_sin(<4 x float>* %X) nounwind { +define void @test_sin(ptr %X) nounwind { ; CHECK-LABEL: test_sin: @@ -292,15 +292,15 @@ define void @test_sin(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>, <4 x float>* @A, align 16 + %0 = load <4 x float>, ptr @A, align 16 %1 = call <4 x float> @llvm.sin.v4f32(<4 x float> %0) - store <4 x float> %1, <4 x float>* %X, align 16 + store <4 x float> %1, ptr %X, align 16 ret void } declare <4 x float> @llvm.sin.v4f32(<4 x float>) nounwind readonly -define void @test_floor(<4 x float>* %X) nounwind { +define void @test_floor(ptr %X) nounwind { ; CHECK-LABEL: test_floor: @@ -323,9 +323,9 @@ define void @test_floor(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>, <4 x float>* @A, align 16 + %0 = load <4 x float>, ptr @A, align 16 %1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0) - store <4 x float> %1, <4 x float>* %X, align 16 + store <4 x float> %1, ptr %X, align 16 ret void } diff --git a/llvm/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll b/llvm/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll index 0d324404d7beab..16ea46f8a1c2a8 100644 --- a/llvm/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll +++ b/llvm/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll @@ -8,9 +8,9 @@ target triple = "thumbv7-apple-darwin10" @x2 = internal global i64 12 define i64 @f() { - %ax = load i32, i32* @x1 + %ax = load i32, ptr @x1 %a = zext i32 %ax to i64 - %b = load i64, i64* @x2 + %b = load i64, ptr @x2 %c = add i64 %a, %b ret i64 %c } diff --git a/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll b/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll index 88019f450e3663..de71e9e6271e4a 100644 --- a/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll +++ b/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll @@ -16,14 +16,14 @@ for.cond: ; preds = %for.body, %entry for.body: ; preds = %for.cond %cond0 = icmp ne i32 %arg1, 42 %v.5 = select i1 %cond0, i32 undef, i32 0 - %0 = load i8, i8* undef, align 1 + %0 = load i8, ptr undef, align 1 %conv88 = zext i8 %0 to i32 %sub89 = sub nsw i32 0, %conv88 %cond1 = icmp ne i32 %arg1, 23 %v.8 = select i1 %cond1, i32 undef, i32 %sub89 - %1 = load i8, i8* null, align 1 + %1 = load i8, ptr null, align 1 %conv108 = zext i8 %1 to i32 - %2 = load i8, i8* undef, align 1 + %2 = load i8, ptr undef, align 1 %conv110 = zext i8 %2 to i32 %sub111 = sub nsw i32 %conv108, %conv110 %cmp112 = icmp slt i32 %sub111, 0 diff --git a/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll b/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll index b00cc51d9842d0..6728b9d4584c26 100644 --- a/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll +++ b/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll @@ -6,50 +6,49 @@ ; CHECK: push {r4, r5, r6, r7, lr} %0 = type opaque -%struct.NSConstantString = type { i32*, i32, i8*, i32 } +%struct.NSConstantString = type { ptr, i32, ptr, i32 } -define i32 @asdf(i32 %a, i32 %b, i8** %c, i8* %d) personality i8* bitcast (i32 (...)* @__objc_personality_v0 to i8*) { +define i32 @asdf(i32 %a, i32 %b, ptr %c, ptr %d) personality ptr @__objc_personality_v0 { bb: %tmp = alloca i32, align 4 %tmp1 = alloca i32, align 4 - %tmp2 = alloca i8*, align 4 + %tmp2 = alloca ptr, align 4 %tmp3 = alloca i1 - %myException = alloca %0*, align 4 - %tmp4 = alloca i8* + %myException = alloca ptr, align 4 + %tmp4 = alloca ptr %tmp5 = alloca i32 - %exception = alloca %0*, align 4 - store i32 %a, i32* %tmp, align 4 - store i32 %b, i32* %tmp1, align 4 - store i8* %d, i8** %tmp2, align 4 - store i1 false, i1* %tmp3 - %tmp7 = load i8*, i8** %c - %tmp10 = invoke %0* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %0* (i8*, i8*, %0*)*)(i8* %tmp7, i8* %d, %0* null) + %exception = alloca ptr, align 4 + store i32 %a, ptr %tmp, align 4 + store i32 %b, ptr %tmp1, align 4 + store ptr %d, ptr %tmp2, align 4 + store i1 false, ptr %tmp3 + %tmp7 = load ptr, ptr %c + %tmp10 = invoke ptr @objc_msgSend(ptr %tmp7, ptr %d, ptr null) to label %bb11 unwind label %bb15 bb11: ; preds = %bb - store %0* %tmp10, %0** %myException, align 4 - %tmp12 = load %0*, %0** %myException, align 4 - %tmp13 = bitcast %0* %tmp12 to i8* - invoke void @objc_exception_throw(i8* %tmp13) noreturn + store ptr %tmp10, ptr %myException, align 4 + %tmp12 = load ptr, ptr %myException, align 4 + invoke void @objc_exception_throw(ptr %tmp12) noreturn to label %bb14 unwind label %bb15 bb14: ; preds = %bb11 unreachable bb15: ; preds = %bb11, %bb - %tmp16 = landingpad { i8*, i32 } - catch i8* null - %tmp17 = extractvalue { i8*, i32 } %tmp16, 0 - store i8* %tmp17, i8** %tmp4 - %tmp18 = extractvalue { i8*, i32 } %tmp16, 1 - store i32 %tmp18, i32* %tmp5 - store i1 true, i1* %tmp3 + %tmp16 = landingpad { ptr, i32 } + catch ptr null + %tmp17 = extractvalue { ptr, i32 } %tmp16, 0 + store ptr %tmp17, ptr %tmp4 + %tmp18 = extractvalue { ptr, i32 } %tmp16, 1 + store i32 %tmp18, ptr %tmp5 + store i1 true, ptr %tmp3 br label %bb56 bb56: unreachable } -declare i8* @objc_msgSend(i8*, i8*, ...) nonlazybind +declare ptr @objc_msgSend(ptr, ptr, ...) nonlazybind declare i32 @__objc_personality_v0(...) -declare void @objc_exception_throw(i8*) +declare void @objc_exception_throw(ptr) diff --git a/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll b/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll index 3f827f8e702f8a..0fe855eea57f79 100644 --- a/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll +++ b/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll @@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" target triple = "armv7-none-linux-gnueabi" -define arm_aapcs_vfpcc void @foo(i8* nocapture %arg) nounwind uwtable align 2 { +define arm_aapcs_vfpcc void @foo(ptr nocapture %arg) nounwind uwtable align 2 { bb: br i1 undef, label %bb1, label %bb2 @@ -18,7 +18,7 @@ bb3: ; preds = %bb4, %bb2 br i1 %tmp, label %bb4, label %bb67 bb4: ; preds = %bb3 - %tmp5 = load <4 x i32>, <4 x i32>* undef, align 16 + %tmp5 = load <4 x i32>, ptr undef, align 16 %tmp6 = and <4 x i32> %tmp5, %tmp7 = or <4 x i32> %tmp6, %tmp8 = bitcast <4 x i32> %tmp7 to <4 x float> @@ -36,14 +36,14 @@ bb4: ; preds = %bb3 %tmp20 = fmul <4 x float> %tmp19, %tmp18 %tmp21 = fmul <4 x float> %tmp20, zeroinitializer %tmp22 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp21, <4 x float> undef) nounwind - call arm_aapcs_vfpcc void @bar(i8* null, i8* undef, <4 x i32>* undef, [2 x i64] zeroinitializer) nounwind + call arm_aapcs_vfpcc void @bar(ptr null, ptr undef, ptr undef, [2 x i64] zeroinitializer) nounwind %tmp23 = bitcast <4 x float> %tmp22 to i128 %tmp24 = trunc i128 %tmp23 to i64 %tmp25 = insertvalue [2 x i64] undef, i64 %tmp24, 0 %tmp26 = insertvalue [2 x i64] %tmp25, i64 0, 1 - %tmp27 = load float, float* undef, align 4 + %tmp27 = load float, ptr undef, align 4 %tmp28 = insertelement <4 x float> undef, float %tmp27, i32 3 - %tmp29 = load <4 x i32>, <4 x i32>* undef, align 16 + %tmp29 = load <4 x i32>, ptr undef, align 16 %tmp30 = and <4 x i32> %tmp29, %tmp31 = or <4 x i32> %tmp30, %tmp32 = bitcast <4 x i32> %tmp31 to <4 x float> @@ -51,11 +51,11 @@ bb4: ; preds = %bb3 %tmp34 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> undef, <4 x float> %tmp28) nounwind %tmp35 = fmul <4 x float> %tmp34, undef %tmp36 = fmul <4 x float> %tmp35, undef - %tmp37 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind - %tmp38 = load float, float* undef, align 4 + %tmp37 = call arm_aapcs_vfpcc ptr undef(ptr undef) nounwind + %tmp38 = load float, ptr undef, align 4 %tmp39 = insertelement <2 x float> undef, float %tmp38, i32 0 - %tmp40 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind - %tmp41 = load float, float* undef, align 4 + %tmp40 = call arm_aapcs_vfpcc ptr undef(ptr undef) nounwind + %tmp41 = load float, ptr undef, align 4 %tmp42 = insertelement <4 x float> undef, float %tmp41, i32 3 %tmp43 = shufflevector <2 x float> %tmp39, <2 x float> undef, <4 x i32> zeroinitializer %tmp44 = fmul <4 x float> %tmp33, %tmp43 @@ -63,11 +63,11 @@ bb4: ; preds = %bb3 %tmp46 = fsub <4 x float> %tmp45, undef %tmp47 = fmul <4 x float> %tmp46, %tmp36 %tmp48 = fadd <4 x float> undef, %tmp47 - %tmp49 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind - %tmp50 = load float, float* undef, align 4 + %tmp49 = call arm_aapcs_vfpcc ptr undef(ptr undef) nounwind + %tmp50 = load float, ptr undef, align 4 %tmp51 = insertelement <4 x float> undef, float %tmp50, i32 3 - %tmp52 = call arm_aapcs_vfpcc float* null(i8* undef) nounwind - %tmp54 = load float, float* %tmp52, align 4 + %tmp52 = call arm_aapcs_vfpcc ptr null(ptr undef) nounwind + %tmp54 = load float, ptr %tmp52, align 4 %tmp55 = insertelement <4 x float> undef, float %tmp54, i32 3 %tmp56 = fsub <4 x float> , %tmp22 %tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounwind @@ -76,23 +76,23 @@ bb4: ; preds = %bb3 %tmp60 = fsub <4 x float> , %tmp58 %tmp61 = fmul <4 x float> %tmp59, %tmp60 %tmp62 = fadd <4 x float> %tmp48, %tmp61 - call arm_aapcs_vfpcc void @baz(i8* undef, i8* undef, [2 x i64] %tmp26, <4 x i32>* undef) + call arm_aapcs_vfpcc void @baz(ptr undef, ptr undef, [2 x i64] %tmp26, ptr undef) %tmp63 = bitcast <4 x float> %tmp62 to i128 %tmp64 = lshr i128 %tmp63, 64 %tmp65 = trunc i128 %tmp64 to i64 %tmp66 = insertvalue [2 x i64] zeroinitializer, i64 %tmp65, 1 - call arm_aapcs_vfpcc void @quux(i8* undef, i8* undef, [2 x i64] undef, i8* undef, [2 x i64] %tmp66, i8* undef, i8* undef, [2 x i64] %tmp26, [2 x i64] %tmp15, <4 x i32>* undef) + call arm_aapcs_vfpcc void @quux(ptr undef, ptr undef, [2 x i64] undef, ptr undef, [2 x i64] %tmp66, ptr undef, ptr undef, [2 x i64] %tmp26, [2 x i64] %tmp15, ptr undef) br label %bb3 bb67: ; preds = %bb3 ret void } -declare arm_aapcs_vfpcc void @bar(i8*, i8*, <4 x i32>*, [2 x i64]) +declare arm_aapcs_vfpcc void @bar(ptr, ptr, ptr, [2 x i64]) -declare arm_aapcs_vfpcc void @baz(i8*, i8* nocapture, [2 x i64], <4 x i32>* nocapture) nounwind uwtable inlinehint align 2 +declare arm_aapcs_vfpcc void @baz(ptr, ptr nocapture, [2 x i64], ptr nocapture) nounwind uwtable inlinehint align 2 -declare arm_aapcs_vfpcc void @quux(i8*, i8*, [2 x i64], i8* nocapture, [2 x i64], i8* nocapture, i8* nocapture, [2 x i64], [2 x i64], <4 x i32>* nocapture) nounwind uwtable inlinehint align 2 +declare arm_aapcs_vfpcc void @quux(ptr, ptr, [2 x i64], ptr nocapture, [2 x i64], ptr nocapture, ptr nocapture, [2 x i64], [2 x i64], ptr nocapture) nounwind uwtable inlinehint align 2 declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone diff --git a/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll b/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll index f622ceb584e6e0..c01a35ad658871 100644 --- a/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll +++ b/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll @@ -5,9 +5,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "armv7-none-linux-eabi" ; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE. -define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 { +define arm_aapcs_vfpcc void @foo(ptr nocapture %arg, ptr %arg1) nounwind align 2 { bb: - %tmp = load <2 x float>, <2 x float>* undef, align 8 + %tmp = load <2 x float>, ptr undef, align 8 %tmp2 = extractelement <2 x float> %tmp, i32 0 %tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0 %tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1 @@ -25,7 +25,7 @@ bb: %tmp16 = shufflevector <2 x i64> %tmp15, <2 x i64> undef, <1 x i32> zeroinitializer %tmp17 = bitcast <1 x i64> %tmp16 to <2 x float> %tmp18 = extractelement <2 x float> %tmp17, i32 0 - tail call arm_aapcs_vfpcc void @bar(i8* undef, float %tmp18, float undef, float 0.000000e+00) nounwind + tail call arm_aapcs_vfpcc void @bar(ptr undef, float %tmp18, float undef, float 0.000000e+00) nounwind %tmp19 = bitcast <4 x float> %tmp10 to <2 x i64> %tmp20 = shufflevector <2 x i64> %tmp19, <2 x i64> undef, <1 x i32> zeroinitializer %tmp21 = bitcast <1 x i64> %tmp20 to <2 x float> @@ -34,7 +34,7 @@ bb: %tmp24 = shufflevector <2 x i64> %tmp23, <2 x i64> undef, <1 x i32> zeroinitializer %tmp25 = bitcast <1 x i64> %tmp24 to <2 x float> %tmp26 = extractelement <2 x float> %tmp25, i32 0 - tail call arm_aapcs_vfpcc void @bar(i8* undef, float undef, float %tmp26, float 0.000000e+00) nounwind + tail call arm_aapcs_vfpcc void @bar(ptr undef, float undef, float %tmp26, float 0.000000e+00) nounwind ret void } @@ -52,8 +52,8 @@ cond.end295: ; preds = %entry %shuffle.i35.i.i = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer %shuffle.i34.i.i = shufflevector <1 x i64> %shuffle.i36.i.i, <1 x i64> %shuffle.i35.i.i, <2 x i32> %2 = bitcast <2 x i64> %shuffle.i34.i.i to <4 x float> - tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* undef, <4 x float> %0, i32 4) nounwind - tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* undef, <4 x float> %2, i32 4) nounwind + tail call void @llvm.arm.neon.vst1.p0.v4f32(ptr undef, <4 x float> %0, i32 4) nounwind + tail call void @llvm.arm.neon.vst1.p0.v4f32(ptr undef, <4 x float> %2, i32 4) nounwind unreachable for.end: ; preds = %entry @@ -61,12 +61,12 @@ for.end: ; preds = %entry } ; Check that pseudo-expansion preserves flags. -define void @foo3(i8* %p) nounwind ssp { +define void @foo3(ptr %p) nounwind ssp { entry: - tail call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %p, <4 x float> undef, <4 x float> undef, i32 4) + tail call void @llvm.arm.neon.vst2.p0.v4f32(ptr %p, <4 x float> undef, <4 x float> undef, i32 4) ret void } -declare arm_aapcs_vfpcc void @bar(i8*, float, float, float) -declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind -declare void @llvm.arm.neon.vst2.p0i8.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind +declare arm_aapcs_vfpcc void @bar(ptr, float, float, float) +declare void @llvm.arm.neon.vst1.p0.v4f32(ptr, <4 x float>, i32) nounwind +declare void @llvm.arm.neon.vst2.p0.v4f32(ptr, <4 x float>, <4 x float>, i32) nounwind diff --git a/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll b/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll index 0ee79086e9fffb..e0f554cf6e056f 100644 --- a/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll +++ b/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll @@ -6,7 +6,7 @@ target triple = "armv7-none-linux-gnueabi" ; This test case exercises the MachineCopyPropagation pass by disabling the ; RegisterCoalescer. -define arm_aapcs_vfpcc void @foo(i8* %arg) nounwind uwtable align 2 { +define arm_aapcs_vfpcc void @foo(ptr %arg) nounwind uwtable align 2 { bb: br i1 undef, label %bb1, label %bb2 @@ -56,9 +56,9 @@ bb3: ; preds = %bb2 %tmp39 = shufflevector <2 x i64> %tmp38, <2 x i64> undef, <1 x i32> zeroinitializer %tmp40 = bitcast <1 x i64> %tmp39 to <2 x float> %tmp41 = shufflevector <2 x float> %tmp40, <2 x float> undef, <4 x i32> - %tmp42 = load <4 x float>, <4 x float>* null, align 16 + %tmp42 = load <4 x float>, ptr null, align 16 %tmp43 = fmul <4 x float> %tmp42, %tmp41 - %tmp44 = load <4 x float>, <4 x float>* undef, align 16 + %tmp44 = load <4 x float>, ptr undef, align 16 %tmp45 = fadd <4 x float> undef, %tmp43 %tmp46 = fadd <4 x float> undef, %tmp45 %tmp47 = bitcast <4 x float> %tmp36 to <2 x i64> @@ -76,8 +76,8 @@ bb3: ; preds = %bb2 %tmp59 = fmul <4 x float> undef, %tmp58 %tmp60 = fadd <4 x float> %tmp59, undef %tmp61 = fadd <4 x float> %tmp60, zeroinitializer - %tmp62 = load void (i8*, i8*)*, void (i8*, i8*)** undef, align 4 - call arm_aapcs_vfpcc void %tmp62(i8* sret(i8) undef, i8* undef) nounwind + %tmp62 = load ptr, ptr undef, align 4 + call arm_aapcs_vfpcc void %tmp62(ptr sret(i8) undef, ptr undef) nounwind %tmp63 = bitcast <4 x float> %tmp46 to i128 %tmp64 = bitcast <4 x float> %tmp54 to i128 %tmp65 = bitcast <4 x float> %tmp61 to i128 @@ -93,10 +93,9 @@ bb3: ; preds = %bb2 %tmp75 = insertvalue [8 x i64] %tmp74, i64 undef, 5 %tmp76 = insertvalue [8 x i64] %tmp75, i64 undef, 6 %tmp77 = insertvalue [8 x i64] %tmp76, i64 undef, 7 - call arm_aapcs_vfpcc void @bar(i8* sret(i8) null, [8 x i64] %tmp77) nounwind - %tmp78 = call arm_aapcs_vfpcc i8* null(i8* null) nounwind - %tmp79 = bitcast i8* %tmp78 to i512* - %tmp80 = load i512, i512* %tmp79, align 16 + call arm_aapcs_vfpcc void @bar(ptr sret(i8) null, [8 x i64] %tmp77) nounwind + %tmp78 = call arm_aapcs_vfpcc ptr null(ptr null) nounwind + %tmp80 = load i512, ptr %tmp78, align 16 %tmp81 = lshr i512 %tmp80, 128 %tmp82 = trunc i512 %tmp80 to i128 %tmp83 = trunc i512 %tmp81 to i128 @@ -108,11 +107,11 @@ bb3: ; preds = %bb2 %tmp89 = fmul <4 x float> undef, %tmp88 %tmp90 = fadd <4 x float> %tmp89, undef %tmp91 = fadd <4 x float> undef, %tmp90 - store <4 x float> %tmp91, <4 x float>* undef, align 16 + store <4 x float> %tmp91, ptr undef, align 16 unreachable bb92: ; preds = %bb2 ret void } -declare arm_aapcs_vfpcc void @bar(i8* noalias nocapture sret(i8), [8 x i64]) nounwind uwtable inlinehint +declare arm_aapcs_vfpcc void @bar(ptr noalias nocapture sret(i8), [8 x i64]) nounwind uwtable inlinehint diff --git a/llvm/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll b/llvm/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll index b0411384b96ae6..3838bceb458f37 100644 --- a/llvm/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll +++ b/llvm/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll @@ -10,7 +10,7 @@ target triple = "armv7-none-linux-gnueabi" @foo = external global %0, align 16 define arm_aapcs_vfpcc void @bar(float, i1 zeroext, i1 zeroext) nounwind { - %4 = load <4 x float>, <4 x float>* getelementptr inbounds (%0, %0* @foo, i32 0, i32 0), align 16 + %4 = load <4 x float>, ptr @foo, align 16 %5 = extractelement <4 x float> %4, i32 0 %6 = extractelement <4 x float> %4, i32 1 %7 = extractelement <4 x float> %4, i32 2 @@ -18,9 +18,9 @@ define arm_aapcs_vfpcc void @bar(float, i1 zeroext, i1 zeroext) nounwind { %9 = insertelement <4 x float> %8, float %6, i32 1 %10 = insertelement <4 x float> %9, float %7, i32 2 %11 = insertelement <4 x float> %10, float 0.000000e+00, i32 3 - store <4 x float> %11, <4 x float>* undef, align 16 - call arm_aapcs_vfpcc void @baz(%1* undef, float 0.000000e+00) nounwind + store <4 x float> %11, ptr undef, align 16 + call arm_aapcs_vfpcc void @baz(ptr undef, float 0.000000e+00) nounwind ret void } -declare arm_aapcs_vfpcc void @baz(%1*, float) +declare arm_aapcs_vfpcc void @baz(ptr, float) diff --git a/llvm/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll b/llvm/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll index 6fb760c4bcc7ef..6e8f1f2208e2b1 100644 --- a/llvm/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll +++ b/llvm/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll @@ -4,12 +4,12 @@ ; DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) to ; (i16 load $addr+c*sizeof(i16)). It should have issued an extload instead. i.e. ; (i32 extload $addr+c*sizeof(i16) -define void @test_hi_short3(<3 x i16> * nocapture %srcA, <2 x i16> * nocapture %dst) nounwind { +define void @test_hi_short3(ptr nocapture %srcA, ptr nocapture %dst) nounwind { entry: ; CHECK: vst1.32 - %0 = load <3 x i16> , <3 x i16> * %srcA, align 8 + %0 = load <3 x i16> , ptr %srcA, align 8 %1 = shufflevector <3 x i16> %0, <3 x i16> undef, <2 x i32> - store <2 x i16> %1, <2 x i16> * %dst, align 4 + store <2 x i16> %1, ptr %dst, align 4 ret void } diff --git a/llvm/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll b/llvm/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll index 0843fdc4e75e97..d55f269c1aa78b 100644 --- a/llvm/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll +++ b/llvm/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll @@ -9,11 +9,11 @@ define arm_aapcs_vfpcc void @foo() nounwind align 2 { ;