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| 1 | +//===-- X86SpeculativeExecutionSideEffectSuppression.cpp ------------------===// |
| 2 | +// |
| 3 | +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +// See https://llvm.org/LICENSE.txt for license information. |
| 5 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +// |
| 7 | +//===----------------------------------------------------------------------===// |
| 8 | +/// \file |
| 9 | +/// |
| 10 | +/// This file contains the X86 implementation of the speculative execution side |
| 11 | +/// effect suppression mitigation. |
| 12 | +/// |
| 13 | +/// This must be used with the -mlvi-cfi flag in order to mitigate indirect |
| 14 | +/// branches and returns. |
| 15 | +//===----------------------------------------------------------------------===// |
| 16 | + |
| 17 | +#include "X86.h" |
| 18 | +#include "X86InstrInfo.h" |
| 19 | +#include "X86Subtarget.h" |
| 20 | +#include "llvm/ADT/Statistic.h" |
| 21 | +#include "llvm/CodeGen/MachineFunction.h" |
| 22 | +#include "llvm/CodeGen/MachineFunctionPass.h" |
| 23 | +#include "llvm/CodeGen/MachineInstrBuilder.h" |
| 24 | +#include "llvm/Pass.h" |
| 25 | +using namespace llvm; |
| 26 | + |
| 27 | +#define DEBUG_TYPE "x86-seses" |
| 28 | + |
| 29 | +STATISTIC(NumLFENCEsInserted, "Number of lfence instructions inserted"); |
| 30 | + |
| 31 | +static cl::opt<bool> EnableSpeculativeExecutionSideEffectSuppression( |
| 32 | + "x86-seses-enable", |
| 33 | + cl::desc("Force enable speculative execution side effect suppresion. " |
| 34 | + "(Note: User must pass -mlvi-cfi in order to mitigate indirect " |
| 35 | + "branches and returns.)"), |
| 36 | + cl::init(false), cl::Hidden); |
| 37 | + |
| 38 | +static cl::opt<bool> OneLFENCEPerBasicBlock( |
| 39 | + "x86-seses-one-lfence-per-bb", |
| 40 | + cl::desc( |
| 41 | + "Omit all lfences other than the first to be placed in a basic block."), |
| 42 | + cl::init(false), cl::Hidden); |
| 43 | + |
| 44 | +static cl::opt<bool> OnlyLFENCENonConst( |
| 45 | + "x86-seses-only-lfence-non-const", |
| 46 | + cl::desc("Only lfence before groups of terminators where at least one " |
| 47 | + "branch instruction has an input to the addressing mode that is a " |
| 48 | + "register other than %rip."), |
| 49 | + cl::init(false), cl::Hidden); |
| 50 | + |
| 51 | +static cl::opt<bool> |
| 52 | + OmitBranchLFENCEs("x86-seses-omit-branch-lfences", |
| 53 | + cl::desc("Omit all lfences before branch instructions."), |
| 54 | + cl::init(false), cl::Hidden); |
| 55 | + |
| 56 | +namespace { |
| 57 | + |
| 58 | +class X86SpeculativeExecutionSideEffectSuppression |
| 59 | + : public MachineFunctionPass { |
| 60 | +public: |
| 61 | + X86SpeculativeExecutionSideEffectSuppression() : MachineFunctionPass(ID) {} |
| 62 | + |
| 63 | + static char ID; |
| 64 | + StringRef getPassName() const override { |
| 65 | + return "X86 Speculative Execution Side Effect Suppression"; |
| 66 | + } |
| 67 | + |
| 68 | + bool runOnMachineFunction(MachineFunction &MF) override; |
| 69 | +}; |
| 70 | +} // namespace |
| 71 | + |
| 72 | +char X86SpeculativeExecutionSideEffectSuppression::ID = 0; |
| 73 | + |
| 74 | +// This function returns whether the passed instruction uses a memory addressing |
| 75 | +// mode that is constant. We treat all memory addressing modes that read |
| 76 | +// from a register that is not %rip as non-constant. Note that the use |
| 77 | +// of the EFLAGS register results in an addressing mode being considered |
| 78 | +// non-constant, therefore all JCC instructions will return false from this |
| 79 | +// function since one of their operands will always be the EFLAGS register. |
| 80 | +static bool hasConstantAddressingMode(const MachineInstr &MI) { |
| 81 | + for (const MachineOperand &MO : MI.uses()) |
| 82 | + if (MO.isReg() && X86::RIP != MO.getReg()) |
| 83 | + return false; |
| 84 | + return true; |
| 85 | +} |
| 86 | + |
| 87 | +bool X86SpeculativeExecutionSideEffectSuppression::runOnMachineFunction( |
| 88 | + MachineFunction &MF) { |
| 89 | + if (!EnableSpeculativeExecutionSideEffectSuppression) |
| 90 | + return false; |
| 91 | + |
| 92 | + LLVM_DEBUG(dbgs() << "********** " << getPassName() << " : " << MF.getName() |
| 93 | + << " **********\n"); |
| 94 | + bool Modified = false; |
| 95 | + const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>(); |
| 96 | + const X86InstrInfo *TII = Subtarget.getInstrInfo(); |
| 97 | + for (MachineBasicBlock &MBB : MF) { |
| 98 | + MachineInstr *FirstTerminator = nullptr; |
| 99 | + |
| 100 | + for (auto &MI : MBB) { |
| 101 | + // We want to put an LFENCE before any instruction that |
| 102 | + // may load or store. This LFENCE is intended to avoid leaking any secret |
| 103 | + // data due to a given load or store. This results in closing the cache |
| 104 | + // and memory timing side channels. We will treat terminators that load |
| 105 | + // or store separately. |
| 106 | + if (MI.mayLoadOrStore() && !MI.isTerminator()) { |
| 107 | + BuildMI(MBB, MI, DebugLoc(), TII->get(X86::LFENCE)); |
| 108 | + NumLFENCEsInserted++; |
| 109 | + Modified = true; |
| 110 | + if (OneLFENCEPerBasicBlock) |
| 111 | + break; |
| 112 | + } |
| 113 | + // The following section will be LFENCEing before groups of terminators |
| 114 | + // that include branches. This will close the branch prediction side |
| 115 | + // channels since we will prevent code executing after misspeculation as |
| 116 | + // a result of the LFENCEs placed with this logic. |
| 117 | + |
| 118 | + // Keep track of the first terminator in a basic block since if we need |
| 119 | + // to LFENCE the terminators in this basic block we must add the |
| 120 | + // instruction before the first terminator in the basic block (as |
| 121 | + // opposed to before the terminator that indicates an LFENCE is |
| 122 | + // required). An example of why this is necessary is that the |
| 123 | + // X86InstrInfo::analyzeBranch method assumes all terminators are grouped |
| 124 | + // together and terminates it's analysis once the first non-termintor |
| 125 | + // instruction is found. |
| 126 | + if (MI.isTerminator() && FirstTerminator == nullptr) |
| 127 | + FirstTerminator = &MI; |
| 128 | + |
| 129 | + // Look for branch instructions that will require an LFENCE to be put |
| 130 | + // before this basic block's terminators. |
| 131 | + if (!MI.isBranch() || OmitBranchLFENCEs) |
| 132 | + // This isn't a branch or we're not putting LFENCEs before branches. |
| 133 | + continue; |
| 134 | + |
| 135 | + if (OnlyLFENCENonConst && hasConstantAddressingMode(MI)) |
| 136 | + // This is a branch, but it only has constant addressing mode and we're |
| 137 | + // not adding LFENCEs before such branches. |
| 138 | + continue; |
| 139 | + |
| 140 | + // This branch requires adding an LFENCE. |
| 141 | + BuildMI(MBB, FirstTerminator, DebugLoc(), TII->get(X86::LFENCE)); |
| 142 | + NumLFENCEsInserted++; |
| 143 | + Modified = true; |
| 144 | + break; |
| 145 | + } |
| 146 | + } |
| 147 | + |
| 148 | + return Modified; |
| 149 | +} |
| 150 | + |
| 151 | +FunctionPass *llvm::createX86SpeculativeExecutionSideEffectSuppression() { |
| 152 | + return new X86SpeculativeExecutionSideEffectSuppression(); |
| 153 | +} |
| 154 | + |
| 155 | +INITIALIZE_PASS(X86SpeculativeExecutionSideEffectSuppression, "x86-seses", |
| 156 | + "X86 Speculative Execution Side Effect Suppresion", false, |
| 157 | + false) |
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