diff --git a/llvm/test/Transforms/InstCombine/pr50555.ll b/llvm/test/Transforms/AggressiveInstCombine/pr50555.ll
similarity index 92%
rename from llvm/test/Transforms/InstCombine/pr50555.ll
rename to llvm/test/Transforms/AggressiveInstCombine/pr50555.ll
index f779806585792..0bedd8fed6265 100644
--- a/llvm/test/Transforms/InstCombine/pr50555.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/pr50555.ll
@@ -1,11 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -instcombine -S | FileCheck %s
+; RUN: opt < %s -aggressive-instcombine -S | FileCheck %s
 
 define void @trunc_one_add(i16* %a, i8 %b) {
 ; CHECK-LABEL: @trunc_one_add(
 ; CHECK-NEXT:    [[ZEXT:%.*]] = zext i8 [[B:%.*]] to i32
 ; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[ZEXT]], 1
-; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[SHR]], [[ZEXT]]
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[ZEXT]], [[SHR]]
 ; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i32 [[ADD]] to i16
 ; CHECK-NEXT:    store i16 [[TRUNC]], i16* [[A:%.*]], align 2
 ; CHECK-NEXT:    ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr50555.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr50555.ll
index 7b9efd6110628..818ba6450fcb6 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/pr50555.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr50555.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -mtriple=x86_64-- -instcombine -slp-vectorizer -dce -S | FileCheck %s --check-prefixes=SSE
-; RUN: opt < %s -mtriple=x86_64-- -mcpu=corei7-avx -instcombine -slp-vectorizer -dce -S | FileCheck %s --check-prefixes=AVX
+; RUN: opt < %s -mtriple=x86_64-- -aggressive-instcombine -slp-vectorizer -dce -S | FileCheck %s --check-prefixes=SSE
+; RUN: opt < %s -mtriple=x86_64-- -mcpu=corei7-avx -aggressive-instcombine -slp-vectorizer -dce -S | FileCheck %s --check-prefixes=AVX
 
 define void @trunc_through_one_add(i16* noalias %0, i8* noalias readonly %1) {
 ; SSE-LABEL: @trunc_through_one_add(