diff --git a/clang-tools-extra/pseudo/include/clang-pseudo/grammar/LRTable.h b/clang-tools-extra/pseudo/include/clang-pseudo/grammar/LRTable.h index 9fc4689da22b78..1706b6936c9ea2 100644 --- a/clang-tools-extra/pseudo/include/clang-pseudo/grammar/LRTable.h +++ b/clang-tools-extra/pseudo/include/clang-pseudo/grammar/LRTable.h @@ -226,7 +226,7 @@ class LRTable { // Count the number of values since the checkpoint. Word BelowKeyMask = KeyMask - 1; unsigned CountSinceCheckpoint = - llvm::countPopulation(HasValue[KeyWord] & BelowKeyMask); + llvm::popcount(HasValue[KeyWord] & BelowKeyMask); // Find the value relative to the last checkpoint. return Values[Checkpoints[KeyWord] + CountSinceCheckpoint]; } diff --git a/clang/lib/Basic/Sanitizers.cpp b/clang/lib/Basic/Sanitizers.cpp index 7d903c8fdf5eca..62ccdf8e9bbf28 100644 --- a/clang/lib/Basic/Sanitizers.cpp +++ b/clang/lib/Basic/Sanitizers.cpp @@ -61,7 +61,7 @@ namespace clang { unsigned SanitizerMask::countPopulation() const { unsigned total = 0; for (const auto &Val : maskLoToHigh) - total += llvm::countPopulation(Val); + total += llvm::popcount(Val); return total; } diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp index 2716cf0cc56a8f..d1745d970c441f 100644 --- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp +++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp @@ -8970,7 +8970,7 @@ static bool DumpEnumValue(const clang::QualType &qual_type, Stream *s, for (auto *enumerator : enum_decl->enumerators()) { uint64_t val = enumerator->getInitVal().getSExtValue(); val = llvm::SignExtend64(val, 8*byte_size); - if (llvm::countPopulation(val) != 1 && (val & ~covered_bits) != 0) + if (llvm::popcount(val) != 1 && (val & ~covered_bits) != 0) can_be_bitfield = false; covered_bits |= val; ++num_enumerators; @@ -9006,9 +9006,10 @@ static bool DumpEnumValue(const clang::QualType &qual_type, Stream *s, // Sort in reverse order of the number of the population count, so that in // `enum {A, B, ALL = A|B }` we visit ALL first. Use a stable sort so that // A | C where A is declared before C is displayed in this order. - std::stable_sort(values.begin(), values.end(), [](const auto &a, const auto &b) { - return llvm::countPopulation(a.first) > llvm::countPopulation(b.first); - }); + std::stable_sort(values.begin(), values.end(), + [](const auto &a, const auto &b) { + return llvm::popcount(a.first) > llvm::popcount(b.first); + }); for (const auto &val : values) { if ((remaining_value & val.first) != val.first) diff --git a/lldb/source/Symbol/CompactUnwindInfo.cpp b/lldb/source/Symbol/CompactUnwindInfo.cpp index b82ead94faa1a5..64b0aa4f62adfe 100644 --- a/lldb/source/Symbol/CompactUnwindInfo.cpp +++ b/lldb/source/Symbol/CompactUnwindInfo.cpp @@ -156,7 +156,7 @@ FLAGS_ANONYMOUS_ENUM(){ #define EXTRACT_BITS(value, mask) \ ((value >> llvm::countTrailingZeros(static_cast(mask))) & \ - (((1 << llvm::countPopulation(static_cast(mask)))) - 1)) + (((1 << llvm::popcount(static_cast(mask)))) - 1)) // constructor diff --git a/llvm/include/llvm/ADT/APInt.h b/llvm/include/llvm/ADT/APInt.h index 4b0886835824a1..2374cfa2dcdc6b 100644 --- a/llvm/include/llvm/ADT/APInt.h +++ b/llvm/include/llvm/ADT/APInt.h @@ -1618,7 +1618,7 @@ class [[nodiscard]] APInt { /// \returns 0 if the value is zero, otherwise returns the number of set bits. unsigned countPopulation() const { if (isSingleWord()) - return llvm::countPopulation(U.VAL); + return llvm::popcount(U.VAL); return countPopulationSlowCase(); } diff --git a/llvm/include/llvm/ADT/BitVector.h b/llvm/include/llvm/ADT/BitVector.h index 2ba4857778166a..da7f9d2f3ae8f8 100644 --- a/llvm/include/llvm/ADT/BitVector.h +++ b/llvm/include/llvm/ADT/BitVector.h @@ -155,7 +155,7 @@ class BitVector { size_type count() const { unsigned NumBits = 0; for (auto Bit : Bits) - NumBits += countPopulation(Bit); + NumBits += llvm::popcount(Bit); return NumBits; } diff --git a/llvm/include/llvm/ADT/SmallBitVector.h b/llvm/include/llvm/ADT/SmallBitVector.h index f739f385d32ec9..f73db0ef53f672 100644 --- a/llvm/include/llvm/ADT/SmallBitVector.h +++ b/llvm/include/llvm/ADT/SmallBitVector.h @@ -200,7 +200,7 @@ class SmallBitVector { size_type count() const { if (isSmall()) { uintptr_t Bits = getSmallBits(); - return countPopulation(Bits); + return llvm::popcount(Bits); } return getPointer()->count(); } diff --git a/llvm/include/llvm/ADT/SparseBitVector.h b/llvm/include/llvm/ADT/SparseBitVector.h index a591896521ceb6..f398f3bb19ac2e 100644 --- a/llvm/include/llvm/ADT/SparseBitVector.h +++ b/llvm/include/llvm/ADT/SparseBitVector.h @@ -120,7 +120,7 @@ template struct SparseBitVectorElement { size_type count() const { unsigned NumBits = 0; for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i) - NumBits += countPopulation(Bits[i]); + NumBits += llvm::popcount(Bits[i]); return NumBits; } diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 9b94cdc9012568..21121d71a5fddc 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -2267,7 +2267,7 @@ class TargetLoweringBase { if (Exponent < 0) Exponent = -Exponent; return !OptForSize || - (countPopulation((unsigned int)Exponent) + Log2_32(Exponent) < 7); + (llvm::popcount((unsigned int)Exponent) + Log2_32(Exponent) < 7); } //===--------------------------------------------------------------------===// diff --git a/llvm/include/llvm/MC/LaneBitmask.h b/llvm/include/llvm/MC/LaneBitmask.h index efc81dce92364b..c06ca7dd5b8fcd 100644 --- a/llvm/include/llvm/MC/LaneBitmask.h +++ b/llvm/include/llvm/MC/LaneBitmask.h @@ -73,9 +73,7 @@ namespace llvm { constexpr Type getAsInteger() const { return Mask; } - unsigned getNumLanes() const { - return countPopulation(Mask); - } + unsigned getNumLanes() const { return llvm::popcount(Mask); } unsigned getHighestLane() const { return Log2_64(Mask); } diff --git a/llvm/include/llvm/MC/SubtargetFeature.h b/llvm/include/llvm/MC/SubtargetFeature.h index 642fb2ca43d239..98aed32a55d6e3 100644 --- a/llvm/include/llvm/MC/SubtargetFeature.h +++ b/llvm/include/llvm/MC/SubtargetFeature.h @@ -95,7 +95,7 @@ class FeatureBitset { size_t count() const { size_t Count = 0; for (auto B : Bits) - Count += countPopulation(B); + Count += llvm::popcount(B); return Count; } diff --git a/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h b/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h index 1c909b01a3907e..88085d0bc453b8 100644 --- a/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h +++ b/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h @@ -247,7 +247,7 @@ class ResourceState { } unsigned getNumUnits() const { - return isAResourceGroup() ? 1U : countPopulation(ResourceSizeMask); + return isAResourceGroup() ? 1U : llvm::popcount(ResourceSizeMask); } /// Checks if there is an available slot in the resource buffer. diff --git a/llvm/lib/Analysis/MemoryProfileInfo.cpp b/llvm/lib/Analysis/MemoryProfileInfo.cpp index f42fff5f195f8b..8ced1d2fd140c0 100644 --- a/llvm/lib/Analysis/MemoryProfileInfo.cpp +++ b/llvm/lib/Analysis/MemoryProfileInfo.cpp @@ -92,7 +92,7 @@ static void addAllocTypeAttribute(LLVMContext &Ctx, CallBase *CI, } static bool hasSingleAllocType(uint8_t AllocTypes) { - const unsigned NumAllocTypes = countPopulation(AllocTypes); + const unsigned NumAllocTypes = llvm::popcount(AllocTypes); assert(NumAllocTypes != 0); return NumAllocTypes == 1; } diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index f696255ccf449a..dd431cc6f4f5ff 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -2603,7 +2603,7 @@ struct ExtAddrMode : public TargetLowering::AddrMode { if (Scale && other.Scale && Scale != other.Scale) Result |= ScaleField; - if (countPopulation(Result) > 1) + if (llvm::popcount(Result) > 1) return MultipleFields; else return static_cast(Result); diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 8cb343ee871859..9820bc5270482b 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -1069,7 +1069,7 @@ void IRTranslator::emitBitTestCase(SwitchCG::BitTestBlock &BB, LLT SwitchTy = getLLTForMVT(BB.RegVT); Register Cmp; - unsigned PopCount = countPopulation(B.Mask); + unsigned PopCount = llvm::popcount(B.Mask); if (PopCount == 1) { // Testing for a single bit; just compare the shift count with what it // would need to be to shift a 1 bit in that position. diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index a7a3e3e41061f6..adb63046900340 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -1022,7 +1022,7 @@ struct FuncUnitSorter { make_range(InstrItins->beginStage(SchedClass), InstrItins->endStage(SchedClass))) { InstrStage::FuncUnits funcUnits = IS.getUnits(); - unsigned numAlternatives = countPopulation(funcUnits); + unsigned numAlternatives = llvm::popcount(funcUnits); if (numAlternatives < min) { min = numAlternatives; F = funcUnits; @@ -1068,7 +1068,7 @@ struct FuncUnitSorter { make_range(InstrItins->beginStage(SchedClass), InstrItins->endStage(SchedClass))) { InstrStage::FuncUnits FuncUnits = IS.getUnits(); - if (countPopulation(FuncUnits) == 1) + if (llvm::popcount(FuncUnits) == 1) Resources[FuncUnits]++; } return; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index dc34362c70d77f..37ffe140a814ad 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -2895,7 +2895,7 @@ void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, MVT VT = BB.RegVT; SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); SDValue Cmp; - unsigned PopCount = countPopulation(B.Mask); + unsigned PopCount = llvm::popcount(B.Mask); const TargetLowering &TLI = DAG.getTargetLoweringInfo(); if (PopCount == 1) { // Testing for a single bit; just compare the shift count with what it diff --git a/llvm/lib/DebugInfo/PDB/Native/GlobalsStream.cpp b/llvm/lib/DebugInfo/PDB/Native/GlobalsStream.cpp index 7217fe38be551c..33e21fd85715e5 100644 --- a/llvm/lib/DebugInfo/PDB/Native/GlobalsStream.cpp +++ b/llvm/lib/DebugInfo/PDB/Native/GlobalsStream.cpp @@ -156,7 +156,7 @@ readGSIHashBuckets(FixedStreamArray &HashBuckets, uint32_t NumBuckets = 0; for (uint32_t B : HashBitmap) - NumBuckets += countPopulation(B); + NumBuckets += llvm::popcount(B); // Hash buckets follow. if (auto EC = Reader.readArray(HashBuckets, NumBuckets)) diff --git a/llvm/lib/MC/MCSchedule.cpp b/llvm/lib/MC/MCSchedule.cpp index 209b24a7d4ac4b..9f00064f501bb2 100644 --- a/llvm/lib/MC/MCSchedule.cpp +++ b/llvm/lib/MC/MCSchedule.cpp @@ -140,7 +140,7 @@ MCSchedModel::getReciprocalThroughput(unsigned SchedClass, for (; I != E; ++I) { if (!I->getCycles()) continue; - double Temp = countPopulation(I->getUnits()) * 1.0 / I->getCycles(); + double Temp = llvm::popcount(I->getUnits()) * 1.0 / I->getCycles(); Throughput = Throughput ? std::min(*Throughput, Temp) : Temp; } if (Throughput) diff --git a/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp b/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp index 600fe5b7a18729..a2e6a9e0e0f19f 100644 --- a/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp +++ b/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp @@ -65,7 +65,7 @@ void DefaultResourceStrategy::used(uint64_t Mask) { ResourceState::ResourceState(const MCProcResourceDesc &Desc, unsigned Index, uint64_t Mask) : ProcResourceDescIndex(Index), ResourceMask(Mask), - BufferSize(Desc.BufferSize), IsAGroup(countPopulation(ResourceMask) > 1) { + BufferSize(Desc.BufferSize), IsAGroup(llvm::popcount(ResourceMask) > 1) { if (IsAGroup) { ResourceSizeMask = ResourceMask ^ 1ULL << getResourceStateIndex(ResourceMask); @@ -79,7 +79,7 @@ ResourceState::ResourceState(const MCProcResourceDesc &Desc, unsigned Index, bool ResourceState::isReady(unsigned NumUnits) const { return (!isReserved() || isADispatchHazard()) && - countPopulation(ReadyMask) >= NumUnits; + (unsigned)llvm::popcount(ReadyMask) >= NumUnits; } ResourceStateEvent ResourceState::isBufferAvailable() const { @@ -293,7 +293,7 @@ uint64_t ResourceManager::checkAvailability(const InstrDesc &Desc) const { } if (Desc.HasPartiallyOverlappingGroups && !RS.isAResourceGroup()) { - unsigned NumAvailableUnits = countPopulation(RS.getReadyMask()); + unsigned NumAvailableUnits = llvm::popcount(RS.getReadyMask()); NumAvailableUnits -= NumUnits; AvailableUnits[E.first] = NumAvailableUnits; if (!NumAvailableUnits) @@ -325,7 +325,7 @@ uint64_t ResourceManager::checkAvailability(const InstrDesc &Desc) const { auto it = AvailableUnits.find(ResourceMask); if (it == AvailableUnits.end()) { unsigned Index = getResourceStateIndex(ResourceMask); - unsigned NumUnits = countPopulation(Resources[Index]->getReadyMask()); + unsigned NumUnits = llvm::popcount(Resources[Index]->getReadyMask()); it = AvailableUnits.insert(std::make_pair(ResourceMask, NumUnits)).first; } @@ -362,7 +362,7 @@ void ResourceManager::issueInstruction( Pipes.emplace_back(std::pair( Pipe, ResourceCycles(CS.size()))); } else { - assert((countPopulation(R.first) > 1) && "Expected a group!"); + assert((llvm::popcount(R.first) > 1) && "Expected a group!"); // Mark this group as reserved. assert(R.second.isReserved()); reserveResource(R.first); @@ -379,7 +379,7 @@ void ResourceManager::cycleEvent(SmallVectorImpl &ResourcesFreed) { // Release this resource. const ResourceRef &RR = BR.first; - if (countPopulation(RR.first) == 1) + if (llvm::popcount(RR.first) == 1) release(RR); releaseResource(RR.first); ResourcesFreed.push_back(RR); diff --git a/llvm/lib/MCA/InstrBuilder.cpp b/llvm/lib/MCA/InstrBuilder.cpp index 5a2989ad7c03d0..19277f5f06b7da 100644 --- a/llvm/lib/MCA/InstrBuilder.cpp +++ b/llvm/lib/MCA/InstrBuilder.cpp @@ -102,8 +102,8 @@ static void initializeUsedResources(InstrDesc &ID, // Sort elements by mask popcount, so that we prioritize resource units over // resource groups, and smaller groups over larger groups. sort(Worklist, [](const ResourcePlusCycles &A, const ResourcePlusCycles &B) { - unsigned popcntA = countPopulation(A.first); - unsigned popcntB = countPopulation(B.first); + unsigned popcntA = llvm::popcount(A.first); + unsigned popcntB = llvm::popcount(B.first); if (popcntA < popcntB) return true; if (popcntA > popcntB) @@ -122,7 +122,7 @@ static void initializeUsedResources(InstrDesc &ID, for (unsigned I = 0, E = Worklist.size(); I < E; ++I) { ResourcePlusCycles &A = Worklist[I]; if (!A.second.size()) { - assert(countPopulation(A.first) > 1 && "Expected a group!"); + assert(llvm::popcount(A.first) > 1 && "Expected a group!"); UsedResourceGroups |= PowerOf2Floor(A.first); continue; } @@ -130,7 +130,7 @@ static void initializeUsedResources(InstrDesc &ID, ID.Resources.emplace_back(A); uint64_t NormalizedMask = A.first; - if (countPopulation(A.first) == 1) { + if (llvm::popcount(A.first) == 1) { UsedResourceUnits |= A.first; } else { // Remove the leading 1 from the resource group mask. @@ -146,7 +146,7 @@ static void initializeUsedResources(InstrDesc &ID, ResourcePlusCycles &B = Worklist[J]; if ((NormalizedMask & B.first) == NormalizedMask) { B.second.CS.subtract(A.second.size() - SuperResources[A.first]); - if (countPopulation(B.first) > 1) + if (llvm::popcount(B.first) > 1) B.second.NumUnits++; } } @@ -170,11 +170,11 @@ static void initializeUsedResources(InstrDesc &ID, // extra delay on top of the 2 cycles latency. // During those extra cycles, HWPort01 is not usable by other instructions. for (ResourcePlusCycles &RPC : ID.Resources) { - if (countPopulation(RPC.first) > 1 && !RPC.second.isReserved()) { + if (llvm::popcount(RPC.first) > 1 && !RPC.second.isReserved()) { // Remove the leading 1 from the resource group mask. uint64_t Mask = RPC.first ^ PowerOf2Floor(RPC.first); - uint64_t MaxResourceUnits = countPopulation(Mask); - if (RPC.second.NumUnits > countPopulation(Mask)) { + uint64_t MaxResourceUnits = llvm::popcount(Mask); + if (RPC.second.NumUnits > (unsigned)llvm::popcount(Mask)) { RPC.second.setReserved(); RPC.second.NumUnits = MaxResourceUnits; } diff --git a/llvm/lib/MCA/Stages/ExecuteStage.cpp b/llvm/lib/MCA/Stages/ExecuteStage.cpp index 369e2f5a4ef1ba..6d36c4aa353322 100644 --- a/llvm/lib/MCA/Stages/ExecuteStage.cpp +++ b/llvm/lib/MCA/Stages/ExecuteStage.cpp @@ -274,7 +274,7 @@ void ExecuteStage::notifyReservedOrReleasedBuffers(const InstRef &IR, if (!UsedBuffers) return; - SmallVector BufferIDs(countPopulation(UsedBuffers), 0); + SmallVector BufferIDs(llvm::popcount(UsedBuffers), 0); for (unsigned I = 0, E = BufferIDs.size(); I < E; ++I) { uint64_t CurrentBufferMask = UsedBuffers & (-UsedBuffers); BufferIDs[I] = HWS.getResourceID(CurrentBufferMask); diff --git a/llvm/lib/Support/APInt.cpp b/llvm/lib/Support/APInt.cpp index 1a2129a5617f5f..afe7478a8b2a5f 100644 --- a/llvm/lib/Support/APInt.cpp +++ b/llvm/lib/Support/APInt.cpp @@ -684,7 +684,7 @@ unsigned APInt::countTrailingOnesSlowCase() const { unsigned APInt::countPopulationSlowCase() const { unsigned Count = 0; for (unsigned i = 0; i < getNumWords(); ++i) - Count += llvm::countPopulation(U.pVal[i]); + Count += llvm::popcount(U.pVal[i]); return Count; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 658d40fc7682c1..0eb07bbc5dda51 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -2151,7 +2151,7 @@ void AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) { uint32_t MaskVal = Mask->getZExtValue(); if (isMask_32(MaskVal)) { - uint32_t WidthVal = countPopulation(MaskVal); + uint32_t WidthVal = llvm::popcount(MaskVal); ReplaceNode(N, getBFE32(false, SDLoc(N), Srl.getOperand(0), ShiftVal, WidthVal)); return; @@ -2172,7 +2172,7 @@ void AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) { uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal; if (isMask_32(MaskVal)) { - uint32_t WidthVal = countPopulation(MaskVal); + uint32_t WidthVal = llvm::popcount(MaskVal); ReplaceNode(N, getBFE32(false, SDLoc(N), And.getOperand(0), ShiftVal, WidthVal)); return; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp index 85b7cbc1d1ef16..62c3eec41836e3 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp @@ -1140,7 +1140,7 @@ static Value *simplifyAMDGCNMemoryIntrinsicDemanded(InstCombiner &IC, unsigned DMaskVal = DMask->getZExtValue() & 0xf; // Mask off values that are undefined because the dmask doesn't cover them - DemandedElts &= (1 << countPopulation(DMaskVal)) - 1; + DemandedElts &= (1 << llvm::popcount(DMaskVal)) - 1; unsigned NewDMaskVal = 0; unsigned OrigLoadIdx = 0; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 7da59414da22b8..2639f1f4556519 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -1807,7 +1807,7 @@ bool AMDGPUInstructionSelector::selectImageIntrinsic( } } else { DMask = MI.getOperand(ArgOffset + Intr->DMaskIndex).getImm(); - DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask); + DMaskLanes = BaseOpcode->Gather4 ? 4 : llvm::popcount(DMask); if (BaseOpcode->Store) { VDataIn = MI.getOperand(1).getReg(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 9fe27c4c207799..41cb0a99b420d8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -4906,7 +4906,7 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic( if (BaseOpcode->Gather4) { DMaskLanes = 4; } else if (DMask != 0) { - DMaskLanes = countPopulation(DMask); + DMaskLanes = llvm::popcount(DMask); } else if (!IsTFE && !BaseOpcode->Store) { // If dmask is 0, this is a no-op load. This can be eliminated. B.buildUndef(MI.getOperand(0)); diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 99479341e0d82b..f0cb7dbfd8d73b 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -3628,7 +3628,7 @@ bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst, bool IsPackedD16 = false; unsigned DataSize = - (Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : countPopulation(DMask); + (Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : llvm::popcount(DMask); if (hasPackedD16()) { int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16); IsPackedD16 = D16Idx >= 0; diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 89f37568e80c69..7659de6797e0ee 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -934,7 +934,7 @@ DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { } unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; - unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); + unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); if (D16 && AMDGPU::hasPackedD16(STI)) { diff --git a/llvm/lib/Target/AMDGPU/EvergreenInstructions.td b/llvm/lib/Target/AMDGPU/EvergreenInstructions.td index 3d4f8d52fdc692..3767dd0b6d478a 100644 --- a/llvm/lib/Target/AMDGPU/EvergreenInstructions.td +++ b/llvm/lib/Target/AMDGPU/EvergreenInstructions.td @@ -35,7 +35,7 @@ def IMMZeroBasedBitfieldMask : ImmLeaf ; def IMMPopCount : SDNodeXFormgetTargetConstant(countPopulation(N->getZExtValue()), SDLoc(N), + return CurDAG->getTargetConstant(llvm::popcount(N->getZExtValue()), SDLoc(N), MVT::i32); }]>; diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp index 0aaa2650e1299f..ff51304ac02e40 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -1454,17 +1454,14 @@ void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo, uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK; uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK; - if (AndMask == BITMASK_MAX && - OrMask == 0 && - countPopulation(XorMask) == 1) { + if (AndMask == BITMASK_MAX && OrMask == 0 && llvm::popcount(XorMask) == 1) { O << "swizzle(" << IdSymbolic[ID_SWAP]; O << ","; O << formatDec(XorMask); O << ")"; - } else if (AndMask == BITMASK_MAX && - OrMask == 0 && XorMask > 0 && + } else if (AndMask == BITMASK_MAX && OrMask == 0 && XorMask > 0 && isPowerOf2_64(XorMask + 1)) { O << "swizzle(" << IdSymbolic[ID_REVERSE]; diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 3889c70967b00e..e1d55714b37164 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1013,7 +1013,7 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, // IR type. Check the dmask for the real number of elements loaded. unsigned DMask = cast(CI.getArgOperand(0))->getZExtValue(); - MaxNumLanes = DMask == 0 ? 1 : countPopulation(DMask); + MaxNumLanes = DMask == 0 ? 1 : llvm::popcount(DMask); } } @@ -1028,7 +1028,7 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Type *DataTy = CI.getArgOperand(0)->getType(); if (RsrcIntr->IsImage) { unsigned DMask = cast(CI.getArgOperand(1))->getZExtValue(); - unsigned DMaskLanes = DMask == 0 ? 1 : countPopulation(DMask); + unsigned DMaskLanes = DMask == 0 ? 1 : llvm::popcount(DMask); Info.memVT = memVTFromLoadIntrData(DataTy, DMaskLanes); } else Info.memVT = EVT::getEVT(DataTy); @@ -6431,7 +6431,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op, auto *DMaskConst = cast(Op.getOperand(ArgOffset + Intr->DMaskIndex)); DMask = DMaskConst->getZExtValue(); - DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask); + DMaskLanes = BaseOpcode->Gather4 ? 4 : llvm::popcount(DMask); if (BaseOpcode->Store) { VData = Op.getOperand(2); @@ -9671,7 +9671,7 @@ SDValue SITargetLowering::performAndCombine(SDNode *N, // It can be optimized out using SDWA for GFX8+ in the SDWA peephole pass, // given that we are selecting 8 or 16 bit fields starting at byte boundary. uint64_t Mask = CRHS->getZExtValue(); - unsigned Bits = countPopulation(Mask); + unsigned Bits = llvm::popcount(Mask); if (getSubtarget()->hasSDWA() && LHS->getOpcode() == ISD::SRL && (Bits == 8 || Bits == 16) && isShiftedMask_64(Mask) && !(Mask & 1)) { if (auto *CShift = dyn_cast(LHS->getOperand(1))) { @@ -11744,7 +11744,7 @@ SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node, return Node; } - unsigned OldBitsSet = countPopulation(OldDmask); + unsigned OldBitsSet = llvm::popcount(OldDmask); // Work out which is the TFE/LWE lane if that is enabled. if (UsesTFC) { TFCLane = OldBitsSet; @@ -11808,7 +11808,7 @@ SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node, if (NewDmask == OldDmask) return Node; - unsigned BitsSet = countPopulation(NewDmask); + unsigned BitsSet = llvm::popcount(NewDmask); // Check for TFE or LWE - increase the number of channels by one to account // for the extra return value @@ -12052,7 +12052,7 @@ void SITargetLowering::AddIMGInit(MachineInstr &MI) const { unsigned dmask = MO_Dmask->getImm(); // Determine the number of active lanes taking into account the // Gather4 special case - unsigned ActiveLanes = TII->isGather4(MI) ? 4 : countPopulation(dmask); + unsigned ActiveLanes = TII->isGather4(MI) ? 4 : llvm::popcount(dmask); bool Packed = !Subtarget->hasUnpackedD16VMem(); diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 76347a3d230e3d..43e72e8b327a41 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -4350,7 +4350,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI, if (DMask) { uint64_t DMaskImm = DMask->getImm(); uint32_t RegCount = - isGather4(MI.getOpcode()) ? 4 : countPopulation(DMaskImm); + isGather4(MI.getOpcode()) ? 4 : llvm::popcount(DMaskImm); const MachineOperand *TFE = getNamedOperand(MI, AMDGPU::OpName::tfe); const MachineOperand *LWE = getNamedOperand(MI, AMDGPU::OpName::lwe); const MachineOperand *D16 = getNamedOperand(MI, AMDGPU::OpName::d16); diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index bfc801a5cd13b3..15c618ffe9958e 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -3140,7 +3140,7 @@ def IMMZeroBasedBitfieldMask : ImmLeaf ; def IMMPopCount : SDNodeXFormgetTargetConstant(countPopulation(N->getZExtValue()), SDLoc(N), + return CurDAG->getTargetConstant(llvm::popcount(N->getZExtValue()), SDLoc(N), MVT::i32); }]>; diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp index d881b0b0a775ee..2b5ca33b0e4f83 100644 --- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp @@ -323,7 +323,7 @@ static unsigned getOpcodeWidth(const MachineInstr &MI, const SIInstrInfo &TII) { if (TII.isMIMG(MI)) { uint64_t DMaskImm = TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); - return countPopulation(DMaskImm); + return llvm::popcount(DMaskImm); } if (TII.isMTBUF(Opc)) { return AMDGPU::getMTBUFElements(Opc); @@ -1784,7 +1784,7 @@ unsigned SILoadStoreOptimizer::getNewOpcode(const CombineInfo &CI, return AMDGPU::FLAT_STORE_DWORDX4; } case MIMG: - assert((countPopulation(CI.DMask | Paired.DMask) == Width) && + assert(((unsigned)llvm::popcount(CI.DMask | Paired.DMask) == Width) && "No overlaps"); return AMDGPU::getMaskedMIMGOp(CI.I->getOpcode(), Width); } @@ -1793,8 +1793,9 @@ unsigned SILoadStoreOptimizer::getNewOpcode(const CombineInfo &CI, std::pair SILoadStoreOptimizer::getSubRegIdxs(const CombineInfo &CI, const CombineInfo &Paired) { - assert((CI.InstClass != MIMG || (countPopulation(CI.DMask | Paired.DMask) == - CI.Width + Paired.Width)) && + assert((CI.InstClass != MIMG || + ((unsigned)llvm::popcount(CI.DMask | Paired.DMask) == + CI.Width + Paired.Width)) && "No overlaps"); unsigned Idx0; diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h index d864f7e867adc2..e9ddf82fb5c89f 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h @@ -362,7 +362,7 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo { uint64_t Even = Mask & 0xAAAAAAAAAAAAAAAAULL; Mask = (Even >> 1) | Mask; uint64_t Odd = Mask & 0x5555555555555555ULL; - return countPopulation(Odd); + return llvm::popcount(Odd); } // \returns a DWORD offset of a \p SubReg diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index c240b2462920c9..e08f64c3f7dd1f 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -1411,8 +1411,8 @@ class ARMOperand : public MCParsedAsmOperand { const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); - return Value > 0 && countPopulation((uint64_t)Value) == 1 && - Value >= Min && Value <= Max; + return Value > 0 && llvm::popcount((uint64_t)Value) == 1 && Value >= Min && + Value <= Max; } bool isModImm() const { return Kind == k_ModifiedImmediate; } @@ -7727,7 +7727,7 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst, // Conditions only allowing a 't' are those with no set bit except // the lowest-order one that indicates the end of the sequence. In // other words, powers of 2. - if (Cond == ARMCC::AL && countPopulation(Mask) != 1) + if (Cond == ARMCC::AL && llvm::popcount(Mask) != 1) return Error(Loc, "unpredictable IT predicate sequence"); break; } diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp index 6d70594174a372..020fb2d1dd167e 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp @@ -1968,7 +1968,7 @@ SmallVector HvxSelector::getPerfectCompletions(ShuffleMask SM, unsigned P = Sorted[I], Count = 1; while (++I != E && P == Sorted[I]) ++Count; - if (countPopulation(P) < Count) { + if ((unsigned)llvm::popcount(P) < Count) { // Reset all occurences of P, if there are more occurrences of P // than there are bits in P. for_each(Worklist, [P](unsigned &Q) { diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp index 536ef9b81d1b9e..5774cad0f102b8 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp @@ -48,7 +48,7 @@ class HexagonBid { public: HexagonBid() = default; - HexagonBid(unsigned B) { Bid = B ? MAX / countPopulation(B) : 0; } + HexagonBid(unsigned B) { Bid = B ? MAX / llvm::popcount(B) : 0; } // Check if the insn priority is overflowed. bool isSold() const { return (Bid >= MAX); } @@ -100,7 +100,7 @@ unsigned HexagonResource::setWeight(unsigned s) { if (Key == 0 || Units == 0 || (SlotWeight * s >= 32)) return Weight = 0; - unsigned Ctpop = countPopulation(Units); + unsigned Ctpop = llvm::popcount(Units); unsigned Cttz = countTrailingZeros(Units); Weight = (1u << (SlotWeight * s)) * ((MaskWeight - Ctpop) << Cttz); return Weight; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h index 66303cb7ac3cf9..10b01e75ace6e4 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h @@ -58,7 +58,7 @@ class HexagonResource { // Check if the resources are in ascending slot order. static bool lessUnits(const HexagonResource &A, const HexagonResource &B) { - return (countPopulation(A.getUnits()) < countPopulation(B.getUnits())); + return (llvm::popcount(A.getUnits()) < llvm::popcount(B.getUnits())); } // Check if the resources are in ascending weight order. diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp index 8ead0b927555d2..65e6d941fc5355 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp @@ -279,9 +279,9 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) { RISCVMatInt::InstSeq TmpSeq; generateInstSeqImpl(Lo, ActiveFeatures, TmpSeq); // Check if it is profitable to use BCLRI/BSETI. - if (Lo > 0 && TmpSeq.size() + countPopulation(Hi) < Res.size()) { + if (Lo > 0 && TmpSeq.size() + llvm::popcount(Hi) < Res.size()) { Opc = RISCV::BSETI; - } else if (Lo < 0 && TmpSeq.size() + countPopulation(~Hi) < Res.size()) { + } else if (Lo < 0 && TmpSeq.size() + llvm::popcount(~Hi) < Res.size()) { Opc = RISCV::BCLRI; Hi = ~Hi; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td index e4bea159e90bdf..1a0ad8098b436a 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td @@ -99,7 +99,7 @@ def BSETINVTwoBitsMask : PatLeaf<(imm), [{ if (isInt<12>(N->getSExtValue())) return false; // The immediate must have exactly two bits set. - return countPopulation(N->getZExtValue()) == 2; + return llvm::popcount(N->getZExtValue()) == 2; }]>; def BSETINVTwoBitsMaskHigh : SDNodeXForm(N->getSExtValue())) return false; // The immediate must have exactly two bits clear. - return countPopulation(N->getZExtValue()) == Subtarget->getXLen() - 2; + return (unsigned)llvm::popcount(N->getZExtValue()) == Subtarget->getXLen() - 2; }]>; def BCLRITwoBitsMaskLow : SDNodeXFormgetZExtValue(); - if (ByteVal == 0 || ByteVal == 255 ? - Bytes <= 16 && countPopulation(Bytes) <= 2 : - Bytes <= 4) { + if (ByteVal == 0 || ByteVal == 255 + ? Bytes <= 16 && llvm::popcount(Bytes) <= 2 + : Bytes <= 4) { unsigned Size1 = Bytes == 16 ? 8 : 1 << findLastSet(Bytes); unsigned Size2 = Bytes - Size1; SDValue Chain1 = memsetStore(DAG, DL, Chain, Dst, ByteVal, Size1, diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp index 33f5bb365da8f6..699e83c6fe1e28 100644 --- a/llvm/lib/Target/X86/X86FloatingPoint.cpp +++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp @@ -973,7 +973,7 @@ void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) { // Now we should have the correct registers live. LLVM_DEBUG(dumpStack()); - assert(StackTop == countPopulation(Mask) && "Live count mismatch"); + assert(StackTop == (unsigned)llvm::popcount(Mask) && "Live count mismatch"); } /// shuffleStackTop - emit fxch instructions before I to shuffle the top diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 6512658701d8cf..d69e2c3ed4930f 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -3831,7 +3831,7 @@ MachineSDNode *X86DAGToDAGISel::matchBEXTRFromAndImm(SDNode *Node) { return nullptr; uint64_t Shift = ShiftCst->getZExtValue(); - uint64_t MaskSize = countPopulation(Mask); + uint64_t MaskSize = llvm::popcount(Mask); // Don't interfere with something that can be handled by extracting AH. // TODO: If we are able to fold a load, BEXTR might still be better than AH. diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 8ffc494501b2e5..3339ac943c1e68 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -11718,7 +11718,7 @@ static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op, return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); } - assert(countPopulation(NonZeros) == 2 && "Simple cases not handled?"); + assert(llvm::popcount(NonZeros) == 2 && "Simple cases not handled?"); if (ResVT.getVectorNumElements() >= 16) return Op; // The operation is legal with KUNPCK diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index b7f0076f24ac7a..e804122adae368 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -2095,7 +2095,7 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, // We can commute insertps if we zero 2 of the elements, the insertion is // "inline" and we don't override the insertion with a zero. if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 && - countPopulation(ZMask) == 2) { + llvm::popcount(ZMask) == 2) { unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15); assert(AltIdx < 4 && "Illegal insertion index"); unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask; diff --git a/llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp b/llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp index 024e511ce7ea45..6ed327fc0c8f07 100644 --- a/llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp +++ b/llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp @@ -69,8 +69,8 @@ getNonRedundantWriteProcRes(const MCSchedClassDesc &SCDesc, } sort(ResourceMaskAndEntries, [](const ResourceMaskAndEntry &A, const ResourceMaskAndEntry &B) { - unsigned popcntA = countPopulation(A.first); - unsigned popcntB = countPopulation(B.first); + unsigned popcntA = llvm::popcount(A.first); + unsigned popcntB = llvm::popcount(B.first); if (popcntA < popcntB) return true; if (popcntA > popcntB) diff --git a/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp b/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp index 88418e21b0e4e9..ef77d4b2fd224b 100644 --- a/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp +++ b/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp @@ -1248,7 +1248,7 @@ bool Decoder::dumpPackedEntry(const object::COFFObjectFile &COFF, } if (RF.C()) { // Count the number of registers pushed below R11 - int FpOffset = 4 * countPopulation(GPRMask & ((1U << 11) - 1)); + int FpOffset = 4 * llvm::popcount(GPRMask & ((1U << 11) - 1)); if (FpOffset) SW.startLine() << "add.w r11, sp, #" << FpOffset << "\n"; else diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.h b/llvm/utils/TableGen/CodeGenDAGPatterns.h index 83ac7173441e61..63e2e4db2dd504 100644 --- a/llvm/utils/TableGen/CodeGenDAGPatterns.h +++ b/llvm/utils/TableGen/CodeGenDAGPatterns.h @@ -69,7 +69,7 @@ struct MachineValueTypeSet { unsigned size() const { unsigned Count = 0; for (WordType W : Words) - Count += countPopulation(W); + Count += llvm::popcount(W); return Count; } LLVM_ATTRIBUTE_ALWAYS_INLINE diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp index 7b9f9e41f5e85f..5e7a7feb113c7d 100644 --- a/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp +++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp @@ -569,8 +569,8 @@ verifyMemorySemantics(Operation *op, spirv::MemorySemantics memorySemantics) { spirv::MemorySemantics::AcquireRelease | spirv::MemorySemantics::SequentiallyConsistent; - auto bitCount = llvm::countPopulation( - static_cast(memorySemantics & atMostOneInSet)); + auto bitCount = + llvm::popcount(static_cast(memorySemantics & atMostOneInSet)); if (bitCount > 1) { return op->emitError( "expected at most one of these four memory constraints " diff --git a/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp b/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp index 4f2b57f9872b5c..7489c3134fc73e 100644 --- a/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp +++ b/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp @@ -397,7 +397,7 @@ static void emitAvailabilityQueryForBitEnum(const Record &enumDef, enumName); os << formatv( - " assert(::llvm::countPopulation(static_cast<{0}>(value)) <= 1" + " assert(::llvm::popcount(static_cast<{0}>(value)) <= 1" " && \"cannot have more than one bit set\");\n", underlyingType);