diff --git a/llvm/lib/CodeGen/CFIInstrInserter.cpp b/llvm/lib/CodeGen/CFIInstrInserter.cpp index 42523c47a671c..842339a1a6858 100644 --- a/llvm/lib/CodeGen/CFIInstrInserter.cpp +++ b/llvm/lib/CodeGen/CFIInstrInserter.cpp @@ -148,7 +148,7 @@ void CFIInstrInserter::calculateCFAInfo(MachineFunction &MF) { MF.getSubtarget().getFrameLowering()->getInitialCFAOffset(MF); // Initial CFA register value i.e. the one valid at the beginning of the // function. - unsigned InitialRegister = + Register InitialRegister = MF.getSubtarget().getFrameLowering()->getInitialCFARegister(MF); const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); unsigned NumRegs = TRI.getNumRegs(); diff --git a/llvm/lib/CodeGen/DetectDeadLanes.cpp b/llvm/lib/CodeGen/DetectDeadLanes.cpp index 565c8b405f828..f5c25232dc6f3 100644 --- a/llvm/lib/CodeGen/DetectDeadLanes.cpp +++ b/llvm/lib/CodeGen/DetectDeadLanes.cpp @@ -488,7 +488,7 @@ std::pair DetectDeadLanes::runOnce(MachineFunction &MF) { // First pass: Populate defs/uses of vregs with initial values unsigned NumVirtRegs = MRI->getNumVirtRegs(); for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { - unsigned Reg = Register::index2VirtReg(RegIdx); + Register Reg = Register::index2VirtReg(RegIdx); // Determine used/defined lanes and add copy instructions to worklist. VRegInfo &Info = VRegInfos[RegIdx]; @@ -502,7 +502,7 @@ std::pair DetectDeadLanes::runOnce(MachineFunction &MF) { Worklist.pop_front(); WorklistMembers.reset(RegIdx); VRegInfo &Info = VRegInfos[RegIdx]; - unsigned Reg = Register::index2VirtReg(RegIdx); + Register Reg = Register::index2VirtReg(RegIdx); // Transfer UsedLanes to operands of DefMI (backwards dataflow). MachineOperand &Def = *MRI->def_begin(Reg); @@ -516,7 +516,7 @@ std::pair DetectDeadLanes::runOnce(MachineFunction &MF) { LLVM_DEBUG({ dbgs() << "Defined/Used lanes:\n"; for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { - unsigned Reg = Register::index2VirtReg(RegIdx); + Register Reg = Register::index2VirtReg(RegIdx); const VRegInfo &Info = VRegInfos[RegIdx]; dbgs() << printReg(Reg, nullptr) << " Used: " << PrintLaneMask(Info.UsedLanes) diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp index 14b8a141af437..9248bd7cf7c50 100644 --- a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp @@ -248,7 +248,7 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) { // that the size of the now-constrained vreg is unchanged and that it has a // register class. for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) { - unsigned VReg = Register::index2VirtReg(I); + Register VReg = Register::index2VirtReg(I); MachineInstr *MI = nullptr; if (!MRI.def_empty(VReg)) diff --git a/llvm/lib/CodeGen/LiveIntervalCalc.cpp b/llvm/lib/CodeGen/LiveIntervalCalc.cpp index 3176d73b35f61..ccc5ae98086e5 100644 --- a/llvm/lib/CodeGen/LiveIntervalCalc.cpp +++ b/llvm/lib/CodeGen/LiveIntervalCalc.cpp @@ -51,7 +51,7 @@ void LiveIntervalCalc::calculate(LiveInterval &LI, bool TrackSubRegs) { // Visit all def operands. If the same instruction has multiple defs of Reg, // createDeadDef() will deduplicate. const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo(); - unsigned Reg = LI.reg(); + Register Reg = LI.reg(); for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) { if (!MO.isDef() && !MO.readsReg()) continue; diff --git a/llvm/lib/CodeGen/LiveRangeEdit.cpp b/llvm/lib/CodeGen/LiveRangeEdit.cpp index afc04f0045c26..45dfbf114f464 100644 --- a/llvm/lib/CodeGen/LiveRangeEdit.cpp +++ b/llvm/lib/CodeGen/LiveRangeEdit.cpp @@ -318,7 +318,7 @@ void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink) { MI->getDesc().getNumDefs() == 1) { Dest = MI->getOperand(0).getReg(); DestSubReg = MI->getOperand(0).getSubReg(); - unsigned Original = VRM->getOriginal(Dest); + Register Original = VRM->getOriginal(Dest); LiveInterval &OrigLI = LIS.getInterval(Original); VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx); // The original live-range may have been shrunk to @@ -448,7 +448,7 @@ void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl &Dead, LiveInterval *LI = ToShrink.pop_back_val(); if (foldAsLoad(LI, Dead)) continue; - unsigned VReg = LI->reg(); + Register VReg = LI->reg(); if (TheDelegate) TheDelegate->LRE_WillShrinkVirtReg(VReg); if (!LIS.shrinkToUses(LI, &Dead)) diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index a4a114473c3d8..fa29c5667cdaa 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -306,13 +306,13 @@ void MIRPrinter::convert(yaml::MachineFunction &MF, // Print the virtual register definitions. for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) { - unsigned Reg = Register::index2VirtReg(I); + Register Reg = Register::index2VirtReg(I); yaml::VirtualRegisterDefinition VReg; VReg.ID = I; if (RegInfo.getVRegName(Reg) != "") continue; ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI); - unsigned PreferredReg = RegInfo.getSimpleHint(Reg); + Register PreferredReg = RegInfo.getSimpleHint(Reg); if (PreferredReg) printRegMIR(PreferredReg, VReg.PreferredRegister, TRI); MF.VirtualRegisters.push_back(VReg); diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp index 7709095cd6836..b205b9601fd04 100644 --- a/llvm/lib/CodeGen/PHIElimination.cpp +++ b/llvm/lib/CodeGen/PHIElimination.cpp @@ -161,7 +161,7 @@ bool PHIElimination::runOnMachineFunction(MachineFunction &MF) { for (unsigned Index = 0, e = MRI->getNumVirtRegs(); Index != e; ++Index) { // Set the bit for this register for each MBB where it is // live-through or live-in (killed). - unsigned VirtReg = Register::index2VirtReg(Index); + Register VirtReg = Register::index2VirtReg(Index); MachineInstr *DefMI = MRI->getVRegDef(VirtReg); if (!DefMI) continue; diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp index 466022ae0ac14..05bbd1a2d03bf 100644 --- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp +++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp @@ -130,7 +130,7 @@ bool RenameIndependentSubregs::renameComponents(LiveInterval &LI) const { return false; // Create a new VReg for each class. - unsigned Reg = LI.reg(); + Register Reg = LI.reg(); const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); SmallVector Intervals; Intervals.push_back(&LI); @@ -175,7 +175,7 @@ bool RenameIndependentSubregs::findComponents(IntEqClasses &Classes, // across subranges when they are affected by the same MachineOperand. const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo(); Classes.grow(NumComponents); - unsigned Reg = LI.reg(); + Register Reg = LI.reg(); for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) { if (!MO.isDef() && !MO.readsReg()) continue; @@ -304,7 +304,7 @@ void RenameIndependentSubregs::computeMainRangesFixFlags( const SlotIndexes &Indexes = *LIS->getSlotIndexes(); for (size_t I = 0, E = Intervals.size(); I < E; ++I) { LiveInterval &LI = *Intervals[I]; - unsigned Reg = LI.reg(); + Register Reg = LI.reg(); LI.removeEmptySubRanges(); @@ -391,7 +391,7 @@ bool RenameIndependentSubregs::runOnMachineFunction(MachineFunction &MF) { // there can't be any further splitting. bool Changed = false; for (size_t I = 0, E = MRI->getNumVirtRegs(); I < E; ++I) { - unsigned Reg = Register::index2VirtReg(I); + Register Reg = Register::index2VirtReg(I); if (!LIS->hasInterval(Reg)) continue; LiveInterval &LI = LIS->getInterval(Reg); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 1e38a999cda3c..bb4dd41097e09 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -1703,7 +1703,7 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { // If this is an instruction which fast-isel has deferred, select it now. if (const Instruction *Inst = dyn_cast(V)) { - unsigned InReg = FuncInfo.InitializeRegForValue(Inst); + Register InReg = FuncInfo.InitializeRegForValue(Inst); RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg, Inst->getType(), std::nullopt); @@ -2115,7 +2115,7 @@ void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { // Already exported? if (FuncInfo.isExportedInst(V)) return; - unsigned Reg = FuncInfo.InitializeRegForValue(V); + Register Reg = FuncInfo.InitializeRegForValue(V); CopyValueToVirtualRegister(V, Reg); } diff --git a/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp index 8e0c4c6f79707..f93bc40b744b7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp @@ -1147,7 +1147,7 @@ SelectionDAGBuilder::LowerStatepoint(const GCStatepointInst &I, // TODO: To eliminate this problem we can remove gc.result intrinsics // completely and make statepoint call to return a tuple. Type *RetTy = GCResultLocality.second->getType(); - unsigned Reg = FuncInfo.CreateRegs(RetTy); + Register Reg = FuncInfo.CreateRegs(RetTy); RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), DAG.getDataLayout(), Reg, RetTy, I.getCallingConv()); diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp index 2ae85c86a9486..5c9a6ebe8b7e9 100644 --- a/llvm/lib/CodeGen/SplitKit.cpp +++ b/llvm/lib/CodeGen/SplitKit.cpp @@ -323,7 +323,7 @@ unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const { } bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const { - unsigned OrigReg = VRM.getOriginal(CurLI->reg()); + Register OrigReg = VRM.getOriginal(CurLI->reg()); const LiveInterval &Orig = LIS.getInterval(OrigReg); assert(!Orig.empty() && "Splitting empty interval?"); LiveInterval::const_iterator I = Orig.find(Idx); @@ -590,7 +590,7 @@ VNInfo *SplitEditor::defFromParent(unsigned RegIdx, const VNInfo *ParentVNI, bool Late = RegIdx != 0; // Attempt cheap-as-a-copy rematerialization. - unsigned Original = VRM.getOriginal(Edit->get(RegIdx)); + Register Original = VRM.getOriginal(Edit->get(RegIdx)); LiveInterval &OrigLI = LIS.getInterval(Original); VNInfo *OrigVNI = OrigLI.getVNInfoAt(UseIdx); diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp index 069aca742da07..01db94495579e 100644 --- a/llvm/lib/CodeGen/VirtRegMap.cpp +++ b/llvm/lib/CodeGen/VirtRegMap.cpp @@ -145,7 +145,7 @@ void VirtRegMap::assignVirt2StackSlot(Register virtReg, int SS) { void VirtRegMap::print(raw_ostream &OS, const Module*) const { OS << "********** REGISTER MAP **********\n"; for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { - unsigned Reg = Register::index2VirtReg(i); + Register Reg = Register::index2VirtReg(i); if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) { OS << '[' << printReg(Reg, TRI) << " -> " << printReg(Virt2PhysMap[Reg], TRI) << "] " @@ -154,7 +154,7 @@ void VirtRegMap::print(raw_ostream &OS, const Module*) const { } for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { - unsigned Reg = Register::index2VirtReg(i); + Register Reg = Register::index2VirtReg(i); if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) { OS << '[' << printReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index b94630295103a..6f8b96c6dc2e5 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -6717,7 +6717,7 @@ MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall( const ARMFunctionInfo &AFI = *C.getMF()->getInfo(); // Can we save to a register? if (C.CallConstructionID == MachineOutlinerRegSave) { - unsigned Reg = findRegisterToSaveLRTo(C); + Register Reg = findRegisterToSaveLRTo(C); assert(Reg != 0 && "No callee-saved register available?"); // Save and restore LR from that register. diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index ca96fdbc03deb..0c6d3a2ea4339 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -5450,7 +5450,7 @@ PPCInstrInfo::isSignOrZeroExtended(const unsigned Reg, case PPC::XORI: case PPC::ORI8: case PPC::XORI8: { - unsigned SrcReg = MI->getOperand(1).getReg(); + Register SrcReg = MI->getOperand(1).getReg(); auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI); return std::pair(SrcExt.first || IsSExt, SrcExt.second || IsZExt); @@ -5464,7 +5464,7 @@ PPCInstrInfo::isSignOrZeroExtended(const unsigned Reg, case PPC::XORIS: case PPC::ORIS8: case PPC::XORIS8: { - unsigned SrcReg = MI->getOperand(1).getReg(); + Register SrcReg = MI->getOperand(1).getReg(); auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI); uint16_t Imm = MI->getOperand(2).getImm(); if (Imm & 0x8000) @@ -5497,7 +5497,7 @@ PPCInstrInfo::isSignOrZeroExtended(const unsigned Reg, if (!MI->getOperand(I).isReg()) return std::pair(false, false); - unsigned SrcReg = MI->getOperand(I).getReg(); + Register SrcReg = MI->getOperand(I).getReg(); auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth + 1, MRI); IsSExt &= SrcExt.first; IsZExt &= SrcExt.second; @@ -5513,8 +5513,8 @@ PPCInstrInfo::isSignOrZeroExtended(const unsigned Reg, if (BinOpDepth >= MAX_BINOP_DEPTH) return std::pair(false, false); - unsigned SrcReg1 = MI->getOperand(1).getReg(); - unsigned SrcReg2 = MI->getOperand(2).getReg(); + Register SrcReg1 = MI->getOperand(1).getReg(); + Register SrcReg2 = MI->getOperand(2).getReg(); auto Src1Ext = isSignOrZeroExtended(SrcReg1, BinOpDepth + 1, MRI); auto Src2Ext = isSignOrZeroExtended(SrcReg2, BinOpDepth + 1, MRI); return std::pair(Src1Ext.first && Src2Ext.first, diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp index 4f3750c15cfdc..542ed2a347280 100644 --- a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp +++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp @@ -736,7 +736,7 @@ TEST_F(AArch64GISelMITest, WidenUADDO) { LLT s8{LLT::scalar(8)}; LLT s16{LLT::scalar(16)}; auto MIBTrunc = B.buildTrunc(s8, Copies[0]); - unsigned CarryReg = MRI->createGenericVirtualRegister(LLT::scalar(1)); + Register CarryReg = MRI->createGenericVirtualRegister(LLT::scalar(1)); auto MIBUAddO = B.buildInstr(TargetOpcode::G_UADDO, {s8, CarryReg}, {MIBTrunc, MIBTrunc}); AInfo Info(MF->getSubtarget()); @@ -775,7 +775,7 @@ TEST_F(AArch64GISelMITest, WidenUSUBO) { LLT s8{LLT::scalar(8)}; LLT s16{LLT::scalar(16)}; auto MIBTrunc = B.buildTrunc(s8, Copies[0]); - unsigned CarryReg = MRI->createGenericVirtualRegister(LLT::scalar(1)); + Register CarryReg = MRI->createGenericVirtualRegister(LLT::scalar(1)); auto MIBUSUBO = B.buildInstr(TargetOpcode::G_USUBO, {s8, CarryReg}, {MIBTrunc, MIBTrunc}); AInfo Info(MF->getSubtarget()); @@ -814,7 +814,7 @@ TEST_F(AArch64GISelMITest, WidenSADDO) { LLT s8{LLT::scalar(8)}; LLT s16{LLT::scalar(16)}; auto MIBTrunc = B.buildTrunc(s8, Copies[0]); - unsigned CarryReg = MRI->createGenericVirtualRegister(LLT::scalar(1)); + Register CarryReg = MRI->createGenericVirtualRegister(LLT::scalar(1)); auto MIBSAddO = B.buildInstr(TargetOpcode::G_SADDO, {s8, CarryReg}, {MIBTrunc, MIBTrunc}); AInfo Info(MF->getSubtarget()); @@ -853,7 +853,7 @@ TEST_F(AArch64GISelMITest, WidenSSUBO) { LLT s8{LLT::scalar(8)}; LLT s16{LLT::scalar(16)}; auto MIBTrunc = B.buildTrunc(s8, Copies[0]); - unsigned CarryReg = MRI->createGenericVirtualRegister(LLT::scalar(1)); + Register CarryReg = MRI->createGenericVirtualRegister(LLT::scalar(1)); auto MIBSSUBO = B.buildInstr(TargetOpcode::G_SSUBO, {s8, CarryReg}, {MIBTrunc, MIBTrunc}); AInfo Info(MF->getSubtarget());