From cdf53e333c9dda94c43cda57b0892f7ec2c16e57 Mon Sep 17 00:00:00 2001
From: Guy Blank <guy.blank@intel.com>
Date: Thu, 24 Nov 2016 06:52:24 +0000
Subject: [PATCH] merge r276347

[X86] Do not use AND8ri8 in AVX512 pattern

This variant is (as documented in the TD) for disassembler use only, and should
not be used in patterns - it is longer, and is broken on 64-bit.

llvm-svn: 287855
---
 llvm/lib/Target/X86/X86InstrAVX512.td |  2 +-
 llvm/test/CodeGen/X86/no-and8ri8.ll   | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/X86/no-and8ri8.ll

diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index de4129f865417..803a7e35c2091 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -2124,7 +2124,7 @@ let Predicates = [HasAVX512] in {
             (COPY_TO_REGCLASS (i16 (EXTRACT_SUBREG $src, sub_16bit)), VK1)>;
 
   def : Pat<(i1 (trunc (i8 GR8:$src))),
-            (COPY_TO_REGCLASS (i16 (SUBREG_TO_REG (i64 0), (AND8ri8 $src, (i8 1)),
+            (COPY_TO_REGCLASS (i16 (SUBREG_TO_REG (i64 0), (AND8ri $src, (i8 1)),
                                     sub_8bit)), VK1)>;
 
   def : Pat<(i1 (trunc (i8 (assertzext_i1 GR8:$src)))),
diff --git a/llvm/test/CodeGen/X86/no-and8ri8.ll b/llvm/test/CodeGen/X86/no-and8ri8.ll
new file mode 100644
index 0000000000000..57f33226602ef
--- /dev/null
+++ b/llvm/test/CodeGen/X86/no-and8ri8.ll
@@ -0,0 +1,18 @@
+; RUN: llc -mtriple=x86_64-pc-linux -mattr=+avx512f --show-mc-encoding < %s | FileCheck %s
+
+declare i1 @bar() 
+
+; CHECK-LABEL: @foo
+; CHECK-NOT: andb {{.*}} # encoding: [0x82,
+define i1 @foo(i1 %i) nounwind {
+entry:
+  br i1 %i, label %if, label %else
+
+if:
+  %r = call i1 @bar()
+  br label %else
+
+else:
+  %ret = phi i1 [%r, %if], [true, %entry]
+  ret i1 %ret
+}