diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index be167d674619c..59a04f3167d86 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -947,11 +947,11 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
   default:
     llvm_unreachable("Unexpected form in emitVEXOpcodePrefix!");
   case X86II::MRMDestMem4VOp3CC: {
-    //  MemAddr, src1(ModR/M), src2(VEX_4V)
+    //  src1(ModR/M), MemAddr, src2(VEX_4V)
+    Prefix.setR(MI, CurOp++);
     Prefix.setB(MI, MemOperand + X86::AddrBaseReg);
     Prefix.setX(MI, MemOperand + X86::AddrIndexReg);
     CurOp += X86::AddrNumOperands;
-    Prefix.setR(MI, ++CurOp);
     Prefix.set4V(MI, CurOp++);
     break;
   }
diff --git a/llvm/test/MC/Disassembler/X86/cmpccxadd-64.txt b/llvm/test/MC/Disassembler/X86/cmpccxadd-64.txt
index c562ffb535956..62420db37f40d 100644
--- a/llvm/test/MC/Disassembler/X86/cmpccxadd-64.txt
+++ b/llvm/test/MC/Disassembler/X86/cmpccxadd-64.txt
@@ -769,3 +769,7 @@
 # INTEL: cmpzxadd qword ptr [rdx - 1024], r9, r10
 0xc4,0x62,0xa9,0xe4,0x8a,0x00,0xfc,0xff,0xff
 
+# ATT:   cmpbexadd  %ecx, %r8d, (%rip)
+# INTEL: cmpbexadd dword ptr [rip], r8d, ecx
+0xc4,0x62,0x71,0xe6,0x05,0x00,0x00,0x00,0x00
+
diff --git a/llvm/test/MC/X86/cmpccxadd-att-64.s b/llvm/test/MC/X86/cmpccxadd-att-64.s
index a18733d4ef895..2ef49cba92e32 100644
--- a/llvm/test/MC/X86/cmpccxadd-att-64.s
+++ b/llvm/test/MC/X86/cmpccxadd-att-64.s
@@ -768,3 +768,6 @@
 // CHECK: encoding: [0xc4,0x62,0xa9,0xe4,0x8a,0x00,0xfc,0xff,0xff]
           cmpzxadd  %r10, %r9, -1024(%rdx)
 
+// CHECK: cmpbexadd  %ecx, %r8d, (%rip)
+// CHECK: encoding: [0xc4,0x62,0x71,0xe6,0x05,0x00,0x00,0x00,0x00]
+          cmpbexadd  %ecx, %r8d, (%rip)
diff --git a/llvm/test/MC/X86/cmpccxadd-intel-64.s b/llvm/test/MC/X86/cmpccxadd-intel-64.s
index 1a2d638281eec..c03873e34dece 100644
--- a/llvm/test/MC/X86/cmpccxadd-intel-64.s
+++ b/llvm/test/MC/X86/cmpccxadd-intel-64.s
@@ -768,3 +768,6 @@
 // CHECK: encoding: [0xc4,0x62,0xa9,0xe4,0x8a,0x00,0xfc,0xff,0xff]
           cmpzxadd qword ptr [rdx - 1024], r9, r10
 
+// CHECK: cmpbexadd dword ptr [rip], r8d, ecx
+// CHECK: encoding: [0xc4,0x62,0x71,0xe6,0x05,0x00,0x00,0x00,0x00]
+          cmpbexadd dword ptr [rip], r8d, ecx