diff --git a/llvm/test/Transforms/IndVarSimplify/X86/widening-vs-and-elimination.ll b/llvm/test/Transforms/IndVarSimplify/X86/widening-vs-and-elimination.ll
new file mode 100644
index 00000000000000..9b8ef313a3c5e8
--- /dev/null
+++ b/llvm/test/Transforms/IndVarSimplify/X86/widening-vs-and-elimination.ll
@@ -0,0 +1,68 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -passes=indvars < %s | FileCheck %s --check-prefixes=WIDENING_ON
+; RUN: opt -S -passes=indvars -indvars-widen-indvars=false < %s | FileCheck %s --check-prefixes=WIDENING_OFF
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @test(ptr %p1, ptr %p2) {
+; WIDENING_ON-LABEL: @test(
+; WIDENING_ON-NEXT:  bb:
+; WIDENING_ON-NEXT:    [[VAR:%.*]] = load atomic i32, ptr [[P1:%.*]] unordered, align 8
+; WIDENING_ON-NEXT:    [[VAR1:%.*]] = load atomic i32, ptr [[P2:%.*]] unordered, align 8
+; WIDENING_ON-NEXT:    [[TMP0:%.*]] = zext i32 [[VAR]] to i64
+; WIDENING_ON-NEXT:    br label [[BB2:%.*]]
+; WIDENING_ON:       bb2:
+; WIDENING_ON-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[BB8:%.*]] ], [ [[TMP0]], [[BB:%.*]] ]
+; WIDENING_ON-NEXT:    [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV]], -1
+; WIDENING_ON-NEXT:    [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], -1
+; WIDENING_ON-NEXT:    [[VAR5:%.*]] = icmp ne i64 [[INDVARS_IV]], 0
+; WIDENING_ON-NEXT:    [[TMP2:%.*]] = zext i32 [[VAR1]] to i64
+; WIDENING_ON-NEXT:    [[VAR6_WIDE:%.*]] = icmp ult i64 [[TMP1]], [[TMP2]]
+; WIDENING_ON-NEXT:    [[VAR7:%.*]] = and i1 [[VAR5]], [[VAR6_WIDE]]
+; WIDENING_ON-NEXT:    br i1 [[VAR7]], label [[BB8]], label [[BB11:%.*]]
+; WIDENING_ON:       bb8:
+; WIDENING_ON-NEXT:    br label [[BB2]]
+; WIDENING_ON:       bb11:
+; WIDENING_ON-NEXT:    ret void
+;
+; WIDENING_OFF-LABEL: @test(
+; WIDENING_OFF-NEXT:  bb:
+; WIDENING_OFF-NEXT:    [[VAR:%.*]] = load atomic i32, ptr [[P1:%.*]] unordered, align 8
+; WIDENING_OFF-NEXT:    [[VAR1:%.*]] = load atomic i32, ptr [[P2:%.*]] unordered, align 8
+; WIDENING_OFF-NEXT:    br label [[BB2:%.*]]
+; WIDENING_OFF:       bb2:
+; WIDENING_OFF-NEXT:    [[VAR3:%.*]] = phi i32 [ [[VAR4:%.*]], [[BB8:%.*]] ], [ [[VAR]], [[BB:%.*]] ]
+; WIDENING_OFF-NEXT:    [[VAR4]] = add i32 [[VAR3]], -1
+; WIDENING_OFF-NEXT:    [[VAR5:%.*]] = icmp ne i32 [[VAR3]], 0
+; WIDENING_OFF-NEXT:    [[VAR6:%.*]] = icmp ult i32 [[VAR4]], [[VAR1]]
+; WIDENING_OFF-NEXT:    [[VAR7:%.*]] = and i1 [[VAR5]], [[VAR6]]
+; WIDENING_OFF-NEXT:    br i1 [[VAR7]], label [[BB8]], label [[BB11:%.*]]
+; WIDENING_OFF:       bb8:
+; WIDENING_OFF-NEXT:    [[VAR9:%.*]] = zext i32 [[VAR4]] to i64
+; WIDENING_OFF-NEXT:    [[VAR10:%.*]] = getelementptr inbounds i32, ptr addrspace(1) poison, i64 [[VAR9]]
+; WIDENING_OFF-NEXT:    br label [[BB2]]
+; WIDENING_OFF:       bb11:
+; WIDENING_OFF-NEXT:    ret void
+;
+bb:
+  %var = load atomic i32, ptr %p1 unordered, align 8
+  %var1 = load atomic i32, ptr %p2 unordered, align 8
+  br label %bb2
+
+bb2:                                              ; preds = %bb8, %bb
+  %var3 = phi i32 [ %var4, %bb8 ], [ %var, %bb ]
+  %var4 = add i32 %var3, -1
+  %var5 = icmp ne i32 %var3, 0
+  %var6 = icmp ult i32 %var4, %var1
+  %var7 = and i1 %var5, %var6
+  br i1 %var7, label %bb8, label %bb11
+
+bb8:                                              ; preds = %bb2
+  %var9 = zext i32 %var4 to i64
+  %var10 = getelementptr inbounds i32, ptr addrspace(1) poison, i64 %var9
+  br label %bb2
+
+bb11:                                             ; preds = %bb2
+  ret void
+}