diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index eb603f16988b5..b9f175c275286 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -140,10 +140,6 @@ static inline unsigned getFormat(uint64_t TSFlags) {
 static inline VLMUL getLMul(uint64_t TSFlags) {
   return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
 }
-/// \returns true if there is a dummy mask operand for the instruction.
-static inline bool hasDummyMaskOp(uint64_t TSFlags) {
-  return TSFlags & HasDummyMaskOpMask;
-}
 /// \returns true if tail agnostic is enforced for the instruction.
 static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
   return TSFlags & ForceTailAgnosticMask;
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 0ce8f05ed5976..4d9fc4bc4c87c 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -630,9 +630,8 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
   const MachineFunction *MF = MBB->getParent();
   assert(MF && "MBB expected to be in a machine function");
 
-  const TargetRegisterInfo *TRI =
-      MF->getSubtarget<RISCVSubtarget>().getRegisterInfo();
-
+  const RISCVSubtarget &Subtarget = MF->getSubtarget<RISCVSubtarget>();
+  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
   assert(TRI && "TargetRegisterInfo expected");
 
   uint64_t TSFlags = MI->getDesc().TSFlags;
@@ -705,9 +704,16 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
 
   // Unmasked pseudo instructions need to append dummy mask operand to
   // V instructions. All V instructions are modeled as the masked version.
-  if (RISCVII::hasDummyMaskOp(TSFlags))
+  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
+  const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
+  if (OutMI.getNumOperands() < OutMCID.getNumOperands()) {
+    assert(OutMCID.operands()[OutMI.getNumOperands()].RegClass ==
+               RISCV::VMV0RegClassID &&
+           "Expected only mask operand to be missing");
     OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));
+  }
 
+  assert(OutMI.getNumOperands() == OutMCID.getNumOperands());
   return true;
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index a27cb80a9f9d8..d857e35a57b5b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3207,16 +3207,13 @@ bool RISCVDAGToDAGISel::doPeepholeMaskedRVV(SDNode *N) {
 
   unsigned Opc = UseTUPseudo ? I->UnmaskedTUPseudo : I->UnmaskedPseudo;
 
-  // Check that we're dropping the mask operand and any policy operand
-  // when we transform to this unmasked pseudo. Additionally, if this
-  // instruction is tail agnostic, the unmasked instruction should not have a
-  // tied destination.
+  // If this instruction is tail agnostic, the unmasked instruction should not
+  // have a tied destination.
 #ifndef NDEBUG
   const MCInstrDesc &MCID = TII.get(Opc);
   uint64_t TSFlags = MCID.TSFlags;
   bool HasTiedDest = RISCVII::isFirstDefTiedToFirstUse(MCID);
-  assert(UseTUPseudo == HasTiedDest && RISCVII::hasDummyMaskOp(TSFlags) &&
-         "Unexpected pseudo to transform to");
+  assert((UseTUPseudo == HasTiedDest) && "Unexpected pseudo to transform to");
 #endif
 
   SmallVector<SDValue, 8> Ops;