From d227029ce45b3edc5a65f3e293f98b0b6e8f9fc8 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo@fhahn.com>
Date: Fri, 7 Oct 2022 20:42:15 +0100
Subject: [PATCH] [ConstraintElimination] Add test for regression after
 3771310eede.

---
 .../signed-query-unsigned-system.ll               | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/llvm/test/Transforms/ConstraintElimination/signed-query-unsigned-system.ll b/llvm/test/Transforms/ConstraintElimination/signed-query-unsigned-system.ll
index 79fa316b916e9..a7fa432ad20e2 100644
--- a/llvm/test/Transforms/ConstraintElimination/signed-query-unsigned-system.ll
+++ b/llvm/test/Transforms/ConstraintElimination/signed-query-unsigned-system.ll
@@ -142,3 +142,18 @@ define i1 @sgt_0_unsigned_a_ugt_neg_10(i8 %a) {
   %cmp = icmp sgt i16 %ext, 0
   ret i1 %cmp
 }
+
+define i1 @sge_neg_1_sge_0_known(i8 %a) {
+; CHECK-LABEL: @sge_neg_1_sge_0_known(
+; CHECK-NEXT:    [[EXT:%.*]] = zext i8 [[A:%.*]] to i16
+; CHECK-NEXT:    [[A_NE_0:%.*]] = icmp sge i16 [[EXT]], 0
+; CHECK-NEXT:    call void @llvm.assume(i1 [[A_NE_0]])
+; CHECK-NEXT:    [[T:%.*]] = icmp sge i16 [[EXT]], -1
+; CHECK-NEXT:    ret i1 [[T]]
+;
+  %ext = zext i8 %a to i16
+  %a.ne.0 = icmp sge i16 %ext, 0
+  call void @llvm.assume(i1 %a.ne.0)
+  %t = icmp sge i16 %ext, -1
+  ret i1 %t
+}