diff --git a/llvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll b/llvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
index d71b589828a2ee..7179909701ee39 100644
--- a/llvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
+++ b/llvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
@@ -89,17 +89,17 @@ define i32 @load_extract_idx_var_i64_known_valid_by_assume(<4 x i32>* %x, i64 %i
 ; CHECK-LABEL: @load_extract_idx_var_i64_known_valid_by_assume(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i64 [[IDX:%.*]], 4
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
 ; CHECK-NEXT:    [[LV:%.*]] = load <4 x i32>, <4 x i32>* [[X:%.*]], align 16
 ; CHECK-NEXT:    call void @maythrow()
-; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
 ; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x i32> [[LV]], i64 [[IDX]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
 entry:
   %cmp = icmp ult i64 %idx, 4
+  call void @llvm.assume(i1 %cmp)
   %lv = load <4 x i32>, <4 x i32>* %x
   call void @maythrow()
-  call void @llvm.assume(i1 %cmp)
   %r = extractelement <4 x i32> %lv, i64 %idx
   ret i32 %r
 }
@@ -108,15 +108,17 @@ define i32 @load_extract_idx_var_i64_not_known_valid_by_assume_after_load(<4 x i
 ; CHECK-LABEL: @load_extract_idx_var_i64_not_known_valid_by_assume_after_load(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i64 [[IDX:%.*]], 4
-; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
 ; CHECK-NEXT:    [[LV:%.*]] = load <4 x i32>, <4 x i32>* [[X:%.*]], align 16
+; CHECK-NEXT:    call void @maythrow()
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
 ; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x i32> [[LV]], i64 [[IDX]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
 entry:
   %cmp = icmp ult i64 %idx, 4
-  call void @llvm.assume(i1 %cmp)
   %lv = load <4 x i32>, <4 x i32>* %x
+  call void @maythrow()
+  call void @llvm.assume(i1 %cmp)
   %r = extractelement <4 x i32> %lv, i64 %idx
   ret i32 %r
 }