diff --git a/llvm/test/CodeGen/X86/h-register-addressing-32.ll b/llvm/test/CodeGen/X86/h-register-addressing-32.ll
index 8a86a421737ba..b02c7d5276c23 100644
--- a/llvm/test/CodeGen/X86/h-register-addressing-32.ll
+++ b/llvm/test/CodeGen/X86/h-register-addressing-32.ll
@@ -1,74 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-- -mattr=-bmi | FileCheck %s
 
 ; Use h-register extract and zero-extend.
 
 define double @foo8(double* nocapture inreg %p, i32 inreg %x) nounwind readonly {
+; CHECK-LABEL: foo8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movzbl %dh, %ecx
+; CHECK-NEXT:    fldl (%eax,%ecx,8)
+; CHECK-NEXT:    retl
   %t0 = lshr i32 %x, 8
   %t1 = and i32 %t0, 255
   %t2 = getelementptr double, double* %p, i32 %t1
   %t3 = load double, double* %t2, align 8
   ret double %t3
 }
-; CHECK: foo8:
-; CHECK: movzbl %{{[abcd]}}h, %e
 
 define float @foo4(float* nocapture inreg %p, i32 inreg %x) nounwind readonly {
+; CHECK-LABEL: foo4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movzbl %dh, %ecx
+; CHECK-NEXT:    flds (%eax,%ecx,4)
+; CHECK-NEXT:    retl
   %t0 = lshr i32 %x, 8
   %t1 = and i32 %t0, 255
   %t2 = getelementptr float, float* %p, i32 %t1
   %t3 = load float, float* %t2, align 8
   ret float %t3
 }
-; CHECK: foo4:
-; CHECK: movzbl %{{[abcd]}}h, %e
 
 define i16 @foo2(i16* nocapture inreg %p, i32 inreg %x) nounwind readonly {
+; CHECK-LABEL: foo2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movzbl %dh, %ecx
+; CHECK-NEXT:    movzwl (%eax,%ecx,2), %eax
+; CHECK-NEXT:    retl
   %t0 = lshr i32 %x, 8
   %t1 = and i32 %t0, 255
   %t2 = getelementptr i16, i16* %p, i32 %t1
   %t3 = load i16, i16* %t2, align 8
   ret i16 %t3
 }
-; CHECK: foo2:
-; CHECK: movzbl %{{[abcd]}}h, %e
 
 define i8 @foo1(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
+; CHECK-LABEL: foo1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movzbl %dh, %ecx
+; CHECK-NEXT:    movb (%eax,%ecx), %al
+; CHECK-NEXT:    retl
   %t0 = lshr i32 %x, 8
   %t1 = and i32 %t0, 255
   %t2 = getelementptr i8, i8* %p, i32 %t1
   %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
-; CHECK: foo1:
-; CHECK: movzbl %{{[abcd]}}h, %e
 
 define i8 @bar8(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
+; CHECK-LABEL: bar8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movzbl %dh, %ecx
+; CHECK-NEXT:    movb (%eax,%ecx,8), %al
+; CHECK-NEXT:    retl
   %t0 = lshr i32 %x, 5
   %t1 = and i32 %t0, 2040
   %t2 = getelementptr i8, i8* %p, i32 %t1
   %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
-; CHECK: bar8:
-; CHECK: movzbl %{{[abcd]}}h, %e
 
 define i8 @bar4(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
+; CHECK-LABEL: bar4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movzbl %dh, %ecx
+; CHECK-NEXT:    movb (%eax,%ecx,4), %al
+; CHECK-NEXT:    retl
   %t0 = lshr i32 %x, 6
   %t1 = and i32 %t0, 1020
   %t2 = getelementptr i8, i8* %p, i32 %t1
   %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
-; CHECK: bar4:
-; CHECK: movzbl %{{[abcd]}}h, %e
 
 define i8 @bar2(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
+; CHECK-LABEL: bar2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movzbl %dh, %ecx
+; CHECK-NEXT:    movb (%eax,%ecx,2), %al
+; CHECK-NEXT:    retl
   %t0 = lshr i32 %x, 7
   %t1 = and i32 %t0, 510
   %t2 = getelementptr i8, i8* %p, i32 %t1
   %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
-; CHECK: bar2:
-; CHECK: movzbl %{{[abcd]}}h, %e
-; CHECK: ret
diff --git a/llvm/test/CodeGen/X86/h-register-addressing-64.ll b/llvm/test/CodeGen/X86/h-register-addressing-64.ll
index 8d8b44ce28267..158f96d804cd1 100644
--- a/llvm/test/CodeGen/X86/h-register-addressing-64.ll
+++ b/llvm/test/CodeGen/X86/h-register-addressing-64.ll
@@ -1,74 +1,102 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=-bmi | FileCheck %s
 
 ; Use h-register extract and zero-extend.
 
 define double @foo8(double* nocapture inreg %p, i64 inreg %x) nounwind readonly {
+; CHECK-LABEL: foo8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movzbl %ah, %eax
+; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT:    retq
   %t0 = lshr i64 %x, 8
   %t1 = and i64 %t0, 255
   %t2 = getelementptr double, double* %p, i64 %t1
   %t3 = load double, double* %t2, align 8
   ret double %t3
 }
-; CHECK: foo8:
-; CHECK: movzbl %{{[abcd]}}h, %e
 
 define float @foo4(float* nocapture inreg %p, i64 inreg %x) nounwind readonly {
+; CHECK-LABEL: foo4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movzbl %ah, %eax
+; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:    retq
   %t0 = lshr i64 %x, 8
   %t1 = and i64 %t0, 255
   %t2 = getelementptr float, float* %p, i64 %t1
   %t3 = load float, float* %t2, align 8
   ret float %t3
 }
-; CHECK: foo4:
-; CHECK: movzbl %{{[abcd]}}h, %e
 
 define i16 @foo2(i16* nocapture inreg %p, i64 inreg %x) nounwind readonly {
+; CHECK-LABEL: foo2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movzbl %ah, %eax
+; CHECK-NEXT:    movzwl (%rdi,%rax,2), %eax
+; CHECK-NEXT:    retq
   %t0 = lshr i64 %x, 8
   %t1 = and i64 %t0, 255
   %t2 = getelementptr i16, i16* %p, i64 %t1
   %t3 = load i16, i16* %t2, align 8
   ret i16 %t3
 }
-; CHECK: foo2:
-; CHECK: movzbl %{{[abcd]}}h, %e
 
 define i8 @foo1(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
+; CHECK-LABEL: foo1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movzbl %ah, %eax
+; CHECK-NEXT:    movb (%rdi,%rax), %al
+; CHECK-NEXT:    retq
   %t0 = lshr i64 %x, 8
   %t1 = and i64 %t0, 255
   %t2 = getelementptr i8, i8* %p, i64 %t1
   %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
-; CHECK: foo1:
-; CHECK: movzbl %{{[abcd]}}h, %e
 
 define i8 @bar8(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
+; CHECK-LABEL: bar8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movzbl %ah, %eax
+; CHECK-NEXT:    movb (%rdi,%rax,8), %al
+; CHECK-NEXT:    retq
   %t0 = lshr i64 %x, 5
   %t1 = and i64 %t0, 2040
   %t2 = getelementptr i8, i8* %p, i64 %t1
   %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
-; CHECK: bar8:
-; CHECK: movzbl %{{[abcd]}}h, %e
 
 define i8 @bar4(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
+; CHECK-LABEL: bar4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movzbl %ah, %eax
+; CHECK-NEXT:    movb (%rdi,%rax,4), %al
+; CHECK-NEXT:    retq
   %t0 = lshr i64 %x, 6
   %t1 = and i64 %t0, 1020
   %t2 = getelementptr i8, i8* %p, i64 %t1
   %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
-; CHECK: bar4:
-; CHECK: movzbl %{{[abcd]}}h, %e
 
 define i8 @bar2(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
+; CHECK-LABEL: bar2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movzbl %ah, %eax
+; CHECK-NEXT:    movb (%rdi,%rax,2), %al
+; CHECK-NEXT:    retq
   %t0 = lshr i64 %x, 7
   %t1 = and i64 %t0, 510
   %t2 = getelementptr i8, i8* %p, i64 %t1
   %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
-; CHECK: bar2:
-; CHECK: movzbl %{{[abcd]}}h, %e
-; CHECK: ret