From d51da7488949fcf76bc1926a3abf4dffd7e862e7 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Thu, 9 Sep 2021 10:22:29 -0700 Subject: [PATCH] [CodeGen] Use DAG.getAllOnesConstant where possible to simplify code. NFC. --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 5 ++-- .../SelectionDAG/LegalizeVectorOps.cpp | 25 +++++++------------ .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 5 +--- llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +- llvm/lib/Target/Lanai/LanaiISelLowering.cpp | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 2 +- 6 files changed, 15 insertions(+), 26 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index fc866aa567bc3..e8759748ad7fb 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -3240,9 +3240,8 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) { assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && TLI.isOperationLegalOrCustom(ISD::XOR, VT) && "Don't know how to expand this subtraction!"); - Tmp1 = DAG.getNode( - ISD::XOR, dl, VT, Node->getOperand(1), - DAG.getConstant(APInt::getAllOnes(VT.getSizeInBits()), dl, VT)); + Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), + DAG.getAllOnesConstant(dl, VT)); Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT)); Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); break; diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 754af1ea48c7b..b2da5d9e9f1b6 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -943,10 +943,8 @@ SDValue VectorLegalizer::ExpandSELECT(SDNode *Node) { // What is the size of each element in the vector mask. EVT BitTy = MaskTy.getScalarType(); - Mask = DAG.getSelect( - DL, BitTy, Mask, - DAG.getConstant(APInt::getAllOnes(BitTy.getSizeInBits()), DL, BitTy), - DAG.getConstant(0, DL, BitTy)); + Mask = DAG.getSelect(DL, BitTy, Mask, DAG.getAllOnesConstant(DL, BitTy), + DAG.getConstant(0, DL, BitTy)); // Broadcast the mask so that the entire vector is all one or all zero. if (VT.isFixedLengthVector()) @@ -960,8 +958,7 @@ SDValue VectorLegalizer::ExpandSELECT(SDNode *Node) { Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); - SDValue AllOnes = - DAG.getConstant(APInt::getAllOnes(BitTy.getSizeInBits()), DL, MaskTy); + SDValue AllOnes = DAG.getAllOnesConstant(DL, MaskTy); SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes); Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask); @@ -1207,8 +1204,7 @@ SDValue VectorLegalizer::ExpandVSELECT(SDNode *Node) { Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1); Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); - SDValue AllOnes = - DAG.getConstant(APInt::getAllOnes(VT.getScalarSizeInBits()), DL, VT); + SDValue AllOnes = DAG.getAllOnesConstant(DL, VT); SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes); Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask); @@ -1501,10 +1497,9 @@ void VectorLegalizer::UnrollStrictFPOp(SDNode *Node, if (Node->getOpcode() == ISD::STRICT_FSETCC || Node->getOpcode() == ISD::STRICT_FSETCCS) - ScalarResult = DAG.getSelect( - dl, EltVT, ScalarResult, - DAG.getConstant(APInt::getAllOnes(EltVT.getSizeInBits()), dl, EltVT), - DAG.getConstant(0, dl, EltVT)); + ScalarResult = DAG.getSelect(dl, EltVT, ScalarResult, + DAG.getAllOnesConstant(dl, EltVT), + DAG.getConstant(0, dl, EltVT)); OpValues.push_back(ScalarResult); OpChains.push_back(ScalarChain); @@ -1536,10 +1531,8 @@ SDValue VectorLegalizer::UnrollVSETCC(SDNode *Node) { TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), TmpEltVT), LHSElem, RHSElem, CC); - Ops[i] = DAG.getSelect( - dl, EltVT, Ops[i], - DAG.getConstant(APInt::getAllOnes(EltVT.getSizeInBits()), dl, EltVT), - DAG.getConstant(0, dl, EltVT)); + Ops[i] = DAG.getSelect(dl, EltVT, Ops[i], DAG.getAllOnesConstant(dl, EltVT), + DAG.getConstant(0, dl, EltVT)); } return DAG.getBuildVector(VT, dl, Ops); } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 2f4a17054a163..2f9f74eb6a712 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1347,10 +1347,7 @@ SDValue SelectionDAG::getPtrExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) { /// getNOT - Create a bitwise NOT operation as (XOR Val, -1). SDValue SelectionDAG::getNOT(const SDLoc &DL, SDValue Val, EVT VT) { - EVT EltVT = VT.getScalarType(); - SDValue NegOne = - getConstant(APInt::getAllOnes(EltVT.getSizeInBits()), DL, VT); - return getNode(ISD::XOR, DL, VT, Val, NegOne); + return getNode(ISD::XOR, DL, VT, Val, getAllOnesConstant(DL, VT)); } SDValue SelectionDAG::getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT) { diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 0863f8a0bda1f..b814d0563eac3 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -12182,7 +12182,7 @@ static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, // When looking for a 0 constant, N can be zext or sext. OtherOp = DAG.getConstant(1, dl, VT); else - OtherOp = DAG.getConstant(APInt::getAllOnes(VT.getSizeInBits()), dl, VT); + OtherOp = DAG.getAllOnesConstant(dl, VT); return true; } } diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp index 520269bb9da43..19219ba985518 100644 --- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp @@ -1400,7 +1400,7 @@ static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, // value is 0. OtherOp = DAG.getConstant(0, dl, VT); else - OtherOp = DAG.getConstant(APInt::getAllOnes(VT.getSizeInBits()), dl, VT); + OtherOp = DAG.getAllOnesConstant(dl, VT); return true; } } diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index dfd673e17303c..7282c29f17a6b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -41235,7 +41235,7 @@ static SDValue combineMinMaxReduction(SDNode *Extract, SelectionDAG &DAG, else if (BinOp == ISD::SMIN) Mask = DAG.getConstant(APInt::getSignedMinValue(MaskEltsBits), DL, SrcVT); else if (BinOp == ISD::UMAX) - Mask = DAG.getConstant(APInt::getAllOnes(MaskEltsBits), DL, SrcVT); + Mask = DAG.getAllOnesConstant(DL, SrcVT); if (Mask) MinPos = DAG.getNode(ISD::XOR, DL, SrcVT, Mask, MinPos);