From d9c0166f12f0231df0893a397326efb93935ed26 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad@amd.com>
Date: Tue, 8 Aug 2023 17:25:03 +0100
Subject: [PATCH] [MachineScheduler] Rename Reg2SUnitsMap to RegUnit2SUnitsMap

This is a follow up to D156552.
---
 llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h |  6 +++---
 llvm/lib/CodeGen/ScheduleDAGInstrs.cpp        | 12 +++++++-----
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
index abffcd5dca16f..ef7662a8e7a26 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
@@ -88,7 +88,7 @@ namespace llvm {
   /// Use a SparseMultiSet to track physical registers. Storage is only
   /// allocated once for the pass. It can be cleared in constant time and reused
   /// without any frees.
-  using Reg2SUnitsMap =
+  using RegUnit2SUnitsMap =
       SparseMultiSet<PhysRegSUOper, identity<unsigned>, uint16_t>;
 
   /// Use SparseSet as a SparseMap by relying on the fact that it never
@@ -166,8 +166,8 @@ namespace llvm {
     /// iterate upward through the instructions. This is allocated here instead
     /// of inside BuildSchedGraph to avoid the need for it to be initialized and
     /// destructed for each block.
-    Reg2SUnitsMap Defs;
-    Reg2SUnitsMap Uses;
+    RegUnit2SUnitsMap Defs;
+    RegUnit2SUnitsMap Uses;
 
     /// Tracks the last instruction(s) in this region defining each virtual
     /// register. There may be multiple current definitions for a register with
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index a42f842b70df7..d22de53d821fd 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -249,7 +249,8 @@ void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
   bool ImplicitPseudoDef = (OperIdx >= DefMIDesc.getNumOperands() &&
                             !DefMIDesc.hasImplicitDefOfPhysReg(Reg));
   for (MCRegUnit Unit : TRI->regunits(Reg)) {
-    for (Reg2SUnitsMap::iterator I = Uses.find(Unit); I != Uses.end(); ++I) {
+    for (RegUnit2SUnitsMap::iterator I = Uses.find(Unit); I != Uses.end();
+         ++I) {
       SUnit *UseSU = I->SU;
       if (UseSU == SU)
         continue;
@@ -308,7 +309,8 @@ void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
   //       there's no cost for reusing registers.
   SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
   for (MCRegUnit Unit : TRI->regunits(Reg)) {
-    for (Reg2SUnitsMap::iterator I = Defs.find(Unit); I != Defs.end(); ++I) {
+    for (RegUnit2SUnitsMap::iterator I = Defs.find(Unit); I != Defs.end();
+         ++I) {
       SUnit *DefSU = I->SU;
       if (DefSU == &ExitSU)
         continue;
@@ -353,9 +355,9 @@ void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
       // the block. Instead, we leave only one call at the back of the
       // DefList.
       for (MCRegUnit Unit : TRI->regunits(Reg)) {
-        Reg2SUnitsMap::RangePair P = Defs.equal_range(Unit);
-        Reg2SUnitsMap::iterator B = P.first;
-        Reg2SUnitsMap::iterator I = P.second;
+        RegUnit2SUnitsMap::RangePair P = Defs.equal_range(Unit);
+        RegUnit2SUnitsMap::iterator B = P.first;
+        RegUnit2SUnitsMap::iterator I = P.second;
         for (bool isBegin = I == B; !isBegin; /* empty */) {
           isBegin = (--I) == B;
           if (!I->SU->isCall)